1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III 4 * systems. 5 * 6 * Copyright (C) 2000 David S. Miller (davem@redhat.com) 7 */ 8 9 #ifndef _SPARC64_BBC_H 10 #define _SPARC64_BBC_H 11 12 /* Register sizes are indicated by "B" (Byte, 1-byte), 13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or 14 * "Q" (Quad, 8 bytes) inside brackets. 15 */ 16 17 #define BBC_AID 0x00 /* [B] Agent ID */ 18 #define BBC_DEVP 0x01 /* [B] Device Present */ 19 #define BBC_ARB 0x02 /* [B] Arbitration */ 20 #define BBC_QUIESCE 0x03 /* [B] Quiesce */ 21 #define BBC_WDACTION 0x04 /* [B] Watchdog Action */ 22 #define BBC_SPG 0x06 /* [B] Soft POR Gen */ 23 #define BBC_SXG 0x07 /* [B] Soft XIR Gen */ 24 #define BBC_PSRC 0x08 /* [W] POR Source */ 25 #define BBC_XSRC 0x0c /* [B] XIR Source */ 26 #define BBC_CSC 0x0d /* [B] Clock Synthesizers Control*/ 27 #define BBC_ES_CTRL 0x0e /* [H] Energy Star Control */ 28 #define BBC_ES_ACT 0x10 /* [W] E* Assert Change Time */ 29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */ 30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */ 31 #define BBC_ES_ABT 0x16 /* [H] E* Assert Bypass Time */ 32 #define BBC_ES_PST 0x18 /* [W] E* PLL Settle Time */ 33 #define BBC_ES_FSL 0x1c /* [W] E* Frequency Switch Latency*/ 34 #define BBC_EBUST 0x20 /* [Q] EBUS Timing */ 35 #define BBC_JTAG_CMD 0x28 /* [W] JTAG+ Command */ 36 #define BBC_JTAG_CTRL 0x2c /* [B] JTAG+ Control */ 37 #define BBC_I2C_SEL 0x2d /* [B] I2C Selection */ 38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */ 39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/ 40 #define BBC_I2C_1_S1 0x30 /* [B] I2C ctrlr-1 reg S1 */ 41 #define BBC_I2C_1_S0 0x31 /* [B] I2C ctrlr-1 regs S0,S0',S2,S3*/ 42 #define BBC_KBD_BEEP 0x32 /* [B] Keyboard Beep */ 43 #define BBC_KBD_BCNT 0x34 /* [W] Keyboard Beep Counter */ 44 45 #define BBC_REGS_SIZE 0x40 46 47 /* There is a 2K scratch ram area at offset 0x80000 but I doubt 48 * we will use it for anything. 49 */ 50 51 /* Agent ID register. This register shows the Safari Agent ID 52 * for the processors. The value returned depends upon which 53 * cpu is reading the register. 54 */ 55 #define BBC_AID_ID 0x07 /* Safari ID */ 56 #define BBC_AID_RESV 0xf8 /* Reserved */ 57 58 /* Device Present register. One can determine which cpus are actually 59 * present in the machine by interrogating this register. 60 */ 61 #define BBC_DEVP_CPU0 0x01 /* Processor 0 present */ 62 #define BBC_DEVP_CPU1 0x02 /* Processor 1 present */ 63 #define BBC_DEVP_CPU2 0x04 /* Processor 2 present */ 64 #define BBC_DEVP_CPU3 0x08 /* Processor 3 present */ 65 #define BBC_DEVP_RESV 0xf0 /* Reserved */ 66 67 /* Arbitration register. This register is used to block access to 68 * the BBC from a particular cpu. 69 */ 70 #define BBC_ARB_CPU0 0x01 /* Enable cpu 0 BBC arbitratrion */ 71 #define BBC_ARB_CPU1 0x02 /* Enable cpu 1 BBC arbitratrion */ 72 #define BBC_ARB_CPU2 0x04 /* Enable cpu 2 BBC arbitratrion */ 73 #define BBC_ARB_CPU3 0x08 /* Enable cpu 3 BBC arbitratrion */ 74 #define BBC_ARB_RESV 0xf0 /* Reserved */ 75 76 /* Quiesce register. Bus and BBC segments for cpus can be disabled 77 * with this register, ie. for hot plugging. 78 */ 79 #define BBC_QUIESCE_S02 0x01 /* Quiesce Safari segment for cpu 0 and 2 */ 80 #define BBC_QUIESCE_S13 0x02 /* Quiesce Safari segment for cpu 1 and 3 */ 81 #define BBC_QUIESCE_B02 0x04 /* Quiesce BBC segment for cpu 0 and 2 */ 82 #define BBC_QUIESCE_B13 0x08 /* Quiesce BBC segment for cpu 1 and 3 */ 83 #define BBC_QUIESCE_FD0 0x10 /* Disable Fatal_Error[0] reporting */ 84 #define BBC_QUIESCE_FD1 0x20 /* Disable Fatal_Error[1] reporting */ 85 #define BBC_QUIESCE_FD2 0x40 /* Disable Fatal_Error[2] reporting */ 86 #define BBC_QUIESCE_FD3 0x80 /* Disable Fatal_Error[3] reporting */ 87 88 /* Watchdog Action register. When the watchdog device timer expires 89 * a line is enabled to the BBC. The action BBC takes when this line 90 * is asserted can be controlled by this regiser. 91 */ 92 #define BBC_WDACTION_RST 0x01 /* When set, watchdog causes system reset. 93 * When clear, BBC ignores watchdog signal. 94 */ 95 #define BBC_WDACTION_RESV 0xfe /* Reserved */ 96 97 /* Soft_POR_GEN register. The POR (Power On Reset) signal may be asserted 98 * for specific processors or all processors via this register. 99 */ 100 #define BBC_SPG_CPU0 0x01 /* Assert POR for processor 0 */ 101 #define BBC_SPG_CPU1 0x02 /* Assert POR for processor 1 */ 102 #define BBC_SPG_CPU2 0x04 /* Assert POR for processor 2 */ 103 #define BBC_SPG_CPU3 0x08 /* Assert POR for processor 3 */ 104 #define BBC_SPG_CPUALL 0x10 /* Reset all processors and reset 105 * the entire system. 106 */ 107 #define BBC_SPG_RESV 0xe0 /* Reserved */ 108 109 /* Soft_XIR_GEN register. The XIR (eXternally Initiated Reset) signal 110 * may be asserted to specific processors via this register. 111 */ 112 #define BBC_SXG_CPU0 0x01 /* Assert XIR for processor 0 */ 113 #define BBC_SXG_CPU1 0x02 /* Assert XIR for processor 1 */ 114 #define BBC_SXG_CPU2 0x04 /* Assert XIR for processor 2 */ 115 #define BBC_SXG_CPU3 0x08 /* Assert XIR for processor 3 */ 116 #define BBC_SXG_RESV 0xf0 /* Reserved */ 117 118 /* POR Source register. One may identify the cause of the most recent 119 * reset by reading this register. 120 */ 121 #define BBC_PSRC_SPG0 0x0001 /* CPU 0 reset via BBC_SPG register */ 122 #define BBC_PSRC_SPG1 0x0002 /* CPU 1 reset via BBC_SPG register */ 123 #define BBC_PSRC_SPG2 0x0004 /* CPU 2 reset via BBC_SPG register */ 124 #define BBC_PSRC_SPG3 0x0008 /* CPU 3 reset via BBC_SPG register */ 125 #define BBC_PSRC_SPGSYS 0x0010 /* System reset via BBC_SPG register */ 126 #define BBC_PSRC_JTAG 0x0020 /* System reset via JTAG+ */ 127 #define BBC_PSRC_BUTTON 0x0040 /* System reset via push-button dongle */ 128 #define BBC_PSRC_PWRUP 0x0080 /* System reset via power-up */ 129 #define BBC_PSRC_FE0 0x0100 /* CPU 0 reported Fatal_Error */ 130 #define BBC_PSRC_FE1 0x0200 /* CPU 1 reported Fatal_Error */ 131 #define BBC_PSRC_FE2 0x0400 /* CPU 2 reported Fatal_Error */ 132 #define BBC_PSRC_FE3 0x0800 /* CPU 3 reported Fatal_Error */ 133 #define BBC_PSRC_FE4 0x1000 /* Schizo reported Fatal_Error */ 134 #define BBC_PSRC_FE5 0x2000 /* Safari device 5 reported Fatal_Error */ 135 #define BBC_PSRC_FE6 0x4000 /* CPMS reported Fatal_Error */ 136 #define BBC_PSRC_SYNTH 0x8000 /* System reset when on-board clock synthesizers 137 * were updated. 138 */ 139 #define BBC_PSRC_WDT 0x10000 /* System reset via Super I/O watchdog */ 140 #define BBC_PSRC_RSC 0x20000 /* System reset via RSC remote monitoring 141 * device 142 */ 143 144 /* XIR Source register. The source of an XIR event sent to a processor may 145 * be determined via this register. 146 */ 147 #define BBC_XSRC_SXG0 0x01 /* CPU 0 received XIR via Soft_XIR_GEN reg */ 148 #define BBC_XSRC_SXG1 0x02 /* CPU 1 received XIR via Soft_XIR_GEN reg */ 149 #define BBC_XSRC_SXG2 0x04 /* CPU 2 received XIR via Soft_XIR_GEN reg */ 150 #define BBC_XSRC_SXG3 0x08 /* CPU 3 received XIR via Soft_XIR_GEN reg */ 151 #define BBC_XSRC_JTAG 0x10 /* All CPUs received XIR via JTAG+ */ 152 #define BBC_XSRC_W_OR_B 0x20 /* All CPUs received XIR either because: 153 * a) Super I/O watchdog fired, or 154 * b) XIR push button was activated 155 */ 156 #define BBC_XSRC_RESV 0xc0 /* Reserved */ 157 158 /* Clock Synthesizers Control register. This register provides the big-bang 159 * programming interface to the two clock synthesizers of the machine. 160 */ 161 #define BBC_CSC_SLOAD 0x01 /* Directly connected to S_LOAD pins */ 162 #define BBC_CSC_SDATA 0x02 /* Directly connected to S_DATA pins */ 163 #define BBC_CSC_SCLOCK 0x04 /* Directly connected to S_CLOCK pins */ 164 #define BBC_CSC_RESV 0x78 /* Reserved */ 165 #define BBC_CSC_RST 0x80 /* Generate system reset when S_LOAD==1 */ 166 167 /* Energy Star Control register. This register is used to generate the 168 * clock frequency change trigger to the main system devices (Schizo and 169 * the processors). The transition occurs when bits in this register 170 * go from 0 to 1, only one bit must be set at once else no action 171 * occurs. Basically the sequence of events is: 172 * a) Choose new frequency: full, 1/2 or 1/32 173 * b) Program this desired frequency into the cpus and Schizo. 174 * c) Set the same value in this register. 175 * d) 16 system clocks later, clear this register. 176 */ 177 #define BBC_ES_CTRL_1_1 0x01 /* Full frequency */ 178 #define BBC_ES_CTRL_1_2 0x02 /* 1/2 frequency */ 179 #define BBC_ES_CTRL_1_32 0x20 /* 1/32 frequency */ 180 #define BBC_ES_RESV 0xdc /* Reserved */ 181 182 /* Energy Star Assert Change Time register. This determines the number 183 * of BBC clock cycles (which is half the system frequency) between 184 * the detection of FREEZE_ACK being asserted and the assertion of 185 * the CLK_CHANGE_L[2:0] signals. 186 */ 187 #define BBC_ES_ACT_VAL 0xff 188 189 /* Energy Star Assert Bypass Time register. This determines the number 190 * of BBC clock cycles (which is half the system frequency) between 191 * the assertion of the CLK_CHANGE_L[2:0] signals and the assertion of 192 * the ESTAR_PLL_BYPASS signal. 193 */ 194 #define BBC_ES_ABT_VAL 0xffff 195 196 /* Energy Star PLL Settle Time register. This determines the number of 197 * BBC clock cycles (which is half the system frequency) between the 198 * de-assertion of CLK_CHANGE_L[2:0] and the de-assertion of the FREEZE_L 199 * signal. 200 */ 201 #define BBC_ES_PST_VAL 0xffffffff 202 203 /* Energy Star Frequency Switch Latency register. This is the number of 204 * BBC clocks between the de-assertion of CLK_CHANGE_L[2:0] and the first 205 * edge of the Safari clock at the new frequency. 206 */ 207 #define BBC_ES_FSL_VAL 0xffffffff 208 209 /* Keyboard Beep control register. This is a simple enabler for the audio 210 * beep sound. 211 */ 212 #define BBC_KBD_BEEP_ENABLE 0x01 /* Enable beep */ 213 #define BBC_KBD_BEEP_RESV 0xfe /* Reserved */ 214 215 /* Keyboard Beep Counter register. There is a free-running counter inside 216 * the BBC which runs at half the system clock. The bit set in this register 217 * determines when the audio sound is generated. So for example if bit 218 * 10 is set, the audio beep will oscillate at 1/(2**12). The keyboard beep 219 * generator automatically selects a different bit to use if the system clock 220 * is changed via Energy Star. 221 */ 222 #define BBC_KBD_BCNT_BITS 0x0007fc00 223 #define BBC_KBC_BCNT_RESV 0xfff803ff 224 225 #endif /* _SPARC64_BBC_H */ 226 227