xref: /openbmc/linux/arch/sparc/include/asm/auxio_64.h (revision b2441318)
1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2a439fe51SSam Ravnborg /*
3a439fe51SSam Ravnborg  * auxio.h:  Definitions and code for the Auxiliary I/O registers.
4a439fe51SSam Ravnborg  *
5a439fe51SSam Ravnborg  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6a439fe51SSam Ravnborg  *
7a439fe51SSam Ravnborg  * Refactoring for unified NCR/PCIO support 2002 Eric Brower (ebrower@usa.net)
8a439fe51SSam Ravnborg  */
9a439fe51SSam Ravnborg #ifndef _SPARC64_AUXIO_H
10a439fe51SSam Ravnborg #define _SPARC64_AUXIO_H
11a439fe51SSam Ravnborg 
12a439fe51SSam Ravnborg /* AUXIO implementations:
13a439fe51SSam Ravnborg  * sbus-based NCR89C105 "Slavio"
14a439fe51SSam Ravnborg  *	LED/Floppy (AUX1) register
15a439fe51SSam Ravnborg  *	Power (AUX2) register
16a439fe51SSam Ravnborg  *
17a439fe51SSam Ravnborg  * ebus-based auxio on PCIO
18a439fe51SSam Ravnborg  *	LED Auxio Register
19a439fe51SSam Ravnborg  *	Power Auxio Register
20a439fe51SSam Ravnborg  *
21a439fe51SSam Ravnborg  * Register definitions from NCR _NCR89C105 Chip Specification_
22a439fe51SSam Ravnborg  *
23a439fe51SSam Ravnborg  * SLAVIO AUX1 @ 0x1900000
24a439fe51SSam Ravnborg  * -------------------------------------------------
25a439fe51SSam Ravnborg  * | (R) | (R) |  D  | (R) |  E  |  M  |  T  |  L  |
26a439fe51SSam Ravnborg  * -------------------------------------------------
27a439fe51SSam Ravnborg  * (R) - bit 7:6,4 are reserved and should be masked in s/w
28a439fe51SSam Ravnborg  *  D  - Floppy Density Sense (1=high density) R/O
29a439fe51SSam Ravnborg  *  E  - Link Test Enable, directly reflected on AT&T 7213 LTE pin
30a439fe51SSam Ravnborg  *  M  - Monitor/Mouse Mux, directly reflected on MON_MSE_MUX pin
31a439fe51SSam Ravnborg  *  T  - Terminal Count: sends TC pulse to 82077 floppy controller
32a439fe51SSam Ravnborg  *  L  - System LED on front panel (0=off, 1=on)
33a439fe51SSam Ravnborg  */
34a439fe51SSam Ravnborg #define AUXIO_AUX1_MASK		0xc0 /* Mask bits 		*/
35a439fe51SSam Ravnborg #define AUXIO_AUX1_FDENS	0x20 /* Floppy Density Sense	*/
36a439fe51SSam Ravnborg #define AUXIO_AUX1_LTE 		0x08 /* Link Test Enable 	*/
37a439fe51SSam Ravnborg #define AUXIO_AUX1_MMUX		0x04 /* Monitor/Mouse Mux	*/
38a439fe51SSam Ravnborg #define AUXIO_AUX1_FTCNT	0x02 /* Terminal Count, 	*/
39a439fe51SSam Ravnborg #define AUXIO_AUX1_LED		0x01 /* System LED		*/
40a439fe51SSam Ravnborg 
41a439fe51SSam Ravnborg /* SLAVIO AUX2 @ 0x1910000
42a439fe51SSam Ravnborg  * -------------------------------------------------
43a439fe51SSam Ravnborg  * | (R) | (R) |  D  | (R) | (R) | (R) |  C  |  F  |
44a439fe51SSam Ravnborg  * -------------------------------------------------
45a439fe51SSam Ravnborg  * (R) - bits 7:6,4:2 are reserved and should be masked in s/w
46a439fe51SSam Ravnborg  *  D  - Power Failure Detect (1=power fail)
47a439fe51SSam Ravnborg  *  C  - Clear Power Failure Detect Int (1=clear)
48a439fe51SSam Ravnborg  *  F  - Power Off (1=power off)
49a439fe51SSam Ravnborg  */
50a439fe51SSam Ravnborg #define AUXIO_AUX2_MASK		0xdc /* Mask Bits		*/
51a439fe51SSam Ravnborg #define AUXIO_AUX2_PFAILDET	0x20 /* Power Fail Detect	*/
52a439fe51SSam Ravnborg #define AUXIO_AUX2_PFAILCLR 	0x02 /* Clear Pwr Fail Det Intr	*/
53a439fe51SSam Ravnborg #define AUXIO_AUX2_PWR_OFF	0x01 /* Power Off		*/
54a439fe51SSam Ravnborg 
55a439fe51SSam Ravnborg /* Register definitions from Sun Microsystems _PCIO_ p/n 802-7837
56a439fe51SSam Ravnborg  *
57a439fe51SSam Ravnborg  * PCIO LED Auxio @ 0x726000
58a439fe51SSam Ravnborg  * -------------------------------------------------
59a439fe51SSam Ravnborg  * |             31:1 Unused                 | LED |
60a439fe51SSam Ravnborg  * -------------------------------------------------
61a439fe51SSam Ravnborg  * Bits 31:1 unused
62a439fe51SSam Ravnborg  * LED - System LED on front panel (0=off, 1=on)
63a439fe51SSam Ravnborg  */
64a439fe51SSam Ravnborg #define AUXIO_PCIO_LED		0x01 /* System LED 		*/
65a439fe51SSam Ravnborg 
66a439fe51SSam Ravnborg /* PCIO Power Auxio @ 0x724000
67a439fe51SSam Ravnborg  * -------------------------------------------------
68a439fe51SSam Ravnborg  * |             31:2 Unused           | CPO | SPO |
69a439fe51SSam Ravnborg  * -------------------------------------------------
70a439fe51SSam Ravnborg  * Bits 31:2 unused
71a439fe51SSam Ravnborg  * CPO - Courtesy Power Off (1=off)
72a439fe51SSam Ravnborg  * SPO - System Power Off   (1=off)
73a439fe51SSam Ravnborg  */
74a439fe51SSam Ravnborg #define AUXIO_PCIO_CPWR_OFF	0x02 /* Courtesy Power Off	*/
75a439fe51SSam Ravnborg #define AUXIO_PCIO_SPWR_OFF	0x01 /* System Power Off	*/
76a439fe51SSam Ravnborg 
77a439fe51SSam Ravnborg #ifndef __ASSEMBLY__
78a439fe51SSam Ravnborg 
79a439fe51SSam Ravnborg #define AUXIO_LTE_ON	1
80a439fe51SSam Ravnborg #define AUXIO_LTE_OFF	0
81a439fe51SSam Ravnborg 
82a439fe51SSam Ravnborg /* auxio_set_lte - Set Link Test Enable (TPE Link Detect)
83a439fe51SSam Ravnborg  *
84a439fe51SSam Ravnborg  * on - AUXIO_LTE_ON or AUXIO_LTE_OFF
85a439fe51SSam Ravnborg  */
86f05a6865SSam Ravnborg void auxio_set_lte(int on);
87a439fe51SSam Ravnborg 
88a439fe51SSam Ravnborg #define AUXIO_LED_ON	1
89a439fe51SSam Ravnborg #define AUXIO_LED_OFF	0
90a439fe51SSam Ravnborg 
91a439fe51SSam Ravnborg /* auxio_set_led - Set system front panel LED
92a439fe51SSam Ravnborg  *
93a439fe51SSam Ravnborg  * on - AUXIO_LED_ON or AUXIO_LED_OFF
94a439fe51SSam Ravnborg  */
95f05a6865SSam Ravnborg void auxio_set_led(int on);
96a439fe51SSam Ravnborg 
97a439fe51SSam Ravnborg #endif /* ifndef __ASSEMBLY__ */
98a439fe51SSam Ravnborg 
99a439fe51SSam Ravnborg #endif /* !(_SPARC64_AUXIO_H) */
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