xref: /openbmc/linux/arch/sh/mm/Kconfig (revision f20c7d91) 
1# SPDX-License-Identifier: GPL-2.0
2menu "Memory management options"
3
4config MMU
5        bool "Support for memory management hardware"
6	depends on !CPU_SH2
7	default y
8	help
9	  Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
10	  boot on these systems, this option must not be set.
11
12	  On other systems (such as the SH-3 and 4) where an MMU exists,
13	  turning this off will boot the kernel on these machines with the
14	  MMU implicitly switched off.
15
16config PAGE_OFFSET
17	hex
18	default "0x80000000" if MMU
19	default "0x00000000"
20
21config FORCE_MAX_ZONEORDER
22	int "Maximum zone order"
23	range 9 64 if PAGE_SIZE_16KB
24	default "9" if PAGE_SIZE_16KB
25	range 7 64 if PAGE_SIZE_64KB
26	default "7" if PAGE_SIZE_64KB
27	range 11 64
28	default "14" if !MMU
29	default "11"
30	help
31	  The kernel memory allocator divides physically contiguous memory
32	  blocks into "zones", where each zone is a power of two number of
33	  pages.  This option selects the largest power of two that the kernel
34	  keeps in the memory allocator.  If you need to allocate very large
35	  blocks of physically contiguous memory, then you may need to
36	  increase this value.
37
38	  This config option is actually maximum order plus one. For example,
39	  a value of 11 means that the largest free memory block is 2^10 pages.
40
41	  The page size is not necessarily 4KB. Keep this in mind when
42	  choosing a value for this option.
43
44config MEMORY_START
45	hex "Physical memory start address"
46	default "0x08000000"
47	help
48	  Computers built with Hitachi SuperH processors always
49	  map the ROM starting at address zero.  But the processor
50	  does not specify the range that RAM takes.
51
52	  The physical memory (RAM) start address will be automatically
53	  set to 08000000. Other platforms, such as the Solution Engine
54	  boards typically map RAM at 0C000000.
55
56	  Tweak this only when porting to a new machine which does not
57	  already have a defconfig. Changing it from the known correct
58	  value on any of the known systems will only lead to disaster.
59
60config MEMORY_SIZE
61	hex "Physical memory size"
62	default "0x04000000"
63	help
64	  This sets the default memory size assumed by your SH kernel. It can
65	  be overridden as normal by the 'mem=' argument on the kernel command
66	  line. If unsure, consult your board specifications or just leave it
67	  as 0x04000000 which was the default value before this became
68	  configurable.
69
70# Physical addressing modes
71
72config 29BIT
73	def_bool !32BIT
74	select UNCACHED_MAPPING
75
76config 32BIT
77	bool
78	default !MMU
79
80config PMB
81	bool "Support 32-bit physical addressing through PMB"
82	depends on MMU && CPU_SH4A && !CPU_SH4AL_DSP
83	select 32BIT
84	select UNCACHED_MAPPING
85	help
86	  If you say Y here, physical addressing will be extended to
87	  32-bits through the SH-4A PMB. If this is not set, legacy
88	  29-bit physical addressing will be used.
89
90config X2TLB
91	def_bool y
92	depends on (CPU_SHX2 || CPU_SHX3) && MMU
93
94config VSYSCALL
95	bool "Support vsyscall page"
96	depends on MMU && (CPU_SH3 || CPU_SH4)
97	default y
98	help
99	  This will enable support for the kernel mapping a vDSO page
100	  in process space, and subsequently handing down the entry point
101	  to the libc through the ELF auxiliary vector.
102
103	  From the kernel side this is used for the signal trampoline.
104	  For systems with an MMU that can afford to give up a page,
105	  (the default value) say Y.
106
107config NUMA
108	bool "Non Uniform Memory Access (NUMA) Support"
109	depends on MMU && SYS_SUPPORTS_NUMA
110	select ARCH_WANT_NUMA_VARIABLE_LOCALITY
111	default n
112	help
113	  Some SH systems have many various memories scattered around
114	  the address space, each with varying latencies. This enables
115	  support for these blocks by binding them to nodes and allowing
116	  memory policies to be used for prioritizing and controlling
117	  allocation behaviour.
118
119config NODES_SHIFT
120	int
121	default "3" if CPU_SUBTYPE_SHX3
122	default "1"
123	depends on NEED_MULTIPLE_NODES
124
125config ARCH_FLATMEM_ENABLE
126	def_bool y
127	depends on !NUMA
128
129config ARCH_SPARSEMEM_ENABLE
130	def_bool y
131	select SPARSEMEM_STATIC
132
133config ARCH_SPARSEMEM_DEFAULT
134	def_bool y
135
136config ARCH_SELECT_MEMORY_MODEL
137	def_bool y
138
139config ARCH_ENABLE_MEMORY_HOTPLUG
140	def_bool y
141	depends on SPARSEMEM && MMU
142
143config ARCH_ENABLE_MEMORY_HOTREMOVE
144	def_bool y
145	depends on SPARSEMEM && MMU
146
147config ARCH_MEMORY_PROBE
148	def_bool y
149	depends on MEMORY_HOTPLUG
150
151config IOREMAP_FIXED
152       def_bool y
153       depends on X2TLB
154
155config UNCACHED_MAPPING
156	bool
157
158config HAVE_SRAM_POOL
159	bool
160	select GENERIC_ALLOCATOR
161
162choice
163	prompt "Kernel page size"
164	default PAGE_SIZE_4KB
165
166config PAGE_SIZE_4KB
167	bool "4kB"
168	help
169	  This is the default page size used by all SuperH CPUs.
170
171config PAGE_SIZE_8KB
172	bool "8kB"
173	depends on !MMU || X2TLB
174	help
175	  This enables 8kB pages as supported by SH-X2 and later MMUs.
176
177config PAGE_SIZE_16KB
178	bool "16kB"
179	depends on !MMU
180	help
181	  This enables 16kB pages on MMU-less SH systems.
182
183config PAGE_SIZE_64KB
184	bool "64kB"
185	depends on !MMU || CPU_SH4
186	help
187	  This enables support for 64kB pages, possible on all SH-4
188	  CPUs and later.
189
190endchoice
191
192choice
193	prompt "HugeTLB page size"
194	depends on HUGETLB_PAGE
195	default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB
196	default HUGETLB_PAGE_SIZE_64K
197
198config HUGETLB_PAGE_SIZE_64K
199	bool "64kB"
200	depends on !PAGE_SIZE_64KB
201
202config HUGETLB_PAGE_SIZE_256K
203	bool "256kB"
204	depends on X2TLB
205
206config HUGETLB_PAGE_SIZE_1MB
207	bool "1MB"
208
209config HUGETLB_PAGE_SIZE_4MB
210	bool "4MB"
211	depends on X2TLB
212
213config HUGETLB_PAGE_SIZE_64MB
214	bool "64MB"
215	depends on X2TLB
216
217endchoice
218
219config SCHED_MC
220	bool "Multi-core scheduler support"
221	depends on SMP
222	default y
223	help
224	  Multi-core scheduler support improves the CPU scheduler's decision
225	  making when dealing with multi-core CPU chips at a cost of slightly
226	  increased overhead in some places. If unsure say N here.
227
228endmenu
229
230menu "Cache configuration"
231
232config SH7705_CACHE_32KB
233	bool "Enable 32KB cache size for SH7705"
234	depends on CPU_SUBTYPE_SH7705
235	default y
236
237choice
238	prompt "Cache mode"
239	default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4
240	default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
241
242config CACHE_WRITEBACK
243	bool "Write-back"
244
245config CACHE_WRITETHROUGH
246	bool "Write-through"
247	help
248	  Selecting this option will configure the caches in write-through
249	  mode, as opposed to the default write-back configuration.
250
251	  Since there's sill some aliasing issues on SH-4, this option will
252	  unfortunately still require the majority of flushing functions to
253	  be implemented to deal with aliasing.
254
255	  If unsure, say N.
256
257config CACHE_OFF
258	bool "Off"
259
260endchoice
261
262endmenu
263