xref: /openbmc/linux/arch/sh/mm/Kconfig (revision e8e0929d) 
1menu "Memory management options"
2
3config QUICKLIST
4	def_bool y
5
6config MMU
7        bool "Support for memory management hardware"
8	depends on !CPU_SH2
9	default y
10	help
11	  Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
12	  boot on these systems, this option must not be set.
13
14	  On other systems (such as the SH-3 and 4) where an MMU exists,
15	  turning this off will boot the kernel on these machines with the
16	  MMU implicitly switched off.
17
18config PAGE_OFFSET
19	hex
20	default "0x80000000" if MMU && SUPERH32
21	default "0x20000000" if MMU && SUPERH64
22	default "0x00000000"
23
24config FORCE_MAX_ZONEORDER
25	int "Maximum zone order"
26	range 9 64 if PAGE_SIZE_16KB
27	default "9" if PAGE_SIZE_16KB
28	range 7 64 if PAGE_SIZE_64KB
29	default "7" if PAGE_SIZE_64KB
30	range 11 64
31	default "14" if !MMU
32	default "11"
33	help
34	  The kernel memory allocator divides physically contiguous memory
35	  blocks into "zones", where each zone is a power of two number of
36	  pages.  This option selects the largest power of two that the kernel
37	  keeps in the memory allocator.  If you need to allocate very large
38	  blocks of physically contiguous memory, then you may need to
39	  increase this value.
40
41	  This config option is actually maximum order plus one. For example,
42	  a value of 11 means that the largest free memory block is 2^10 pages.
43
44	  The page size is not necessarily 4KB. Keep this in mind when
45	  choosing a value for this option.
46
47config MEMORY_START
48	hex "Physical memory start address"
49	default "0x08000000"
50	---help---
51	  Computers built with Hitachi SuperH processors always
52	  map the ROM starting at address zero.  But the processor
53	  does not specify the range that RAM takes.
54
55	  The physical memory (RAM) start address will be automatically
56	  set to 08000000. Other platforms, such as the Solution Engine
57	  boards typically map RAM at 0C000000.
58
59	  Tweak this only when porting to a new machine which does not
60	  already have a defconfig. Changing it from the known correct
61	  value on any of the known systems will only lead to disaster.
62
63config MEMORY_SIZE
64	hex "Physical memory size"
65	default "0x04000000"
66	help
67	  This sets the default memory size assumed by your SH kernel. It can
68	  be overridden as normal by the 'mem=' argument on the kernel command
69	  line. If unsure, consult your board specifications or just leave it
70	  as 0x04000000 which was the default value before this became
71	  configurable.
72
73# Physical addressing modes
74
75config 29BIT
76	def_bool !32BIT
77	depends on SUPERH32
78
79config 32BIT
80	bool
81	default y if CPU_SH5
82
83config PMB_ENABLE
84	bool "Support 32-bit physical addressing through PMB"
85	depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
86	select 32BIT
87	default y
88	help
89	  If you say Y here, physical addressing will be extended to
90	  32-bits through the SH-4A PMB. If this is not set, legacy
91	  29-bit physical addressing will be used.
92
93choice
94	prompt "PMB handling type"
95	depends on PMB_ENABLE
96	default PMB_FIXED
97
98config PMB
99	bool "PMB"
100	depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
101	select 32BIT
102	help
103	  If you say Y here, physical addressing will be extended to
104	  32-bits through the SH-4A PMB. If this is not set, legacy
105	  29-bit physical addressing will be used.
106
107config PMB_FIXED
108	bool "fixed PMB"
109	depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || \
110					   CPU_SUBTYPE_SH7780 || \
111					   CPU_SUBTYPE_SH7785)
112	select 32BIT
113	help
114	  If this option is enabled, fixed PMB mappings are inherited
115	  from the boot loader, and the kernel does not attempt dynamic
116	  management. This is the closest to legacy 29-bit physical mode,
117	  and allows systems to support up to 512MiB of system memory.
118
119endchoice
120
121config X2TLB
122	bool "Enable extended TLB mode"
123	depends on (CPU_SHX2 || CPU_SHX3) && MMU && EXPERIMENTAL
124	help
125	  Selecting this option will enable the extended mode of the SH-X2
126	  TLB. For legacy SH-X behaviour and interoperability, say N. For
127	  all of the fun new features and a willingless to submit bug reports,
128	  say Y.
129
130config VSYSCALL
131	bool "Support vsyscall page"
132	depends on MMU && (CPU_SH3 || CPU_SH4)
133	default y
134	help
135	  This will enable support for the kernel mapping a vDSO page
136	  in process space, and subsequently handing down the entry point
137	  to the libc through the ELF auxiliary vector.
138
139	  From the kernel side this is used for the signal trampoline.
140	  For systems with an MMU that can afford to give up a page,
141	  (the default value) say Y.
142
143config NUMA
144	bool "Non Uniform Memory Access (NUMA) Support"
145	depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
146	default n
147	help
148	  Some SH systems have many various memories scattered around
149	  the address space, each with varying latencies. This enables
150	  support for these blocks by binding them to nodes and allowing
151	  memory policies to be used for prioritizing and controlling
152	  allocation behaviour.
153
154config NODES_SHIFT
155	int
156	default "3" if CPU_SUBTYPE_SHX3
157	default "1"
158	depends on NEED_MULTIPLE_NODES
159
160config ARCH_FLATMEM_ENABLE
161	def_bool y
162	depends on !NUMA
163
164config ARCH_SPARSEMEM_ENABLE
165	def_bool y
166	select SPARSEMEM_STATIC
167
168config ARCH_SPARSEMEM_DEFAULT
169	def_bool y
170
171config MAX_ACTIVE_REGIONS
172	int
173	default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM)
174	default "2" if SPARSEMEM && (CPU_SUBTYPE_SH7722 || \
175		       CPU_SUBTYPE_SH7785)
176	default "1"
177
178config ARCH_POPULATES_NODE_MAP
179	def_bool y
180
181config ARCH_SELECT_MEMORY_MODEL
182	def_bool y
183
184config ARCH_ENABLE_MEMORY_HOTPLUG
185	def_bool y
186	depends on SPARSEMEM && MMU
187
188config ARCH_ENABLE_MEMORY_HOTREMOVE
189	def_bool y
190	depends on SPARSEMEM && MMU
191
192config ARCH_MEMORY_PROBE
193	def_bool y
194	depends on MEMORY_HOTPLUG
195
196choice
197	prompt "Kernel page size"
198	default PAGE_SIZE_8KB if X2TLB
199	default PAGE_SIZE_4KB
200
201config PAGE_SIZE_4KB
202	bool "4kB"
203	depends on !MMU || !X2TLB
204	help
205	  This is the default page size used by all SuperH CPUs.
206
207config PAGE_SIZE_8KB
208	bool "8kB"
209	depends on !MMU || X2TLB
210	help
211	  This enables 8kB pages as supported by SH-X2 and later MMUs.
212
213config PAGE_SIZE_16KB
214	bool "16kB"
215	depends on !MMU
216	help
217	  This enables 16kB pages on MMU-less SH systems.
218
219config PAGE_SIZE_64KB
220	bool "64kB"
221	depends on !MMU || CPU_SH4 || CPU_SH5
222	help
223	  This enables support for 64kB pages, possible on all SH-4
224	  CPUs and later.
225
226endchoice
227
228choice
229	prompt "HugeTLB page size"
230	depends on HUGETLB_PAGE && (CPU_SH4 || CPU_SH5) && MMU
231	default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB
232	default HUGETLB_PAGE_SIZE_64K
233
234config HUGETLB_PAGE_SIZE_64K
235	bool "64kB"
236	depends on !PAGE_SIZE_64KB
237
238config HUGETLB_PAGE_SIZE_256K
239	bool "256kB"
240	depends on X2TLB
241
242config HUGETLB_PAGE_SIZE_1MB
243	bool "1MB"
244
245config HUGETLB_PAGE_SIZE_4MB
246	bool "4MB"
247	depends on X2TLB
248
249config HUGETLB_PAGE_SIZE_64MB
250	bool "64MB"
251	depends on X2TLB
252
253config HUGETLB_PAGE_SIZE_512MB
254	bool "512MB"
255	depends on CPU_SH5
256
257endchoice
258
259source "mm/Kconfig"
260
261endmenu
262
263menu "Cache configuration"
264
265config SH7705_CACHE_32KB
266	bool "Enable 32KB cache size for SH7705"
267	depends on CPU_SUBTYPE_SH7705
268	default y
269
270choice
271	prompt "Cache mode"
272	default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5
273	default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
274
275config CACHE_WRITEBACK
276	bool "Write-back"
277
278config CACHE_WRITETHROUGH
279	bool "Write-through"
280	help
281	  Selecting this option will configure the caches in write-through
282	  mode, as opposed to the default write-back configuration.
283
284	  Since there's sill some aliasing issues on SH-4, this option will
285	  unfortunately still require the majority of flushing functions to
286	  be implemented to deal with aliasing.
287
288	  If unsure, say N.
289
290config CACHE_OFF
291	bool "Off"
292
293endchoice
294
295endmenu
296