xref: /openbmc/linux/arch/sh/mm/Kconfig (revision e7f93a35)
1menu "Processor selection"
2
3#
4# Processor families
5#
6config CPU_SH2
7	bool
8	select SH_WRITETHROUGH
9
10config CPU_SH3
11	bool
12	select CPU_HAS_INTEVT
13	select CPU_HAS_SR_RB
14
15config CPU_SH4
16	bool
17	select CPU_HAS_INTEVT
18	select CPU_HAS_SR_RB
19
20config CPU_SH4A
21	bool
22	select CPU_SH4
23
24config CPU_SUBTYPE_ST40
25	bool
26	select CPU_SH4
27	select CPU_HAS_INTC2_IRQ
28
29#
30# Processor subtypes
31#
32
33comment "SH-2 Processor Support"
34
35config CPU_SUBTYPE_SH7604
36	bool "Support SH7604 processor"
37	select CPU_SH2
38
39comment "SH-3 Processor Support"
40
41config CPU_SUBTYPE_SH7300
42	bool "Support SH7300 processor"
43	select CPU_SH3
44
45config CPU_SUBTYPE_SH7705
46	bool "Support SH7705 processor"
47	select CPU_SH3
48	select CPU_HAS_PINT_IRQ
49
50config CPU_SUBTYPE_SH7707
51	bool "Support SH7707 processor"
52	select CPU_SH3
53	select CPU_HAS_PINT_IRQ
54	help
55	  Select SH7707 if you have a  60 Mhz SH-3 HD6417707 CPU.
56
57config CPU_SUBTYPE_SH7708
58	bool "Support SH7708 processor"
59	select CPU_SH3
60	help
61	  Select SH7708 if you have a  60 Mhz SH-3 HD6417708S or
62	  if you have a 100 Mhz SH-3 HD6417708R CPU.
63
64config CPU_SUBTYPE_SH7709
65	bool "Support SH7709 processor"
66	select CPU_SH3
67	select CPU_HAS_PINT_IRQ
68	help
69	  Select SH7709 if you have a  80 Mhz SH-3 HD6417709 CPU.
70
71comment "SH-4 Processor Support"
72
73config CPU_SUBTYPE_SH7750
74	bool "Support SH7750 processor"
75	select CPU_SH4
76	help
77	  Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
78
79config CPU_SUBTYPE_SH7091
80	bool "Support SH7091 processor"
81	select CPU_SH4
82	select CPU_SUBTYPE_SH7750
83	help
84	  Select SH7091 if you have an SH-4 based Sega device (such as
85	  the Dreamcast, Naomi, and Naomi 2).
86
87config CPU_SUBTYPE_SH7750R
88	bool "Support SH7750R processor"
89	select CPU_SH4
90	select CPU_SUBTYPE_SH7750
91
92config CPU_SUBTYPE_SH7750S
93	bool "Support SH7750S processor"
94	select CPU_SH4
95	select CPU_SUBTYPE_SH7750
96
97config CPU_SUBTYPE_SH7751
98	bool "Support SH7751 processor"
99	select CPU_SH4
100	help
101	  Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
102	  or if you have a HD6417751R CPU.
103
104config CPU_SUBTYPE_SH7751R
105	bool "Support SH7751R processor"
106	select CPU_SH4
107	select CPU_SUBTYPE_SH7751
108
109config CPU_SUBTYPE_SH7760
110	bool "Support SH7760 processor"
111	select CPU_SH4
112	select CPU_HAS_INTC2_IRQ
113
114config CPU_SUBTYPE_SH4_202
115	bool "Support SH4-202 processor"
116	select CPU_SH4
117
118comment "ST40 Processor Support"
119
120config CPU_SUBTYPE_ST40STB1
121	bool "Support ST40STB1/ST40RA processors"
122	select CPU_SUBTYPE_ST40
123	help
124	  Select ST40STB1 if you have a ST40RA CPU.
125	  This was previously called the ST40STB1, hence the option name.
126
127config CPU_SUBTYPE_ST40GX1
128	bool "Support ST40GX1 processor"
129	select CPU_SUBTYPE_ST40
130	help
131	  Select ST40GX1 if you have a ST40GX1 CPU.
132
133comment "SH-4A Processor Support"
134
135config CPU_SUBTYPE_SH73180
136	bool "Support SH73180 processor"
137	select CPU_SH4A
138
139config CPU_SUBTYPE_SH7770
140	bool "Support SH7770 processor"
141	select CPU_SH4A
142
143config CPU_SUBTYPE_SH7780
144	bool "Support SH7780 processor"
145	select CPU_SH4A
146	select CPU_HAS_INTC2_IRQ
147
148endmenu
149
150menu "Memory management options"
151
152config MMU
153        bool "Support for memory management hardware"
154	depends on !CPU_SH2
155	default y
156	help
157	  Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
158	  boot on these systems, this option must not be set.
159
160	  On other systems (such as the SH-3 and 4) where an MMU exists,
161	  turning this off will boot the kernel on these machines with the
162	  MMU implicitly switched off.
163
164config PAGE_OFFSET
165	hex
166	default "0x80000000" if MMU
167	default "0x00000000"
168
169config MEMORY_START
170	hex "Physical memory start address"
171	default "0x08000000"
172	---help---
173	  Computers built with Hitachi SuperH processors always
174	  map the ROM starting at address zero.  But the processor
175	  does not specify the range that RAM takes.
176
177	  The physical memory (RAM) start address will be automatically
178	  set to 08000000. Other platforms, such as the Solution Engine
179	  boards typically map RAM at 0C000000.
180
181	  Tweak this only when porting to a new machine which does not
182	  already have a defconfig. Changing it from the known correct
183	  value on any of the known systems will only lead to disaster.
184
185config MEMORY_SIZE
186	hex "Physical memory size"
187	default "0x00400000"
188	help
189	  This sets the default memory size assumed by your SH kernel. It can
190	  be overridden as normal by the 'mem=' argument on the kernel command
191	  line. If unsure, consult your board specifications or just leave it
192	  as 0x00400000 which was the default value before this became
193	  configurable.
194
195config 32BIT
196	bool "Support 32-bit physical addressing through PMB"
197	depends on CPU_SH4A
198	default y
199	help
200	  If you say Y here, physical addressing will be extended to
201	  32-bits through the SH-4A PMB. If this is not set, legacy
202	  29-bit physical addressing will be used.
203
204choice
205	prompt "HugeTLB page size"
206	depends on HUGETLB_PAGE && CPU_SH4 && MMU
207	default HUGETLB_PAGE_SIZE_64K
208
209config HUGETLB_PAGE_SIZE_64K
210	bool "64K"
211
212config HUGETLB_PAGE_SIZE_1MB
213	bool "1MB"
214
215endchoice
216
217source "mm/Kconfig"
218
219endmenu
220
221menu "Cache configuration"
222
223config SH7705_CACHE_32KB
224	bool "Enable 32KB cache size for SH7705"
225	depends on CPU_SUBTYPE_SH7705
226	default y
227
228config SH_DIRECT_MAPPED
229	bool "Use direct-mapped caching"
230	default n
231	help
232	  Selecting this option will configure the caches to be direct-mapped,
233	  even if the cache supports a 2 or 4-way mode. This is useful primarily
234	  for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
235	  SH4-202, SH4-501, etc.)
236
237	  Turn this option off for platforms that do not have a direct-mapped
238	  cache, and you have no need to run the caches in such a configuration.
239
240config SH_WRITETHROUGH
241	bool "Use write-through caching"
242	default y if CPU_SH2
243	help
244	  Selecting this option will configure the caches in write-through
245	  mode, as opposed to the default write-back configuration.
246
247	  Since there's sill some aliasing issues on SH-4, this option will
248	  unfortunately still require the majority of flushing functions to
249	  be implemented to deal with aliasing.
250
251	  If unsure, say N.
252
253config SH_OCRAM
254	bool "Operand Cache RAM (OCRAM) support"
255	help
256	  Selecting this option will automatically tear down the number of
257	  sets in the dcache by half, which in turn exposes a memory range.
258
259	  The addresses for the OC RAM base will vary according to the
260	  processor version. Consult vendor documentation for specifics.
261
262	  If unsure, say N.
263
264endmenu
265