1# SPDX-License-Identifier: GPL-2.0 2menu "Memory management options" 3 4config MMU 5 bool "Support for memory management hardware" 6 depends on !CPU_SH2 7 default y 8 help 9 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to 10 boot on these systems, this option must not be set. 11 12 On other systems (such as the SH-3 and 4) where an MMU exists, 13 turning this off will boot the kernel on these machines with the 14 MMU implicitly switched off. 15 16config PAGE_OFFSET 17 hex 18 default "0x80000000" if MMU 19 default "0x00000000" 20 21config ARCH_FORCE_MAX_ORDER 22 int "Order of maximal physically contiguous allocations" 23 default "8" if PAGE_SIZE_16KB 24 default "6" if PAGE_SIZE_64KB 25 default "13" if !MMU 26 default "10" 27 help 28 The kernel page allocator limits the size of maximal physically 29 contiguous allocations. The limit is called MAX_ORDER and it 30 defines the maximal power of two of number of pages that can be 31 allocated as a single contiguous block. This option allows 32 overriding the default setting when ability to allocate very 33 large blocks of physically contiguous memory is required. 34 35 The page size is not necessarily 4KB. Keep this in mind when 36 choosing a value for this option. 37 38 Don't change if unsure. 39 40config MEMORY_START 41 hex "Physical memory start address" 42 default "0x08000000" 43 help 44 Computers built with Hitachi SuperH processors always 45 map the ROM starting at address zero. But the processor 46 does not specify the range that RAM takes. 47 48 The physical memory (RAM) start address will be automatically 49 set to 08000000. Other platforms, such as the Solution Engine 50 boards typically map RAM at 0C000000. 51 52 Tweak this only when porting to a new machine which does not 53 already have a defconfig. Changing it from the known correct 54 value on any of the known systems will only lead to disaster. 55 56config MEMORY_SIZE 57 hex "Physical memory size" 58 default "0x04000000" 59 help 60 This sets the default memory size assumed by your SH kernel. It can 61 be overridden as normal by the 'mem=' argument on the kernel command 62 line. If unsure, consult your board specifications or just leave it 63 as 0x04000000 which was the default value before this became 64 configurable. 65 66# Physical addressing modes 67 68config 29BIT 69 def_bool !32BIT 70 select UNCACHED_MAPPING 71 72config 32BIT 73 bool 74 default !MMU 75 76config PMB 77 bool "Support 32-bit physical addressing through PMB" 78 depends on MMU && CPU_SH4A && !CPU_SH4AL_DSP 79 select 32BIT 80 select UNCACHED_MAPPING 81 help 82 If you say Y here, physical addressing will be extended to 83 32-bits through the SH-4A PMB. If this is not set, legacy 84 29-bit physical addressing will be used. 85 86config X2TLB 87 def_bool y 88 depends on (CPU_SHX2 || CPU_SHX3) && MMU 89 90config VSYSCALL 91 bool "Support vsyscall page" 92 depends on MMU && (CPU_SH3 || CPU_SH4) 93 default y 94 help 95 This will enable support for the kernel mapping a vDSO page 96 in process space, and subsequently handing down the entry point 97 to the libc through the ELF auxiliary vector. 98 99 From the kernel side this is used for the signal trampoline. 100 For systems with an MMU that can afford to give up a page, 101 (the default value) say Y. 102 103config NUMA 104 bool "Non-Uniform Memory Access (NUMA) Support" 105 depends on MMU && SYS_SUPPORTS_NUMA 106 select ARCH_WANT_NUMA_VARIABLE_LOCALITY 107 default n 108 help 109 Some SH systems have many various memories scattered around 110 the address space, each with varying latencies. This enables 111 support for these blocks by binding them to nodes and allowing 112 memory policies to be used for prioritizing and controlling 113 allocation behaviour. 114 115config NODES_SHIFT 116 int 117 default "3" if CPU_SUBTYPE_SHX3 118 default "1" 119 depends on NUMA 120 121config ARCH_FLATMEM_ENABLE 122 def_bool y 123 depends on !NUMA 124 125config ARCH_SPARSEMEM_ENABLE 126 def_bool y 127 select SPARSEMEM_STATIC 128 129config ARCH_SPARSEMEM_DEFAULT 130 def_bool y 131 132config ARCH_SELECT_MEMORY_MODEL 133 def_bool y 134 135config ARCH_MEMORY_PROBE 136 def_bool y 137 depends on MEMORY_HOTPLUG 138 139config IOREMAP_FIXED 140 def_bool y 141 depends on X2TLB 142 143config UNCACHED_MAPPING 144 bool 145 146config HAVE_SRAM_POOL 147 bool 148 select GENERIC_ALLOCATOR 149 150choice 151 prompt "Kernel page size" 152 default PAGE_SIZE_4KB 153 154config PAGE_SIZE_4KB 155 bool "4kB" 156 help 157 This is the default page size used by all SuperH CPUs. 158 159config PAGE_SIZE_8KB 160 bool "8kB" 161 depends on !MMU || X2TLB 162 help 163 This enables 8kB pages as supported by SH-X2 and later MMUs. 164 165config PAGE_SIZE_16KB 166 bool "16kB" 167 depends on !MMU 168 help 169 This enables 16kB pages on MMU-less SH systems. 170 171config PAGE_SIZE_64KB 172 bool "64kB" 173 depends on !MMU || CPU_SH4 174 help 175 This enables support for 64kB pages, possible on all SH-4 176 CPUs and later. 177 178endchoice 179 180choice 181 prompt "HugeTLB page size" 182 depends on HUGETLB_PAGE 183 default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB 184 default HUGETLB_PAGE_SIZE_64K 185 186config HUGETLB_PAGE_SIZE_64K 187 bool "64kB" 188 depends on !PAGE_SIZE_64KB 189 190config HUGETLB_PAGE_SIZE_256K 191 bool "256kB" 192 depends on X2TLB 193 194config HUGETLB_PAGE_SIZE_1MB 195 bool "1MB" 196 197config HUGETLB_PAGE_SIZE_4MB 198 bool "4MB" 199 depends on X2TLB 200 201config HUGETLB_PAGE_SIZE_64MB 202 bool "64MB" 203 depends on X2TLB 204 205endchoice 206 207config SCHED_MC 208 bool "Multi-core scheduler support" 209 depends on SMP 210 default y 211 help 212 Multi-core scheduler support improves the CPU scheduler's decision 213 making when dealing with multi-core CPU chips at a cost of slightly 214 increased overhead in some places. If unsure say N here. 215 216endmenu 217 218menu "Cache configuration" 219 220config SH7705_CACHE_32KB 221 bool "Enable 32KB cache size for SH7705" 222 depends on CPU_SUBTYPE_SH7705 223 default y 224 225choice 226 prompt "Cache mode" 227 default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 228 default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A) 229 230config CACHE_WRITEBACK 231 bool "Write-back" 232 233config CACHE_WRITETHROUGH 234 bool "Write-through" 235 help 236 Selecting this option will configure the caches in write-through 237 mode, as opposed to the default write-back configuration. 238 239 Since there's sill some aliasing issues on SH-4, this option will 240 unfortunately still require the majority of flushing functions to 241 be implemented to deal with aliasing. 242 243 If unsure, say N. 244 245config CACHE_OFF 246 bool "Off" 247 248endchoice 249 250endmenu 251