xref: /openbmc/linux/arch/sh/mm/Kconfig (revision b552c7e8)
1menu "Processor selection"
2
3#
4# Processor families
5#
6config CPU_SH2
7	select SH_WRITETHROUGH if !CPU_SH2A
8	bool
9
10config CPU_SH2A
11	bool
12	select CPU_SH2
13
14config CPU_SH3
15	bool
16	select CPU_HAS_INTEVT
17	select CPU_HAS_SR_RB
18
19config CPU_SH4
20	bool
21	select CPU_HAS_INTEVT
22	select CPU_HAS_SR_RB
23
24config CPU_SH4A
25	bool
26	select CPU_SH4
27
28config CPU_SH4AL_DSP
29	bool
30	select CPU_SH4A
31
32config CPU_SUBTYPE_ST40
33	bool
34	select CPU_SH4
35	select CPU_HAS_INTC2_IRQ
36
37#
38# Processor subtypes
39#
40
41comment "SH-2 Processor Support"
42
43config CPU_SUBTYPE_SH7604
44	bool "Support SH7604 processor"
45	select CPU_SH2
46
47config CPU_SUBTYPE_SH7619
48	bool "Support SH7619 processor"
49	select CPU_SH2
50
51comment "SH-2A Processor Support"
52
53config CPU_SUBTYPE_SH7206
54	bool "Support SH7206 processor"
55	select CPU_SH2A
56
57comment "SH-3 Processor Support"
58
59config CPU_SUBTYPE_SH7300
60	bool "Support SH7300 processor"
61	select CPU_SH3
62
63config CPU_SUBTYPE_SH7705
64	bool "Support SH7705 processor"
65	select CPU_SH3
66	select CPU_HAS_PINT_IRQ
67
68config CPU_SUBTYPE_SH7706
69	bool "Support SH7706 processor"
70	select CPU_SH3
71	help
72	  Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
73
74config CPU_SUBTYPE_SH7707
75	bool "Support SH7707 processor"
76	select CPU_SH3
77	select CPU_HAS_PINT_IRQ
78	help
79	  Select SH7707 if you have a  60 Mhz SH-3 HD6417707 CPU.
80
81config CPU_SUBTYPE_SH7708
82	bool "Support SH7708 processor"
83	select CPU_SH3
84	help
85	  Select SH7708 if you have a  60 Mhz SH-3 HD6417708S or
86	  if you have a 100 Mhz SH-3 HD6417708R CPU.
87
88config CPU_SUBTYPE_SH7709
89	bool "Support SH7709 processor"
90	select CPU_SH3
91	select CPU_HAS_PINT_IRQ
92	help
93	  Select SH7709 if you have a  80 Mhz SH-3 HD6417709 CPU.
94
95config CPU_SUBTYPE_SH7710
96	bool "Support SH7710 processor"
97	select CPU_SH3
98	help
99	  Select SH7710 if you have a SH3-DSP SH7710 CPU.
100
101comment "SH-4 Processor Support"
102
103config CPU_SUBTYPE_SH7750
104	bool "Support SH7750 processor"
105	select CPU_SH4
106	help
107	  Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
108
109config CPU_SUBTYPE_SH7091
110	bool "Support SH7091 processor"
111	select CPU_SH4
112	select CPU_SUBTYPE_SH7750
113	help
114	  Select SH7091 if you have an SH-4 based Sega device (such as
115	  the Dreamcast, Naomi, and Naomi 2).
116
117config CPU_SUBTYPE_SH7750R
118	bool "Support SH7750R processor"
119	select CPU_SH4
120	select CPU_SUBTYPE_SH7750
121
122config CPU_SUBTYPE_SH7750S
123	bool "Support SH7750S processor"
124	select CPU_SH4
125	select CPU_SUBTYPE_SH7750
126
127config CPU_SUBTYPE_SH7751
128	bool "Support SH7751 processor"
129	select CPU_SH4
130	help
131	  Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
132	  or if you have a HD6417751R CPU.
133
134config CPU_SUBTYPE_SH7751R
135	bool "Support SH7751R processor"
136	select CPU_SH4
137	select CPU_SUBTYPE_SH7751
138
139config CPU_SUBTYPE_SH7760
140	bool "Support SH7760 processor"
141	select CPU_SH4
142	select CPU_HAS_INTC2_IRQ
143
144config CPU_SUBTYPE_SH4_202
145	bool "Support SH4-202 processor"
146	select CPU_SH4
147
148comment "ST40 Processor Support"
149
150config CPU_SUBTYPE_ST40STB1
151	bool "Support ST40STB1/ST40RA processors"
152	select CPU_SUBTYPE_ST40
153	help
154	  Select ST40STB1 if you have a ST40RA CPU.
155	  This was previously called the ST40STB1, hence the option name.
156
157config CPU_SUBTYPE_ST40GX1
158	bool "Support ST40GX1 processor"
159	select CPU_SUBTYPE_ST40
160	help
161	  Select ST40GX1 if you have a ST40GX1 CPU.
162
163comment "SH-4A Processor Support"
164
165config CPU_SUBTYPE_SH7770
166	bool "Support SH7770 processor"
167	select CPU_SH4A
168
169config CPU_SUBTYPE_SH7780
170	bool "Support SH7780 processor"
171	select CPU_SH4A
172	select CPU_HAS_INTC2_IRQ
173
174config CPU_SUBTYPE_SH7785
175	bool "Support SH7785 processor"
176	select CPU_SH4A
177	select CPU_HAS_INTC2_IRQ
178
179comment "SH4AL-DSP Processor Support"
180
181config CPU_SUBTYPE_SH73180
182	bool "Support SH73180 processor"
183	select CPU_SH4AL_DSP
184
185config CPU_SUBTYPE_SH7343
186	bool "Support SH7343 processor"
187	select CPU_SH4AL_DSP
188
189endmenu
190
191menu "Memory management options"
192
193config MMU
194        bool "Support for memory management hardware"
195	depends on !CPU_SH2
196	default y
197	help
198	  Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
199	  boot on these systems, this option must not be set.
200
201	  On other systems (such as the SH-3 and 4) where an MMU exists,
202	  turning this off will boot the kernel on these machines with the
203	  MMU implicitly switched off.
204
205config PAGE_OFFSET
206	hex
207	default "0x80000000" if MMU
208	default "0x00000000"
209
210config MEMORY_START
211	hex "Physical memory start address"
212	default "0x08000000"
213	---help---
214	  Computers built with Hitachi SuperH processors always
215	  map the ROM starting at address zero.  But the processor
216	  does not specify the range that RAM takes.
217
218	  The physical memory (RAM) start address will be automatically
219	  set to 08000000. Other platforms, such as the Solution Engine
220	  boards typically map RAM at 0C000000.
221
222	  Tweak this only when porting to a new machine which does not
223	  already have a defconfig. Changing it from the known correct
224	  value on any of the known systems will only lead to disaster.
225
226config MEMORY_SIZE
227	hex "Physical memory size"
228	default "0x00400000"
229	help
230	  This sets the default memory size assumed by your SH kernel. It can
231	  be overridden as normal by the 'mem=' argument on the kernel command
232	  line. If unsure, consult your board specifications or just leave it
233	  as 0x00400000 which was the default value before this became
234	  configurable.
235
236config 32BIT
237	bool "Support 32-bit physical addressing through PMB"
238	depends on CPU_SH4A && MMU
239	default y
240	help
241	  If you say Y here, physical addressing will be extended to
242	  32-bits through the SH-4A PMB. If this is not set, legacy
243	  29-bit physical addressing will be used.
244
245config VSYSCALL
246	bool "Support vsyscall page"
247	depends on MMU
248	default y
249	help
250	  This will enable support for the kernel mapping a vDSO page
251	  in process space, and subsequently handing down the entry point
252	  to the libc through the ELF auxiliary vector.
253
254	  From the kernel side this is used for the signal trampoline.
255	  For systems with an MMU that can afford to give up a page,
256	  (the default value) say Y.
257
258choice
259	prompt "HugeTLB page size"
260	depends on HUGETLB_PAGE && CPU_SH4 && MMU
261	default HUGETLB_PAGE_SIZE_64K
262
263config HUGETLB_PAGE_SIZE_64K
264	bool "64K"
265
266config HUGETLB_PAGE_SIZE_1MB
267	bool "1MB"
268
269endchoice
270
271source "mm/Kconfig"
272
273endmenu
274
275menu "Cache configuration"
276
277config SH7705_CACHE_32KB
278	bool "Enable 32KB cache size for SH7705"
279	depends on CPU_SUBTYPE_SH7705
280	default y
281
282config SH_DIRECT_MAPPED
283	bool "Use direct-mapped caching"
284	default n
285	help
286	  Selecting this option will configure the caches to be direct-mapped,
287	  even if the cache supports a 2 or 4-way mode. This is useful primarily
288	  for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
289	  SH4-202, SH4-501, etc.)
290
291	  Turn this option off for platforms that do not have a direct-mapped
292	  cache, and you have no need to run the caches in such a configuration.
293
294config SH_WRITETHROUGH
295	bool "Use write-through caching"
296	help
297	  Selecting this option will configure the caches in write-through
298	  mode, as opposed to the default write-back configuration.
299
300	  Since there's sill some aliasing issues on SH-4, this option will
301	  unfortunately still require the majority of flushing functions to
302	  be implemented to deal with aliasing.
303
304	  If unsure, say N.
305
306config SH_OCRAM
307	bool "Operand Cache RAM (OCRAM) support"
308	help
309	  Selecting this option will automatically tear down the number of
310	  sets in the dcache by half, which in turn exposes a memory range.
311
312	  The addresses for the OC RAM base will vary according to the
313	  processor version. Consult vendor documentation for specifics.
314
315	  If unsure, say N.
316
317endmenu
318