xref: /openbmc/linux/arch/sh/mm/Kconfig (revision b2a37fb2) 
1# SPDX-License-Identifier: GPL-2.0
2menu "Memory management options"
3
4config MMU
5        bool "Support for memory management hardware"
6	depends on !CPU_SH2
7	default y
8	help
9	  Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
10	  boot on these systems, this option must not be set.
11
12	  On other systems (such as the SH-3 and 4) where an MMU exists,
13	  turning this off will boot the kernel on these machines with the
14	  MMU implicitly switched off.
15
16config PAGE_OFFSET
17	hex
18	default "0x80000000" if MMU
19	default "0x00000000"
20
21config ARCH_FORCE_MAX_ORDER
22	int "Order of maximal physically contiguous allocations"
23	range 8 63 if PAGE_SIZE_16KB
24	default "8" if PAGE_SIZE_16KB
25	range 6 63 if PAGE_SIZE_64KB
26	default "6" if PAGE_SIZE_64KB
27	range 10 63
28	default "13" if !MMU
29	default "10"
30	help
31	  The kernel page allocator limits the size of maximal physically
32	  contiguous allocations. The limit is called MAX_ORDER and it
33	  defines the maximal power of two of number of pages that can be
34	  allocated as a single contiguous block. This option allows
35	  overriding the default setting when ability to allocate very
36	  large blocks of physically contiguous memory is required.
37
38	  The page size is not necessarily 4KB. Keep this in mind when
39	  choosing a value for this option.
40
41	  Don't change if unsure.
42
43config MEMORY_START
44	hex "Physical memory start address"
45	default "0x08000000"
46	help
47	  Computers built with Hitachi SuperH processors always
48	  map the ROM starting at address zero.  But the processor
49	  does not specify the range that RAM takes.
50
51	  The physical memory (RAM) start address will be automatically
52	  set to 08000000. Other platforms, such as the Solution Engine
53	  boards typically map RAM at 0C000000.
54
55	  Tweak this only when porting to a new machine which does not
56	  already have a defconfig. Changing it from the known correct
57	  value on any of the known systems will only lead to disaster.
58
59config MEMORY_SIZE
60	hex "Physical memory size"
61	default "0x04000000"
62	help
63	  This sets the default memory size assumed by your SH kernel. It can
64	  be overridden as normal by the 'mem=' argument on the kernel command
65	  line. If unsure, consult your board specifications or just leave it
66	  as 0x04000000 which was the default value before this became
67	  configurable.
68
69# Physical addressing modes
70
71config 29BIT
72	def_bool !32BIT
73	select UNCACHED_MAPPING
74
75config 32BIT
76	bool
77	default !MMU
78
79config PMB
80	bool "Support 32-bit physical addressing through PMB"
81	depends on MMU && CPU_SH4A && !CPU_SH4AL_DSP
82	select 32BIT
83	select UNCACHED_MAPPING
84	help
85	  If you say Y here, physical addressing will be extended to
86	  32-bits through the SH-4A PMB. If this is not set, legacy
87	  29-bit physical addressing will be used.
88
89config X2TLB
90	def_bool y
91	depends on (CPU_SHX2 || CPU_SHX3) && MMU
92
93config VSYSCALL
94	bool "Support vsyscall page"
95	depends on MMU && (CPU_SH3 || CPU_SH4)
96	default y
97	help
98	  This will enable support for the kernel mapping a vDSO page
99	  in process space, and subsequently handing down the entry point
100	  to the libc through the ELF auxiliary vector.
101
102	  From the kernel side this is used for the signal trampoline.
103	  For systems with an MMU that can afford to give up a page,
104	  (the default value) say Y.
105
106config NUMA
107	bool "Non-Uniform Memory Access (NUMA) Support"
108	depends on MMU && SYS_SUPPORTS_NUMA
109	select ARCH_WANT_NUMA_VARIABLE_LOCALITY
110	default n
111	help
112	  Some SH systems have many various memories scattered around
113	  the address space, each with varying latencies. This enables
114	  support for these blocks by binding them to nodes and allowing
115	  memory policies to be used for prioritizing and controlling
116	  allocation behaviour.
117
118config NODES_SHIFT
119	int
120	default "3" if CPU_SUBTYPE_SHX3
121	default "1"
122	depends on NUMA
123
124config ARCH_FLATMEM_ENABLE
125	def_bool y
126	depends on !NUMA
127
128config ARCH_SPARSEMEM_ENABLE
129	def_bool y
130	select SPARSEMEM_STATIC
131
132config ARCH_SPARSEMEM_DEFAULT
133	def_bool y
134
135config ARCH_SELECT_MEMORY_MODEL
136	def_bool y
137
138config ARCH_MEMORY_PROBE
139	def_bool y
140	depends on MEMORY_HOTPLUG
141
142config IOREMAP_FIXED
143       def_bool y
144       depends on X2TLB
145
146config UNCACHED_MAPPING
147	bool
148
149config HAVE_SRAM_POOL
150	bool
151	select GENERIC_ALLOCATOR
152
153choice
154	prompt "Kernel page size"
155	default PAGE_SIZE_4KB
156
157config PAGE_SIZE_4KB
158	bool "4kB"
159	help
160	  This is the default page size used by all SuperH CPUs.
161
162config PAGE_SIZE_8KB
163	bool "8kB"
164	depends on !MMU || X2TLB
165	help
166	  This enables 8kB pages as supported by SH-X2 and later MMUs.
167
168config PAGE_SIZE_16KB
169	bool "16kB"
170	depends on !MMU
171	help
172	  This enables 16kB pages on MMU-less SH systems.
173
174config PAGE_SIZE_64KB
175	bool "64kB"
176	depends on !MMU || CPU_SH4
177	help
178	  This enables support for 64kB pages, possible on all SH-4
179	  CPUs and later.
180
181endchoice
182
183choice
184	prompt "HugeTLB page size"
185	depends on HUGETLB_PAGE
186	default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB
187	default HUGETLB_PAGE_SIZE_64K
188
189config HUGETLB_PAGE_SIZE_64K
190	bool "64kB"
191	depends on !PAGE_SIZE_64KB
192
193config HUGETLB_PAGE_SIZE_256K
194	bool "256kB"
195	depends on X2TLB
196
197config HUGETLB_PAGE_SIZE_1MB
198	bool "1MB"
199
200config HUGETLB_PAGE_SIZE_4MB
201	bool "4MB"
202	depends on X2TLB
203
204config HUGETLB_PAGE_SIZE_64MB
205	bool "64MB"
206	depends on X2TLB
207
208endchoice
209
210config SCHED_MC
211	bool "Multi-core scheduler support"
212	depends on SMP
213	default y
214	help
215	  Multi-core scheduler support improves the CPU scheduler's decision
216	  making when dealing with multi-core CPU chips at a cost of slightly
217	  increased overhead in some places. If unsure say N here.
218
219endmenu
220
221menu "Cache configuration"
222
223config SH7705_CACHE_32KB
224	bool "Enable 32KB cache size for SH7705"
225	depends on CPU_SUBTYPE_SH7705
226	default y
227
228choice
229	prompt "Cache mode"
230	default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4
231	default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
232
233config CACHE_WRITEBACK
234	bool "Write-back"
235
236config CACHE_WRITETHROUGH
237	bool "Write-through"
238	help
239	  Selecting this option will configure the caches in write-through
240	  mode, as opposed to the default write-back configuration.
241
242	  Since there's sill some aliasing issues on SH-4, this option will
243	  unfortunately still require the majority of flushing functions to
244	  be implemented to deal with aliasing.
245
246	  If unsure, say N.
247
248config CACHE_OFF
249	bool "Off"
250
251endchoice
252
253endmenu
254