1menu "Memory management options" 2 3config QUICKLIST 4 def_bool y 5 6config MMU 7 bool "Support for memory management hardware" 8 depends on !CPU_SH2 9 default y 10 help 11 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to 12 boot on these systems, this option must not be set. 13 14 On other systems (such as the SH-3 and 4) where an MMU exists, 15 turning this off will boot the kernel on these machines with the 16 MMU implicitly switched off. 17 18config PAGE_OFFSET 19 hex 20 default "0x80000000" if MMU && SUPERH32 21 default "0x20000000" if MMU && SUPERH64 22 default "0x00000000" 23 24config FORCE_MAX_ZONEORDER 25 int "Maximum zone order" 26 range 9 64 if PAGE_SIZE_16KB 27 default "9" if PAGE_SIZE_16KB 28 range 7 64 if PAGE_SIZE_64KB 29 default "7" if PAGE_SIZE_64KB 30 range 11 64 31 default "14" if !MMU 32 default "11" 33 help 34 The kernel memory allocator divides physically contiguous memory 35 blocks into "zones", where each zone is a power of two number of 36 pages. This option selects the largest power of two that the kernel 37 keeps in the memory allocator. If you need to allocate very large 38 blocks of physically contiguous memory, then you may need to 39 increase this value. 40 41 This config option is actually maximum order plus one. For example, 42 a value of 11 means that the largest free memory block is 2^10 pages. 43 44 The page size is not necessarily 4KB. Keep this in mind when 45 choosing a value for this option. 46 47config MEMORY_START 48 hex "Physical memory start address" 49 default "0x08000000" 50 ---help--- 51 Computers built with Hitachi SuperH processors always 52 map the ROM starting at address zero. But the processor 53 does not specify the range that RAM takes. 54 55 The physical memory (RAM) start address will be automatically 56 set to 08000000. Other platforms, such as the Solution Engine 57 boards typically map RAM at 0C000000. 58 59 Tweak this only when porting to a new machine which does not 60 already have a defconfig. Changing it from the known correct 61 value on any of the known systems will only lead to disaster. 62 63config MEMORY_SIZE 64 hex "Physical memory size" 65 default "0x04000000" 66 help 67 This sets the default memory size assumed by your SH kernel. It can 68 be overridden as normal by the 'mem=' argument on the kernel command 69 line. If unsure, consult your board specifications or just leave it 70 as 0x04000000 which was the default value before this became 71 configurable. 72 73# Physical addressing modes 74 75config 29BIT 76 def_bool !32BIT 77 depends on SUPERH32 78 select UNCACHED_MAPPING 79 80config 32BIT 81 bool 82 default y if CPU_SH5 83 84config PMB 85 bool "Support 32-bit physical addressing through PMB" 86 depends on MMU && EXPERIMENTAL && CPU_SH4A && !CPU_SH4AL_DSP 87 select 32BIT 88 select UNCACHED_MAPPING 89 help 90 If you say Y here, physical addressing will be extended to 91 32-bits through the SH-4A PMB. If this is not set, legacy 92 29-bit physical addressing will be used. 93 94config PMB_LEGACY 95 bool "Support legacy boot mappings for PMB" 96 depends on PMB 97 select 32BIT 98 help 99 If this option is enabled, fixed PMB mappings are inherited 100 from the boot loader, and the kernel does not attempt dynamic 101 management. This is the closest to legacy 29-bit physical mode, 102 and allows systems to support up to 512MiB of system memory. 103 104config X2TLB 105 def_bool y 106 depends on (CPU_SHX2 || CPU_SHX3) && MMU 107 108config VSYSCALL 109 bool "Support vsyscall page" 110 depends on MMU && (CPU_SH3 || CPU_SH4) 111 default y 112 help 113 This will enable support for the kernel mapping a vDSO page 114 in process space, and subsequently handing down the entry point 115 to the libc through the ELF auxiliary vector. 116 117 From the kernel side this is used for the signal trampoline. 118 For systems with an MMU that can afford to give up a page, 119 (the default value) say Y. 120 121config NUMA 122 bool "Non Uniform Memory Access (NUMA) Support" 123 depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL 124 default n 125 help 126 Some SH systems have many various memories scattered around 127 the address space, each with varying latencies. This enables 128 support for these blocks by binding them to nodes and allowing 129 memory policies to be used for prioritizing and controlling 130 allocation behaviour. 131 132config NODES_SHIFT 133 int 134 default "3" if CPU_SUBTYPE_SHX3 135 default "1" 136 depends on NEED_MULTIPLE_NODES 137 138config ARCH_FLATMEM_ENABLE 139 def_bool y 140 depends on !NUMA 141 142config ARCH_SPARSEMEM_ENABLE 143 def_bool y 144 select SPARSEMEM_STATIC 145 146config ARCH_SPARSEMEM_DEFAULT 147 def_bool y 148 149config MAX_ACTIVE_REGIONS 150 int 151 default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM) 152 default "2" if SPARSEMEM && (CPU_SUBTYPE_SH7722 || \ 153 CPU_SUBTYPE_SH7785) 154 default "1" 155 156config ARCH_POPULATES_NODE_MAP 157 def_bool y 158 159config ARCH_SELECT_MEMORY_MODEL 160 def_bool y 161 162config ARCH_ENABLE_MEMORY_HOTPLUG 163 def_bool y 164 depends on SPARSEMEM && MMU 165 166config ARCH_ENABLE_MEMORY_HOTREMOVE 167 def_bool y 168 depends on SPARSEMEM && MMU 169 170config ARCH_MEMORY_PROBE 171 def_bool y 172 depends on MEMORY_HOTPLUG 173 174config IOREMAP_FIXED 175 def_bool y 176 depends on X2TLB || SUPERH64 177 178config UNCACHED_MAPPING 179 bool 180 181choice 182 prompt "Kernel page size" 183 default PAGE_SIZE_4KB 184 185config PAGE_SIZE_4KB 186 bool "4kB" 187 help 188 This is the default page size used by all SuperH CPUs. 189 190config PAGE_SIZE_8KB 191 bool "8kB" 192 depends on !MMU || X2TLB 193 help 194 This enables 8kB pages as supported by SH-X2 and later MMUs. 195 196config PAGE_SIZE_16KB 197 bool "16kB" 198 depends on !MMU 199 help 200 This enables 16kB pages on MMU-less SH systems. 201 202config PAGE_SIZE_64KB 203 bool "64kB" 204 depends on !MMU || CPU_SH4 || CPU_SH5 205 help 206 This enables support for 64kB pages, possible on all SH-4 207 CPUs and later. 208 209endchoice 210 211choice 212 prompt "HugeTLB page size" 213 depends on HUGETLB_PAGE 214 default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB 215 default HUGETLB_PAGE_SIZE_64K 216 217config HUGETLB_PAGE_SIZE_64K 218 bool "64kB" 219 depends on !PAGE_SIZE_64KB 220 221config HUGETLB_PAGE_SIZE_256K 222 bool "256kB" 223 depends on X2TLB 224 225config HUGETLB_PAGE_SIZE_1MB 226 bool "1MB" 227 228config HUGETLB_PAGE_SIZE_4MB 229 bool "4MB" 230 depends on X2TLB 231 232config HUGETLB_PAGE_SIZE_64MB 233 bool "64MB" 234 depends on X2TLB 235 236config HUGETLB_PAGE_SIZE_512MB 237 bool "512MB" 238 depends on CPU_SH5 239 240endchoice 241 242source "mm/Kconfig" 243 244config SCHED_MC 245 bool "Multi-core scheduler support" 246 depends on SMP 247 default y 248 help 249 Multi-core scheduler support improves the CPU scheduler's decision 250 making when dealing with multi-core CPU chips at a cost of slightly 251 increased overhead in some places. If unsure say N here. 252 253endmenu 254 255menu "Cache configuration" 256 257config SH7705_CACHE_32KB 258 bool "Enable 32KB cache size for SH7705" 259 depends on CPU_SUBTYPE_SH7705 260 default y 261 262choice 263 prompt "Cache mode" 264 default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5 265 default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A) 266 267config CACHE_WRITEBACK 268 bool "Write-back" 269 270config CACHE_WRITETHROUGH 271 bool "Write-through" 272 help 273 Selecting this option will configure the caches in write-through 274 mode, as opposed to the default write-back configuration. 275 276 Since there's sill some aliasing issues on SH-4, this option will 277 unfortunately still require the majority of flushing functions to 278 be implemented to deal with aliasing. 279 280 If unsure, say N. 281 282config CACHE_OFF 283 bool "Off" 284 285endchoice 286 287endmenu 288