xref: /openbmc/linux/arch/sh/mm/Kconfig (revision b04b4f78) 
1menu "Memory management options"
2
3config QUICKLIST
4	def_bool y
5
6config MMU
7        bool "Support for memory management hardware"
8	depends on !CPU_SH2
9	default y
10	help
11	  Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
12	  boot on these systems, this option must not be set.
13
14	  On other systems (such as the SH-3 and 4) where an MMU exists,
15	  turning this off will boot the kernel on these machines with the
16	  MMU implicitly switched off.
17
18config PAGE_OFFSET
19	hex
20	default "0x80000000" if MMU && SUPERH32
21	default "0x20000000" if MMU && SUPERH64
22	default "0x00000000"
23
24config MEMORY_START
25	hex "Physical memory start address"
26	default "0x08000000"
27	---help---
28	  Computers built with Hitachi SuperH processors always
29	  map the ROM starting at address zero.  But the processor
30	  does not specify the range that RAM takes.
31
32	  The physical memory (RAM) start address will be automatically
33	  set to 08000000. Other platforms, such as the Solution Engine
34	  boards typically map RAM at 0C000000.
35
36	  Tweak this only when porting to a new machine which does not
37	  already have a defconfig. Changing it from the known correct
38	  value on any of the known systems will only lead to disaster.
39
40config MEMORY_SIZE
41	hex "Physical memory size"
42	default "0x04000000"
43	help
44	  This sets the default memory size assumed by your SH kernel. It can
45	  be overridden as normal by the 'mem=' argument on the kernel command
46	  line. If unsure, consult your board specifications or just leave it
47	  as 0x04000000 which was the default value before this became
48	  configurable.
49
50# Physical addressing modes
51
52config 29BIT
53	def_bool !32BIT
54	depends on SUPERH32
55
56config 32BIT
57	bool
58	default y if CPU_SH5
59
60config PMB_ENABLE
61	bool "Support 32-bit physical addressing through PMB"
62	depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
63	select 32BIT
64	default y
65	help
66	  If you say Y here, physical addressing will be extended to
67	  32-bits through the SH-4A PMB. If this is not set, legacy
68	  29-bit physical addressing will be used.
69
70choice
71	prompt "PMB handling type"
72	depends on PMB_ENABLE
73	default PMB_FIXED
74
75config PMB
76	bool "PMB"
77	depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
78	select 32BIT
79	help
80	  If you say Y here, physical addressing will be extended to
81	  32-bits through the SH-4A PMB. If this is not set, legacy
82	  29-bit physical addressing will be used.
83
84config PMB_FIXED
85	bool "fixed PMB"
86	depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || \
87					   CPU_SUBTYPE_SH7785)
88	select 32BIT
89	help
90	  If this option is enabled, fixed PMB mappings are inherited
91	  from the boot loader, and the kernel does not attempt dynamic
92	  management. This is the closest to legacy 29-bit physical mode,
93	  and allows systems to support up to 512MiB of system memory.
94
95endchoice
96
97config X2TLB
98	bool "Enable extended TLB mode"
99	depends on (CPU_SHX2 || CPU_SHX3) && MMU && EXPERIMENTAL
100	help
101	  Selecting this option will enable the extended mode of the SH-X2
102	  TLB. For legacy SH-X behaviour and interoperability, say N. For
103	  all of the fun new features and a willingless to submit bug reports,
104	  say Y.
105
106config VSYSCALL
107	bool "Support vsyscall page"
108	depends on MMU && (CPU_SH3 || CPU_SH4)
109	default y
110	help
111	  This will enable support for the kernel mapping a vDSO page
112	  in process space, and subsequently handing down the entry point
113	  to the libc through the ELF auxiliary vector.
114
115	  From the kernel side this is used for the signal trampoline.
116	  For systems with an MMU that can afford to give up a page,
117	  (the default value) say Y.
118
119config NUMA
120	bool "Non Uniform Memory Access (NUMA) Support"
121	depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
122	default n
123	help
124	  Some SH systems have many various memories scattered around
125	  the address space, each with varying latencies. This enables
126	  support for these blocks by binding them to nodes and allowing
127	  memory policies to be used for prioritizing and controlling
128	  allocation behaviour.
129
130config NODES_SHIFT
131	int
132	default "3" if CPU_SUBTYPE_SHX3
133	default "1"
134	depends on NEED_MULTIPLE_NODES
135
136config ARCH_FLATMEM_ENABLE
137	def_bool y
138	depends on !NUMA
139
140config ARCH_SPARSEMEM_ENABLE
141	def_bool y
142	select SPARSEMEM_STATIC
143
144config ARCH_SPARSEMEM_DEFAULT
145	def_bool y
146
147config MAX_ACTIVE_REGIONS
148	int
149	default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM)
150	default "2" if SPARSEMEM && (CPU_SUBTYPE_SH7722 || \
151		       CPU_SUBTYPE_SH7785)
152	default "1"
153
154config ARCH_POPULATES_NODE_MAP
155	def_bool y
156
157config ARCH_SELECT_MEMORY_MODEL
158	def_bool y
159
160config ARCH_ENABLE_MEMORY_HOTPLUG
161	def_bool y
162	depends on SPARSEMEM && MMU
163
164config ARCH_ENABLE_MEMORY_HOTREMOVE
165	def_bool y
166	depends on SPARSEMEM && MMU
167
168config ARCH_MEMORY_PROBE
169	def_bool y
170	depends on MEMORY_HOTPLUG
171
172choice
173	prompt "Kernel page size"
174	default PAGE_SIZE_8KB if X2TLB
175	default PAGE_SIZE_4KB
176
177config PAGE_SIZE_4KB
178	bool "4kB"
179	depends on !MMU || !X2TLB
180	help
181	  This is the default page size used by all SuperH CPUs.
182
183config PAGE_SIZE_8KB
184	bool "8kB"
185	depends on !MMU || X2TLB
186	help
187	  This enables 8kB pages as supported by SH-X2 and later MMUs.
188
189config PAGE_SIZE_16KB
190	bool "16kB"
191	depends on !MMU
192	help
193	  This enables 16kB pages on MMU-less SH systems.
194
195config PAGE_SIZE_64KB
196	bool "64kB"
197	depends on !MMU || CPU_SH4 || CPU_SH5
198	help
199	  This enables support for 64kB pages, possible on all SH-4
200	  CPUs and later.
201
202endchoice
203
204config ENTRY_OFFSET
205	hex
206	default "0x00001000" if PAGE_SIZE_4KB
207	default "0x00002000" if PAGE_SIZE_8KB
208	default "0x00004000" if PAGE_SIZE_16KB
209	default "0x00010000" if PAGE_SIZE_64KB
210	default "0x00000000"
211
212choice
213	prompt "HugeTLB page size"
214	depends on HUGETLB_PAGE && (CPU_SH4 || CPU_SH5) && MMU
215	default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB
216	default HUGETLB_PAGE_SIZE_64K
217
218config HUGETLB_PAGE_SIZE_64K
219	bool "64kB"
220	depends on !PAGE_SIZE_64KB
221
222config HUGETLB_PAGE_SIZE_256K
223	bool "256kB"
224	depends on X2TLB
225
226config HUGETLB_PAGE_SIZE_1MB
227	bool "1MB"
228
229config HUGETLB_PAGE_SIZE_4MB
230	bool "4MB"
231	depends on X2TLB
232
233config HUGETLB_PAGE_SIZE_64MB
234	bool "64MB"
235	depends on X2TLB
236
237config HUGETLB_PAGE_SIZE_512MB
238	bool "512MB"
239	depends on CPU_SH5
240
241endchoice
242
243source "mm/Kconfig"
244
245endmenu
246
247menu "Cache configuration"
248
249config SH7705_CACHE_32KB
250	bool "Enable 32KB cache size for SH7705"
251	depends on CPU_SUBTYPE_SH7705
252	default y
253
254choice
255	prompt "Cache mode"
256	default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5
257	default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
258
259config CACHE_WRITEBACK
260	bool "Write-back"
261
262config CACHE_WRITETHROUGH
263	bool "Write-through"
264	help
265	  Selecting this option will configure the caches in write-through
266	  mode, as opposed to the default write-back configuration.
267
268	  Since there's sill some aliasing issues on SH-4, this option will
269	  unfortunately still require the majority of flushing functions to
270	  be implemented to deal with aliasing.
271
272	  If unsure, say N.
273
274config CACHE_OFF
275	bool "Off"
276
277endchoice
278
279endmenu
280