xref: /openbmc/linux/arch/sh/mm/Kconfig (revision a0ab3668) 
1menu "Memory management options"
2
3config QUICKLIST
4	def_bool y
5
6config MMU
7        bool "Support for memory management hardware"
8	depends on !CPU_SH2
9	default y
10	help
11	  Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
12	  boot on these systems, this option must not be set.
13
14	  On other systems (such as the SH-3 and 4) where an MMU exists,
15	  turning this off will boot the kernel on these machines with the
16	  MMU implicitly switched off.
17
18config PAGE_OFFSET
19	hex
20	default "0x80000000" if MMU && SUPERH32
21	default "0x20000000" if MMU && SUPERH64
22	default "0x00000000"
23
24config FORCE_MAX_ZONEORDER
25	int "Maximum zone order"
26	range 9 64 if PAGE_SIZE_16KB
27	default "9" if PAGE_SIZE_16KB
28	range 7 64 if PAGE_SIZE_64KB
29	default "7" if PAGE_SIZE_64KB
30	range 11 64
31	default "14" if !MMU
32	default "11"
33	help
34	  The kernel memory allocator divides physically contiguous memory
35	  blocks into "zones", where each zone is a power of two number of
36	  pages.  This option selects the largest power of two that the kernel
37	  keeps in the memory allocator.  If you need to allocate very large
38	  blocks of physically contiguous memory, then you may need to
39	  increase this value.
40
41	  This config option is actually maximum order plus one. For example,
42	  a value of 11 means that the largest free memory block is 2^10 pages.
43
44	  The page size is not necessarily 4KB. Keep this in mind when
45	  choosing a value for this option.
46
47config MEMORY_START
48	hex "Physical memory start address"
49	default "0x08000000"
50	---help---
51	  Computers built with Hitachi SuperH processors always
52	  map the ROM starting at address zero.  But the processor
53	  does not specify the range that RAM takes.
54
55	  The physical memory (RAM) start address will be automatically
56	  set to 08000000. Other platforms, such as the Solution Engine
57	  boards typically map RAM at 0C000000.
58
59	  Tweak this only when porting to a new machine which does not
60	  already have a defconfig. Changing it from the known correct
61	  value on any of the known systems will only lead to disaster.
62
63config MEMORY_SIZE
64	hex "Physical memory size"
65	default "0x04000000"
66	help
67	  This sets the default memory size assumed by your SH kernel. It can
68	  be overridden as normal by the 'mem=' argument on the kernel command
69	  line. If unsure, consult your board specifications or just leave it
70	  as 0x04000000 which was the default value before this became
71	  configurable.
72
73# Physical addressing modes
74
75config 29BIT
76	def_bool !32BIT
77	depends on SUPERH32
78
79config 32BIT
80	bool
81	default y if CPU_SH5
82
83config PMB
84	bool "Support 32-bit physical addressing through PMB"
85	depends on MMU && EXPERIMENTAL && CPU_SH4A && !CPU_SH4AL_DSP
86	select 32BIT
87	help
88	  If you say Y here, physical addressing will be extended to
89	  32-bits through the SH-4A PMB. If this is not set, legacy
90	  29-bit physical addressing will be used.
91
92config PMB_LEGACY
93	bool "Support legacy boot mappings for PMB"
94	depends on PMB
95	select 32BIT
96	help
97	  If this option is enabled, fixed PMB mappings are inherited
98	  from the boot loader, and the kernel does not attempt dynamic
99	  management. This is the closest to legacy 29-bit physical mode,
100	  and allows systems to support up to 512MiB of system memory.
101
102config X2TLB
103	bool "Enable extended TLB mode"
104	depends on (CPU_SHX2 || CPU_SHX3) && MMU && EXPERIMENTAL
105	help
106	  Selecting this option will enable the extended mode of the SH-X2
107	  TLB. For legacy SH-X behaviour and interoperability, say N. For
108	  all of the fun new features and a willingless to submit bug reports,
109	  say Y.
110
111config VSYSCALL
112	bool "Support vsyscall page"
113	depends on MMU && (CPU_SH3 || CPU_SH4)
114	default y
115	help
116	  This will enable support for the kernel mapping a vDSO page
117	  in process space, and subsequently handing down the entry point
118	  to the libc through the ELF auxiliary vector.
119
120	  From the kernel side this is used for the signal trampoline.
121	  For systems with an MMU that can afford to give up a page,
122	  (the default value) say Y.
123
124config NUMA
125	bool "Non Uniform Memory Access (NUMA) Support"
126	depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
127	default n
128	help
129	  Some SH systems have many various memories scattered around
130	  the address space, each with varying latencies. This enables
131	  support for these blocks by binding them to nodes and allowing
132	  memory policies to be used for prioritizing and controlling
133	  allocation behaviour.
134
135config NODES_SHIFT
136	int
137	default "3" if CPU_SUBTYPE_SHX3
138	default "1"
139	depends on NEED_MULTIPLE_NODES
140
141config ARCH_FLATMEM_ENABLE
142	def_bool y
143	depends on !NUMA
144
145config ARCH_SPARSEMEM_ENABLE
146	def_bool y
147	select SPARSEMEM_STATIC
148
149config ARCH_SPARSEMEM_DEFAULT
150	def_bool y
151
152config MAX_ACTIVE_REGIONS
153	int
154	default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM)
155	default "2" if SPARSEMEM && (CPU_SUBTYPE_SH7722 || \
156		       CPU_SUBTYPE_SH7785)
157	default "1"
158
159config ARCH_POPULATES_NODE_MAP
160	def_bool y
161
162config ARCH_SELECT_MEMORY_MODEL
163	def_bool y
164
165config ARCH_ENABLE_MEMORY_HOTPLUG
166	def_bool y
167	depends on SPARSEMEM && MMU
168
169config ARCH_ENABLE_MEMORY_HOTREMOVE
170	def_bool y
171	depends on SPARSEMEM && MMU
172
173config ARCH_MEMORY_PROBE
174	def_bool y
175	depends on MEMORY_HOTPLUG
176
177choice
178	prompt "Page table layout"
179	default PGTABLE_LEVELS_3 if X2TLB
180	default PGTABLE_LEVELS_2
181
182config PGTABLE_LEVELS_2
183       bool "2 Levels"
184       help
185         This is the default page table layout for all SuperH CPUs.
186
187config PGTABLE_LEVELS_3
188       bool "3 Levels"
189       depends on X2TLB
190       help
191         This enables a 3 level page table structure.
192
193endchoice
194
195choice
196	prompt "Kernel page size"
197	default PAGE_SIZE_8KB if X2TLB
198	default PAGE_SIZE_4KB
199
200config PAGE_SIZE_4KB
201	bool "4kB"
202	depends on !MMU || !X2TLB || PGTABLE_LEVELS_3
203	help
204	  This is the default page size used by all SuperH CPUs.
205
206config PAGE_SIZE_8KB
207	bool "8kB"
208	depends on !MMU || X2TLB
209	help
210	  This enables 8kB pages as supported by SH-X2 and later MMUs.
211
212config PAGE_SIZE_16KB
213	bool "16kB"
214	depends on !MMU
215	help
216	  This enables 16kB pages on MMU-less SH systems.
217
218config PAGE_SIZE_64KB
219	bool "64kB"
220	depends on !MMU || CPU_SH4 || CPU_SH5
221	help
222	  This enables support for 64kB pages, possible on all SH-4
223	  CPUs and later.
224
225endchoice
226
227choice
228	prompt "HugeTLB page size"
229	depends on HUGETLB_PAGE
230	default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB
231	default HUGETLB_PAGE_SIZE_64K
232
233config HUGETLB_PAGE_SIZE_64K
234	bool "64kB"
235	depends on !PAGE_SIZE_64KB
236
237config HUGETLB_PAGE_SIZE_256K
238	bool "256kB"
239	depends on X2TLB
240
241config HUGETLB_PAGE_SIZE_1MB
242	bool "1MB"
243
244config HUGETLB_PAGE_SIZE_4MB
245	bool "4MB"
246	depends on X2TLB
247
248config HUGETLB_PAGE_SIZE_64MB
249	bool "64MB"
250	depends on X2TLB
251
252config HUGETLB_PAGE_SIZE_512MB
253	bool "512MB"
254	depends on CPU_SH5
255
256endchoice
257
258source "mm/Kconfig"
259
260config SCHED_MC
261	bool "Multi-core scheduler support"
262	depends on SMP
263	default y
264	help
265	  Multi-core scheduler support improves the CPU scheduler's decision
266	  making when dealing with multi-core CPU chips at a cost of slightly
267	  increased overhead in some places. If unsure say N here.
268
269endmenu
270
271menu "Cache configuration"
272
273config SH7705_CACHE_32KB
274	bool "Enable 32KB cache size for SH7705"
275	depends on CPU_SUBTYPE_SH7705
276	default y
277
278choice
279	prompt "Cache mode"
280	default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5
281	default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
282
283config CACHE_WRITEBACK
284	bool "Write-back"
285
286config CACHE_WRITETHROUGH
287	bool "Write-through"
288	help
289	  Selecting this option will configure the caches in write-through
290	  mode, as opposed to the default write-back configuration.
291
292	  Since there's sill some aliasing issues on SH-4, this option will
293	  unfortunately still require the majority of flushing functions to
294	  be implemented to deal with aliasing.
295
296	  If unsure, say N.
297
298config CACHE_OFF
299	bool "Off"
300
301endchoice
302
303endmenu
304