xref: /openbmc/linux/arch/sh/mm/Kconfig (revision 9d56dd3b) 
1menu "Memory management options"
2
3config QUICKLIST
4	def_bool y
5
6config MMU
7        bool "Support for memory management hardware"
8	depends on !CPU_SH2
9	default y
10	help
11	  Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
12	  boot on these systems, this option must not be set.
13
14	  On other systems (such as the SH-3 and 4) where an MMU exists,
15	  turning this off will boot the kernel on these machines with the
16	  MMU implicitly switched off.
17
18config PAGE_OFFSET
19	hex
20	default "0x80000000" if MMU && SUPERH32
21	default "0x20000000" if MMU && SUPERH64
22	default "0x00000000"
23
24config FORCE_MAX_ZONEORDER
25	int "Maximum zone order"
26	range 9 64 if PAGE_SIZE_16KB
27	default "9" if PAGE_SIZE_16KB
28	range 7 64 if PAGE_SIZE_64KB
29	default "7" if PAGE_SIZE_64KB
30	range 11 64
31	default "14" if !MMU
32	default "11"
33	help
34	  The kernel memory allocator divides physically contiguous memory
35	  blocks into "zones", where each zone is a power of two number of
36	  pages.  This option selects the largest power of two that the kernel
37	  keeps in the memory allocator.  If you need to allocate very large
38	  blocks of physically contiguous memory, then you may need to
39	  increase this value.
40
41	  This config option is actually maximum order plus one. For example,
42	  a value of 11 means that the largest free memory block is 2^10 pages.
43
44	  The page size is not necessarily 4KB. Keep this in mind when
45	  choosing a value for this option.
46
47config MEMORY_START
48	hex "Physical memory start address"
49	default "0x08000000"
50	---help---
51	  Computers built with Hitachi SuperH processors always
52	  map the ROM starting at address zero.  But the processor
53	  does not specify the range that RAM takes.
54
55	  The physical memory (RAM) start address will be automatically
56	  set to 08000000. Other platforms, such as the Solution Engine
57	  boards typically map RAM at 0C000000.
58
59	  Tweak this only when porting to a new machine which does not
60	  already have a defconfig. Changing it from the known correct
61	  value on any of the known systems will only lead to disaster.
62
63config MEMORY_SIZE
64	hex "Physical memory size"
65	default "0x04000000"
66	help
67	  This sets the default memory size assumed by your SH kernel. It can
68	  be overridden as normal by the 'mem=' argument on the kernel command
69	  line. If unsure, consult your board specifications or just leave it
70	  as 0x04000000 which was the default value before this became
71	  configurable.
72
73# Physical addressing modes
74
75config 29BIT
76	def_bool !32BIT
77	depends on SUPERH32
78
79config 32BIT
80	bool
81	default y if CPU_SH5
82
83config PMB
84	bool "Support 32-bit physical addressing through PMB"
85	depends on MMU && EXPERIMENTAL && CPU_SH4A && !CPU_SH4AL_DSP
86	select 32BIT
87	help
88	  If you say Y here, physical addressing will be extended to
89	  32-bits through the SH-4A PMB. If this is not set, legacy
90	  29-bit physical addressing will be used.
91
92config PMB_LEGACY
93	bool "Support legacy boot mappings for PMB"
94	depends on PMB
95	select 32BIT
96	help
97	  If this option is enabled, fixed PMB mappings are inherited
98	  from the boot loader, and the kernel does not attempt dynamic
99	  management. This is the closest to legacy 29-bit physical mode,
100	  and allows systems to support up to 512MiB of system memory.
101
102config X2TLB
103	def_bool y
104	depends on (CPU_SHX2 || CPU_SHX3) && MMU
105
106config VSYSCALL
107	bool "Support vsyscall page"
108	depends on MMU && (CPU_SH3 || CPU_SH4)
109	default y
110	help
111	  This will enable support for the kernel mapping a vDSO page
112	  in process space, and subsequently handing down the entry point
113	  to the libc through the ELF auxiliary vector.
114
115	  From the kernel side this is used for the signal trampoline.
116	  For systems with an MMU that can afford to give up a page,
117	  (the default value) say Y.
118
119config NUMA
120	bool "Non Uniform Memory Access (NUMA) Support"
121	depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
122	default n
123	help
124	  Some SH systems have many various memories scattered around
125	  the address space, each with varying latencies. This enables
126	  support for these blocks by binding them to nodes and allowing
127	  memory policies to be used for prioritizing and controlling
128	  allocation behaviour.
129
130config NODES_SHIFT
131	int
132	default "3" if CPU_SUBTYPE_SHX3
133	default "1"
134	depends on NEED_MULTIPLE_NODES
135
136config ARCH_FLATMEM_ENABLE
137	def_bool y
138	depends on !NUMA
139
140config ARCH_SPARSEMEM_ENABLE
141	def_bool y
142	select SPARSEMEM_STATIC
143
144config ARCH_SPARSEMEM_DEFAULT
145	def_bool y
146
147config MAX_ACTIVE_REGIONS
148	int
149	default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM)
150	default "2" if SPARSEMEM && (CPU_SUBTYPE_SH7722 || \
151		       CPU_SUBTYPE_SH7785)
152	default "1"
153
154config ARCH_POPULATES_NODE_MAP
155	def_bool y
156
157config ARCH_SELECT_MEMORY_MODEL
158	def_bool y
159
160config ARCH_ENABLE_MEMORY_HOTPLUG
161	def_bool y
162	depends on SPARSEMEM && MMU
163
164config ARCH_ENABLE_MEMORY_HOTREMOVE
165	def_bool y
166	depends on SPARSEMEM && MMU
167
168config ARCH_MEMORY_PROBE
169	def_bool y
170	depends on MEMORY_HOTPLUG
171
172config IOREMAP_FIXED
173       def_bool y
174       depends on X2TLB || SUPERH64
175
176choice
177	prompt "Kernel page size"
178	default PAGE_SIZE_4KB
179
180config PAGE_SIZE_4KB
181	bool "4kB"
182	help
183	  This is the default page size used by all SuperH CPUs.
184
185config PAGE_SIZE_8KB
186	bool "8kB"
187	depends on !MMU || X2TLB
188	help
189	  This enables 8kB pages as supported by SH-X2 and later MMUs.
190
191config PAGE_SIZE_16KB
192	bool "16kB"
193	depends on !MMU
194	help
195	  This enables 16kB pages on MMU-less SH systems.
196
197config PAGE_SIZE_64KB
198	bool "64kB"
199	depends on !MMU || CPU_SH4 || CPU_SH5
200	help
201	  This enables support for 64kB pages, possible on all SH-4
202	  CPUs and later.
203
204endchoice
205
206choice
207	prompt "HugeTLB page size"
208	depends on HUGETLB_PAGE
209	default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB
210	default HUGETLB_PAGE_SIZE_64K
211
212config HUGETLB_PAGE_SIZE_64K
213	bool "64kB"
214	depends on !PAGE_SIZE_64KB
215
216config HUGETLB_PAGE_SIZE_256K
217	bool "256kB"
218	depends on X2TLB
219
220config HUGETLB_PAGE_SIZE_1MB
221	bool "1MB"
222
223config HUGETLB_PAGE_SIZE_4MB
224	bool "4MB"
225	depends on X2TLB
226
227config HUGETLB_PAGE_SIZE_64MB
228	bool "64MB"
229	depends on X2TLB
230
231config HUGETLB_PAGE_SIZE_512MB
232	bool "512MB"
233	depends on CPU_SH5
234
235endchoice
236
237source "mm/Kconfig"
238
239config SCHED_MC
240	bool "Multi-core scheduler support"
241	depends on SMP
242	default y
243	help
244	  Multi-core scheduler support improves the CPU scheduler's decision
245	  making when dealing with multi-core CPU chips at a cost of slightly
246	  increased overhead in some places. If unsure say N here.
247
248endmenu
249
250menu "Cache configuration"
251
252config SH7705_CACHE_32KB
253	bool "Enable 32KB cache size for SH7705"
254	depends on CPU_SUBTYPE_SH7705
255	default y
256
257choice
258	prompt "Cache mode"
259	default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5
260	default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
261
262config CACHE_WRITEBACK
263	bool "Write-back"
264
265config CACHE_WRITETHROUGH
266	bool "Write-through"
267	help
268	  Selecting this option will configure the caches in write-through
269	  mode, as opposed to the default write-back configuration.
270
271	  Since there's sill some aliasing issues on SH-4, this option will
272	  unfortunately still require the majority of flushing functions to
273	  be implemented to deal with aliasing.
274
275	  If unsure, say N.
276
277config CACHE_OFF
278	bool "Off"
279
280endchoice
281
282endmenu
283