1menu "Processor selection" 2 3# 4# Processor families 5# 6config CPU_SH2 7 select SH_WRITETHROUGH if !CPU_SH2A 8 bool 9 10config CPU_SH2A 11 bool 12 select CPU_SH2 13 14config CPU_SH3 15 bool 16 select CPU_HAS_INTEVT 17 select CPU_HAS_SR_RB 18 19config CPU_SH4 20 bool 21 select CPU_HAS_INTEVT 22 select CPU_HAS_SR_RB 23 select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2 24 25config CPU_SH4A 26 bool 27 select CPU_SH4 28 29config CPU_SH4AL_DSP 30 bool 31 select CPU_SH4A 32 33config CPU_SUBTYPE_ST40 34 bool 35 select CPU_SH4 36 select CPU_HAS_INTC2_IRQ 37 38config CPU_SHX2 39 bool 40 41# 42# Processor subtypes 43# 44 45comment "SH-2 Processor Support" 46 47config CPU_SUBTYPE_SH7604 48 bool "Support SH7604 processor" 49 select CPU_SH2 50 51config CPU_SUBTYPE_SH7619 52 bool "Support SH7619 processor" 53 select CPU_SH2 54 55comment "SH-2A Processor Support" 56 57config CPU_SUBTYPE_SH7206 58 bool "Support SH7206 processor" 59 select CPU_SH2A 60 61comment "SH-3 Processor Support" 62 63config CPU_SUBTYPE_SH7300 64 bool "Support SH7300 processor" 65 select CPU_SH3 66 67config CPU_SUBTYPE_SH7705 68 bool "Support SH7705 processor" 69 select CPU_SH3 70 select CPU_HAS_PINT_IRQ 71 72config CPU_SUBTYPE_SH7706 73 bool "Support SH7706 processor" 74 select CPU_SH3 75 select CPU_HAS_IPR_IRQ 76 help 77 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU. 78 79config CPU_SUBTYPE_SH7707 80 bool "Support SH7707 processor" 81 select CPU_SH3 82 select CPU_HAS_PINT_IRQ 83 help 84 Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU. 85 86config CPU_SUBTYPE_SH7708 87 bool "Support SH7708 processor" 88 select CPU_SH3 89 help 90 Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or 91 if you have a 100 Mhz SH-3 HD6417708R CPU. 92 93config CPU_SUBTYPE_SH7709 94 bool "Support SH7709 processor" 95 select CPU_SH3 96 select CPU_HAS_IPR_IRQ 97 select CPU_HAS_PINT_IRQ 98 help 99 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU. 100 101config CPU_SUBTYPE_SH7710 102 bool "Support SH7710 processor" 103 select CPU_SH3 104 select CPU_HAS_IPR_IRQ 105 help 106 Select SH7710 if you have a SH3-DSP SH7710 CPU. 107 108config CPU_SUBTYPE_SH7712 109 bool "Support SH7712 processor" 110 select CPU_SH3 111 select CPU_HAS_IPR_IRQ 112 help 113 Select SH7712 if you have a SH3-DSP SH7712 CPU. 114 115comment "SH-4 Processor Support" 116 117config CPU_SUBTYPE_SH7750 118 bool "Support SH7750 processor" 119 select CPU_SH4 120 select CPU_HAS_IPR_IRQ 121 help 122 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU. 123 124config CPU_SUBTYPE_SH7091 125 bool "Support SH7091 processor" 126 select CPU_SH4 127 select CPU_SUBTYPE_SH7750 128 help 129 Select SH7091 if you have an SH-4 based Sega device (such as 130 the Dreamcast, Naomi, and Naomi 2). 131 132config CPU_SUBTYPE_SH7750R 133 bool "Support SH7750R processor" 134 select CPU_SH4 135 select CPU_SUBTYPE_SH7750 136 select CPU_HAS_IPR_IRQ 137 138config CPU_SUBTYPE_SH7750S 139 bool "Support SH7750S processor" 140 select CPU_SH4 141 select CPU_SUBTYPE_SH7750 142 select CPU_HAS_IPR_IRQ 143 144config CPU_SUBTYPE_SH7751 145 bool "Support SH7751 processor" 146 select CPU_SH4 147 select CPU_HAS_IPR_IRQ 148 help 149 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU, 150 or if you have a HD6417751R CPU. 151 152config CPU_SUBTYPE_SH7751R 153 bool "Support SH7751R processor" 154 select CPU_SH4 155 select CPU_SUBTYPE_SH7751 156 select CPU_HAS_IPR_IRQ 157 158config CPU_SUBTYPE_SH7760 159 bool "Support SH7760 processor" 160 select CPU_SH4 161 select CPU_HAS_INTC2_IRQ 162 select CPU_HAS_IPR_IRQ 163 164config CPU_SUBTYPE_SH4_202 165 bool "Support SH4-202 processor" 166 select CPU_SH4 167 168comment "ST40 Processor Support" 169 170config CPU_SUBTYPE_ST40STB1 171 bool "Support ST40STB1/ST40RA processors" 172 select CPU_SUBTYPE_ST40 173 help 174 Select ST40STB1 if you have a ST40RA CPU. 175 This was previously called the ST40STB1, hence the option name. 176 177config CPU_SUBTYPE_ST40GX1 178 bool "Support ST40GX1 processor" 179 select CPU_SUBTYPE_ST40 180 help 181 Select ST40GX1 if you have a ST40GX1 CPU. 182 183comment "SH-4A Processor Support" 184 185config CPU_SUBTYPE_SH7770 186 bool "Support SH7770 processor" 187 select CPU_SH4A 188 189config CPU_SUBTYPE_SH7780 190 bool "Support SH7780 processor" 191 select CPU_SH4A 192 select CPU_HAS_INTC2_IRQ 193 194config CPU_SUBTYPE_SH7785 195 bool "Support SH7785 processor" 196 select CPU_SH4A 197 select CPU_SHX2 198 select CPU_HAS_INTC2_IRQ 199 200comment "SH4AL-DSP Processor Support" 201 202config CPU_SUBTYPE_SH73180 203 bool "Support SH73180 processor" 204 select CPU_SH4AL_DSP 205 206config CPU_SUBTYPE_SH7343 207 bool "Support SH7343 processor" 208 select CPU_SH4AL_DSP 209 210config CPU_SUBTYPE_SH7722 211 bool "Support SH7722 processor" 212 select CPU_SH4AL_DSP 213 select CPU_SHX2 214 select CPU_HAS_IPR_IRQ 215 216endmenu 217 218menu "Memory management options" 219 220config MMU 221 bool "Support for memory management hardware" 222 depends on !CPU_SH2 223 default y 224 help 225 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to 226 boot on these systems, this option must not be set. 227 228 On other systems (such as the SH-3 and 4) where an MMU exists, 229 turning this off will boot the kernel on these machines with the 230 MMU implicitly switched off. 231 232config PAGE_OFFSET 233 hex 234 default "0x80000000" if MMU 235 default "0x00000000" 236 237config MEMORY_START 238 hex "Physical memory start address" 239 default "0x08000000" 240 ---help--- 241 Computers built with Hitachi SuperH processors always 242 map the ROM starting at address zero. But the processor 243 does not specify the range that RAM takes. 244 245 The physical memory (RAM) start address will be automatically 246 set to 08000000. Other platforms, such as the Solution Engine 247 boards typically map RAM at 0C000000. 248 249 Tweak this only when porting to a new machine which does not 250 already have a defconfig. Changing it from the known correct 251 value on any of the known systems will only lead to disaster. 252 253config MEMORY_SIZE 254 hex "Physical memory size" 255 default "0x00400000" 256 help 257 This sets the default memory size assumed by your SH kernel. It can 258 be overridden as normal by the 'mem=' argument on the kernel command 259 line. If unsure, consult your board specifications or just leave it 260 as 0x00400000 which was the default value before this became 261 configurable. 262 263config 32BIT 264 bool "Support 32-bit physical addressing through PMB" 265 depends on CPU_SH4A && MMU && (!X2TLB || BROKEN) 266 default y 267 help 268 If you say Y here, physical addressing will be extended to 269 32-bits through the SH-4A PMB. If this is not set, legacy 270 29-bit physical addressing will be used. 271 272config X2TLB 273 bool "Enable extended TLB mode" 274 depends on CPU_SHX2 && MMU && EXPERIMENTAL 275 help 276 Selecting this option will enable the extended mode of the SH-X2 277 TLB. For legacy SH-X behaviour and interoperability, say N. For 278 all of the fun new features and a willingless to submit bug reports, 279 say Y. 280 281config VSYSCALL 282 bool "Support vsyscall page" 283 depends on MMU 284 default y 285 help 286 This will enable support for the kernel mapping a vDSO page 287 in process space, and subsequently handing down the entry point 288 to the libc through the ELF auxiliary vector. 289 290 From the kernel side this is used for the signal trampoline. 291 For systems with an MMU that can afford to give up a page, 292 (the default value) say Y. 293 294choice 295 prompt "Kernel page size" 296 default PAGE_SIZE_4KB 297 298config PAGE_SIZE_4KB 299 bool "4kB" 300 help 301 This is the default page size used by all SuperH CPUs. 302 303config PAGE_SIZE_8KB 304 bool "8kB" 305 depends on EXPERIMENTAL && X2TLB 306 help 307 This enables 8kB pages as supported by SH-X2 and later MMUs. 308 309config PAGE_SIZE_64KB 310 bool "64kB" 311 depends on EXPERIMENTAL && CPU_SH4 312 help 313 This enables support for 64kB pages, possible on all SH-4 314 CPUs and later. Highly experimental, not recommended. 315 316endchoice 317 318choice 319 prompt "HugeTLB page size" 320 depends on HUGETLB_PAGE && CPU_SH4 && MMU 321 default HUGETLB_PAGE_SIZE_64K 322 323config HUGETLB_PAGE_SIZE_64K 324 bool "64kB" 325 326config HUGETLB_PAGE_SIZE_256K 327 bool "256kB" 328 depends on X2TLB 329 330config HUGETLB_PAGE_SIZE_1MB 331 bool "1MB" 332 333config HUGETLB_PAGE_SIZE_4MB 334 bool "4MB" 335 depends on X2TLB 336 337config HUGETLB_PAGE_SIZE_64MB 338 bool "64MB" 339 depends on X2TLB 340 341endchoice 342 343source "mm/Kconfig" 344 345endmenu 346 347menu "Cache configuration" 348 349config SH7705_CACHE_32KB 350 bool "Enable 32KB cache size for SH7705" 351 depends on CPU_SUBTYPE_SH7705 352 default y 353 354config SH_DIRECT_MAPPED 355 bool "Use direct-mapped caching" 356 default n 357 help 358 Selecting this option will configure the caches to be direct-mapped, 359 even if the cache supports a 2 or 4-way mode. This is useful primarily 360 for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R, 361 SH4-202, SH4-501, etc.) 362 363 Turn this option off for platforms that do not have a direct-mapped 364 cache, and you have no need to run the caches in such a configuration. 365 366config SH_WRITETHROUGH 367 bool "Use write-through caching" 368 help 369 Selecting this option will configure the caches in write-through 370 mode, as opposed to the default write-back configuration. 371 372 Since there's sill some aliasing issues on SH-4, this option will 373 unfortunately still require the majority of flushing functions to 374 be implemented to deal with aliasing. 375 376 If unsure, say N. 377 378config SH_OCRAM 379 bool "Operand Cache RAM (OCRAM) support" 380 help 381 Selecting this option will automatically tear down the number of 382 sets in the dcache by half, which in turn exposes a memory range. 383 384 The addresses for the OC RAM base will vary according to the 385 processor version. Consult vendor documentation for specifics. 386 387 If unsure, say N. 388 389endmenu 390