1menu "Processor selection" 2 3# 4# Processor families 5# 6config CPU_SH2 7 select SH_WRITETHROUGH if !CPU_SH2A 8 bool 9 10config CPU_SH2A 11 bool 12 select CPU_SH2 13 14config CPU_SH3 15 bool 16 select CPU_HAS_INTEVT 17 select CPU_HAS_SR_RB 18 19config CPU_SH4 20 bool 21 select CPU_HAS_INTEVT 22 select CPU_HAS_SR_RB 23 select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2 24 25config CPU_SH4A 26 bool 27 select CPU_SH4 28 29config CPU_SH4AL_DSP 30 bool 31 select CPU_SH4A 32 33config CPU_SUBTYPE_ST40 34 bool 35 select CPU_SH4 36 select CPU_HAS_INTC2_IRQ 37 38config CPU_SHX2 39 bool 40 41# 42# Processor subtypes 43# 44 45comment "SH-2 Processor Support" 46 47config CPU_SUBTYPE_SH7604 48 bool "Support SH7604 processor" 49 select CPU_SH2 50 51config CPU_SUBTYPE_SH7619 52 bool "Support SH7619 processor" 53 select CPU_SH2 54 55comment "SH-2A Processor Support" 56 57config CPU_SUBTYPE_SH7206 58 bool "Support SH7206 processor" 59 select CPU_SH2A 60 61comment "SH-3 Processor Support" 62 63config CPU_SUBTYPE_SH7300 64 bool "Support SH7300 processor" 65 select CPU_SH3 66 67config CPU_SUBTYPE_SH7705 68 bool "Support SH7705 processor" 69 select CPU_SH3 70 select CPU_HAS_IPR_IRQ 71 select CPU_HAS_PINT_IRQ 72 73config CPU_SUBTYPE_SH7706 74 bool "Support SH7706 processor" 75 select CPU_SH3 76 select CPU_HAS_IPR_IRQ 77 help 78 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU. 79 80config CPU_SUBTYPE_SH7707 81 bool "Support SH7707 processor" 82 select CPU_SH3 83 select CPU_HAS_PINT_IRQ 84 help 85 Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU. 86 87config CPU_SUBTYPE_SH7708 88 bool "Support SH7708 processor" 89 select CPU_SH3 90 help 91 Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or 92 if you have a 100 Mhz SH-3 HD6417708R CPU. 93 94config CPU_SUBTYPE_SH7709 95 bool "Support SH7709 processor" 96 select CPU_SH3 97 select CPU_HAS_IPR_IRQ 98 select CPU_HAS_PINT_IRQ 99 help 100 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU. 101 102config CPU_SUBTYPE_SH7710 103 bool "Support SH7710 processor" 104 select CPU_SH3 105 select CPU_HAS_IPR_IRQ 106 help 107 Select SH7710 if you have a SH3-DSP SH7710 CPU. 108 109config CPU_SUBTYPE_SH7712 110 bool "Support SH7712 processor" 111 select CPU_SH3 112 select CPU_HAS_IPR_IRQ 113 help 114 Select SH7712 if you have a SH3-DSP SH7712 CPU. 115 116comment "SH-4 Processor Support" 117 118config CPU_SUBTYPE_SH7750 119 bool "Support SH7750 processor" 120 select CPU_SH4 121 select CPU_HAS_IPR_IRQ 122 help 123 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU. 124 125config CPU_SUBTYPE_SH7091 126 bool "Support SH7091 processor" 127 select CPU_SH4 128 select CPU_SUBTYPE_SH7750 129 help 130 Select SH7091 if you have an SH-4 based Sega device (such as 131 the Dreamcast, Naomi, and Naomi 2). 132 133config CPU_SUBTYPE_SH7750R 134 bool "Support SH7750R processor" 135 select CPU_SH4 136 select CPU_SUBTYPE_SH7750 137 select CPU_HAS_IPR_IRQ 138 139config CPU_SUBTYPE_SH7750S 140 bool "Support SH7750S processor" 141 select CPU_SH4 142 select CPU_SUBTYPE_SH7750 143 select CPU_HAS_IPR_IRQ 144 145config CPU_SUBTYPE_SH7751 146 bool "Support SH7751 processor" 147 select CPU_SH4 148 select CPU_HAS_IPR_IRQ 149 help 150 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU, 151 or if you have a HD6417751R CPU. 152 153config CPU_SUBTYPE_SH7751R 154 bool "Support SH7751R processor" 155 select CPU_SH4 156 select CPU_SUBTYPE_SH7751 157 select CPU_HAS_IPR_IRQ 158 159config CPU_SUBTYPE_SH7760 160 bool "Support SH7760 processor" 161 select CPU_SH4 162 select CPU_HAS_INTC2_IRQ 163 select CPU_HAS_IPR_IRQ 164 165config CPU_SUBTYPE_SH4_202 166 bool "Support SH4-202 processor" 167 select CPU_SH4 168 169comment "ST40 Processor Support" 170 171config CPU_SUBTYPE_ST40STB1 172 bool "Support ST40STB1/ST40RA processors" 173 select CPU_SUBTYPE_ST40 174 help 175 Select ST40STB1 if you have a ST40RA CPU. 176 This was previously called the ST40STB1, hence the option name. 177 178config CPU_SUBTYPE_ST40GX1 179 bool "Support ST40GX1 processor" 180 select CPU_SUBTYPE_ST40 181 help 182 Select ST40GX1 if you have a ST40GX1 CPU. 183 184comment "SH-4A Processor Support" 185 186config CPU_SUBTYPE_SH7770 187 bool "Support SH7770 processor" 188 select CPU_SH4A 189 190config CPU_SUBTYPE_SH7780 191 bool "Support SH7780 processor" 192 select CPU_SH4A 193 select CPU_HAS_INTC2_IRQ 194 195config CPU_SUBTYPE_SH7785 196 bool "Support SH7785 processor" 197 select CPU_SH4A 198 select CPU_SHX2 199 select CPU_HAS_INTC2_IRQ 200 201comment "SH4AL-DSP Processor Support" 202 203config CPU_SUBTYPE_SH73180 204 bool "Support SH73180 processor" 205 select CPU_SH4AL_DSP 206 207config CPU_SUBTYPE_SH7343 208 bool "Support SH7343 processor" 209 select CPU_SH4AL_DSP 210 211config CPU_SUBTYPE_SH7722 212 bool "Support SH7722 processor" 213 select CPU_SH4AL_DSP 214 select CPU_SHX2 215 select CPU_HAS_IPR_IRQ 216 217endmenu 218 219menu "Memory management options" 220 221config QUICKLIST 222 def_bool y 223 224config MMU 225 bool "Support for memory management hardware" 226 depends on !CPU_SH2 227 default y 228 help 229 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to 230 boot on these systems, this option must not be set. 231 232 On other systems (such as the SH-3 and 4) where an MMU exists, 233 turning this off will boot the kernel on these machines with the 234 MMU implicitly switched off. 235 236config PAGE_OFFSET 237 hex 238 default "0x80000000" if MMU 239 default "0x00000000" 240 241config MEMORY_START 242 hex "Physical memory start address" 243 default "0x08000000" 244 ---help--- 245 Computers built with Hitachi SuperH processors always 246 map the ROM starting at address zero. But the processor 247 does not specify the range that RAM takes. 248 249 The physical memory (RAM) start address will be automatically 250 set to 08000000. Other platforms, such as the Solution Engine 251 boards typically map RAM at 0C000000. 252 253 Tweak this only when porting to a new machine which does not 254 already have a defconfig. Changing it from the known correct 255 value on any of the known systems will only lead to disaster. 256 257config MEMORY_SIZE 258 hex "Physical memory size" 259 default "0x00400000" 260 help 261 This sets the default memory size assumed by your SH kernel. It can 262 be overridden as normal by the 'mem=' argument on the kernel command 263 line. If unsure, consult your board specifications or just leave it 264 as 0x00400000 which was the default value before this became 265 configurable. 266 267config 32BIT 268 bool "Support 32-bit physical addressing through PMB" 269 depends on CPU_SH4A && MMU && (!X2TLB || BROKEN) 270 default y 271 help 272 If you say Y here, physical addressing will be extended to 273 32-bits through the SH-4A PMB. If this is not set, legacy 274 29-bit physical addressing will be used. 275 276config X2TLB 277 bool "Enable extended TLB mode" 278 depends on CPU_SHX2 && MMU && EXPERIMENTAL 279 help 280 Selecting this option will enable the extended mode of the SH-X2 281 TLB. For legacy SH-X behaviour and interoperability, say N. For 282 all of the fun new features and a willingless to submit bug reports, 283 say Y. 284 285config VSYSCALL 286 bool "Support vsyscall page" 287 depends on MMU 288 default y 289 help 290 This will enable support for the kernel mapping a vDSO page 291 in process space, and subsequently handing down the entry point 292 to the libc through the ELF auxiliary vector. 293 294 From the kernel side this is used for the signal trampoline. 295 For systems with an MMU that can afford to give up a page, 296 (the default value) say Y. 297 298config NODES_SHIFT 299 int 300 default "1" 301 depends on NEED_MULTIPLE_NODES 302 303config ARCH_FLATMEM_ENABLE 304 def_bool y 305 306config MAX_ACTIVE_REGIONS 307 int 308 default "1" 309 310config ARCH_POPULATES_NODE_MAP 311 def_bool y 312 313choice 314 prompt "Kernel page size" 315 default PAGE_SIZE_4KB 316 317config PAGE_SIZE_4KB 318 bool "4kB" 319 help 320 This is the default page size used by all SuperH CPUs. 321 322config PAGE_SIZE_8KB 323 bool "8kB" 324 depends on EXPERIMENTAL && X2TLB 325 help 326 This enables 8kB pages as supported by SH-X2 and later MMUs. 327 328config PAGE_SIZE_64KB 329 bool "64kB" 330 depends on EXPERIMENTAL && CPU_SH4 331 help 332 This enables support for 64kB pages, possible on all SH-4 333 CPUs and later. Highly experimental, not recommended. 334 335endchoice 336 337choice 338 prompt "HugeTLB page size" 339 depends on HUGETLB_PAGE && CPU_SH4 && MMU 340 default HUGETLB_PAGE_SIZE_64K 341 342config HUGETLB_PAGE_SIZE_64K 343 bool "64kB" 344 345config HUGETLB_PAGE_SIZE_256K 346 bool "256kB" 347 depends on X2TLB 348 349config HUGETLB_PAGE_SIZE_1MB 350 bool "1MB" 351 352config HUGETLB_PAGE_SIZE_4MB 353 bool "4MB" 354 depends on X2TLB 355 356config HUGETLB_PAGE_SIZE_64MB 357 bool "64MB" 358 depends on X2TLB 359 360endchoice 361 362source "mm/Kconfig" 363 364endmenu 365 366menu "Cache configuration" 367 368config SH7705_CACHE_32KB 369 bool "Enable 32KB cache size for SH7705" 370 depends on CPU_SUBTYPE_SH7705 371 default y 372 373config SH_DIRECT_MAPPED 374 bool "Use direct-mapped caching" 375 default n 376 help 377 Selecting this option will configure the caches to be direct-mapped, 378 even if the cache supports a 2 or 4-way mode. This is useful primarily 379 for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R, 380 SH4-202, SH4-501, etc.) 381 382 Turn this option off for platforms that do not have a direct-mapped 383 cache, and you have no need to run the caches in such a configuration. 384 385config SH_WRITETHROUGH 386 bool "Use write-through caching" 387 help 388 Selecting this option will configure the caches in write-through 389 mode, as opposed to the default write-back configuration. 390 391 Since there's sill some aliasing issues on SH-4, this option will 392 unfortunately still require the majority of flushing functions to 393 be implemented to deal with aliasing. 394 395 If unsure, say N. 396 397config SH_OCRAM 398 bool "Operand Cache RAM (OCRAM) support" 399 help 400 Selecting this option will automatically tear down the number of 401 sets in the dcache by half, which in turn exposes a memory range. 402 403 The addresses for the OC RAM base will vary according to the 404 processor version. Consult vendor documentation for specifics. 405 406 If unsure, say N. 407 408endmenu 409