xref: /openbmc/linux/arch/sh/mm/Kconfig (revision 5e9daa0f) 
1menu "Memory management options"
2
3config QUICKLIST
4	def_bool y
5
6config MMU
7        bool "Support for memory management hardware"
8	depends on !CPU_SH2
9	default y
10	help
11	  Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
12	  boot on these systems, this option must not be set.
13
14	  On other systems (such as the SH-3 and 4) where an MMU exists,
15	  turning this off will boot the kernel on these machines with the
16	  MMU implicitly switched off.
17
18config PAGE_OFFSET
19	hex
20	default "0x80000000" if MMU && SUPERH32
21	default "0x20000000" if MMU && SUPERH64
22	default "0x00000000"
23
24config FORCE_MAX_ZONEORDER
25	int "Maximum zone order"
26	range 9 64 if PAGE_SIZE_16KB
27	default "9" if PAGE_SIZE_16KB
28	range 7 64 if PAGE_SIZE_64KB
29	default "7" if PAGE_SIZE_64KB
30	range 11 64
31	default "14" if !MMU
32	default "11"
33	help
34	  The kernel memory allocator divides physically contiguous memory
35	  blocks into "zones", where each zone is a power of two number of
36	  pages.  This option selects the largest power of two that the kernel
37	  keeps in the memory allocator.  If you need to allocate very large
38	  blocks of physically contiguous memory, then you may need to
39	  increase this value.
40
41	  This config option is actually maximum order plus one. For example,
42	  a value of 11 means that the largest free memory block is 2^10 pages.
43
44	  The page size is not necessarily 4KB. Keep this in mind when
45	  choosing a value for this option.
46
47config MEMORY_START
48	hex "Physical memory start address"
49	default "0x08000000"
50	---help---
51	  Computers built with Hitachi SuperH processors always
52	  map the ROM starting at address zero.  But the processor
53	  does not specify the range that RAM takes.
54
55	  The physical memory (RAM) start address will be automatically
56	  set to 08000000. Other platforms, such as the Solution Engine
57	  boards typically map RAM at 0C000000.
58
59	  Tweak this only when porting to a new machine which does not
60	  already have a defconfig. Changing it from the known correct
61	  value on any of the known systems will only lead to disaster.
62
63config MEMORY_SIZE
64	hex "Physical memory size"
65	default "0x04000000"
66	help
67	  This sets the default memory size assumed by your SH kernel. It can
68	  be overridden as normal by the 'mem=' argument on the kernel command
69	  line. If unsure, consult your board specifications or just leave it
70	  as 0x04000000 which was the default value before this became
71	  configurable.
72
73# Physical addressing modes
74
75config 29BIT
76	def_bool !32BIT
77	depends on SUPERH32
78
79config 32BIT
80	bool
81	default y if CPU_SH5
82
83config PMB_ENABLE
84	bool "Support 32-bit physical addressing through PMB"
85	depends on MMU && EXPERIMENTAL && CPU_SH4A && !CPU_SH4AL_DSP
86	help
87	  If you say Y here, physical addressing will be extended to
88	  32-bits through the SH-4A PMB. If this is not set, legacy
89	  29-bit physical addressing will be used.
90
91choice
92	prompt "PMB handling type"
93	depends on PMB_ENABLE
94	default PMB_FIXED
95
96config PMB
97	bool "PMB"
98	depends on MMU && EXPERIMENTAL && CPU_SH4A && !CPU_SH4AL_DSP
99	help
100	  If you say Y here, physical addressing will be extended to
101	  32-bits through the SH-4A PMB. If this is not set, legacy
102	  29-bit physical addressing will be used.
103
104config PMB_FIXED
105	bool "fixed PMB"
106	depends on MMU && EXPERIMENTAL && CPU_SH4A && !CPU_SH4AL_DSP
107	select 32BIT
108	help
109	  If this option is enabled, fixed PMB mappings are inherited
110	  from the boot loader, and the kernel does not attempt dynamic
111	  management. This is the closest to legacy 29-bit physical mode,
112	  and allows systems to support up to 512MiB of system memory.
113
114endchoice
115
116config X2TLB
117	bool "Enable extended TLB mode"
118	depends on (CPU_SHX2 || CPU_SHX3) && MMU && EXPERIMENTAL
119	help
120	  Selecting this option will enable the extended mode of the SH-X2
121	  TLB. For legacy SH-X behaviour and interoperability, say N. For
122	  all of the fun new features and a willingless to submit bug reports,
123	  say Y.
124
125config VSYSCALL
126	bool "Support vsyscall page"
127	depends on MMU && (CPU_SH3 || CPU_SH4)
128	default y
129	help
130	  This will enable support for the kernel mapping a vDSO page
131	  in process space, and subsequently handing down the entry point
132	  to the libc through the ELF auxiliary vector.
133
134	  From the kernel side this is used for the signal trampoline.
135	  For systems with an MMU that can afford to give up a page,
136	  (the default value) say Y.
137
138config NUMA
139	bool "Non Uniform Memory Access (NUMA) Support"
140	depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
141	default n
142	help
143	  Some SH systems have many various memories scattered around
144	  the address space, each with varying latencies. This enables
145	  support for these blocks by binding them to nodes and allowing
146	  memory policies to be used for prioritizing and controlling
147	  allocation behaviour.
148
149config NODES_SHIFT
150	int
151	default "3" if CPU_SUBTYPE_SHX3
152	default "1"
153	depends on NEED_MULTIPLE_NODES
154
155config ARCH_FLATMEM_ENABLE
156	def_bool y
157	depends on !NUMA
158
159config ARCH_SPARSEMEM_ENABLE
160	def_bool y
161	select SPARSEMEM_STATIC
162
163config ARCH_SPARSEMEM_DEFAULT
164	def_bool y
165
166config MAX_ACTIVE_REGIONS
167	int
168	default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM)
169	default "2" if SPARSEMEM && (CPU_SUBTYPE_SH7722 || \
170		       CPU_SUBTYPE_SH7785)
171	default "1"
172
173config ARCH_POPULATES_NODE_MAP
174	def_bool y
175
176config ARCH_SELECT_MEMORY_MODEL
177	def_bool y
178
179config ARCH_ENABLE_MEMORY_HOTPLUG
180	def_bool y
181	depends on SPARSEMEM && MMU
182
183config ARCH_ENABLE_MEMORY_HOTREMOVE
184	def_bool y
185	depends on SPARSEMEM && MMU
186
187config ARCH_MEMORY_PROBE
188	def_bool y
189	depends on MEMORY_HOTPLUG
190
191choice
192	prompt "Kernel page size"
193	default PAGE_SIZE_8KB if X2TLB
194	default PAGE_SIZE_4KB
195
196config PAGE_SIZE_4KB
197	bool "4kB"
198	depends on !MMU || !X2TLB
199	help
200	  This is the default page size used by all SuperH CPUs.
201
202config PAGE_SIZE_8KB
203	bool "8kB"
204	depends on !MMU || X2TLB
205	help
206	  This enables 8kB pages as supported by SH-X2 and later MMUs.
207
208config PAGE_SIZE_16KB
209	bool "16kB"
210	depends on !MMU
211	help
212	  This enables 16kB pages on MMU-less SH systems.
213
214config PAGE_SIZE_64KB
215	bool "64kB"
216	depends on !MMU || CPU_SH4 || CPU_SH5
217	help
218	  This enables support for 64kB pages, possible on all SH-4
219	  CPUs and later.
220
221endchoice
222
223choice
224	prompt "HugeTLB page size"
225	depends on HUGETLB_PAGE
226	default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB
227	default HUGETLB_PAGE_SIZE_64K
228
229config HUGETLB_PAGE_SIZE_64K
230	bool "64kB"
231	depends on !PAGE_SIZE_64KB
232
233config HUGETLB_PAGE_SIZE_256K
234	bool "256kB"
235	depends on X2TLB
236
237config HUGETLB_PAGE_SIZE_1MB
238	bool "1MB"
239
240config HUGETLB_PAGE_SIZE_4MB
241	bool "4MB"
242	depends on X2TLB
243
244config HUGETLB_PAGE_SIZE_64MB
245	bool "64MB"
246	depends on X2TLB
247
248config HUGETLB_PAGE_SIZE_512MB
249	bool "512MB"
250	depends on CPU_SH5
251
252endchoice
253
254source "mm/Kconfig"
255
256config SCHED_MC
257	bool "Multi-core scheduler support"
258	depends on SMP
259	default y
260	help
261	  Multi-core scheduler support improves the CPU scheduler's decision
262	  making when dealing with multi-core CPU chips at a cost of slightly
263	  increased overhead in some places. If unsure say N here.
264
265endmenu
266
267menu "Cache configuration"
268
269config SH7705_CACHE_32KB
270	bool "Enable 32KB cache size for SH7705"
271	depends on CPU_SUBTYPE_SH7705
272	default y
273
274choice
275	prompt "Cache mode"
276	default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5
277	default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
278
279config CACHE_WRITEBACK
280	bool "Write-back"
281
282config CACHE_WRITETHROUGH
283	bool "Write-through"
284	help
285	  Selecting this option will configure the caches in write-through
286	  mode, as opposed to the default write-back configuration.
287
288	  Since there's sill some aliasing issues on SH-4, this option will
289	  unfortunately still require the majority of flushing functions to
290	  be implemented to deal with aliasing.
291
292	  If unsure, say N.
293
294config CACHE_OFF
295	bool "Off"
296
297endchoice
298
299endmenu
300