xref: /openbmc/linux/arch/sh/mm/Kconfig (revision 2a8ff459)
1menu "Processor selection"
2
3#
4# Processor families
5#
6config CPU_SH2
7	select SH_WRITETHROUGH if !CPU_SH2A
8	bool
9
10config CPU_SH2A
11	bool
12	select CPU_SH2
13
14config CPU_SH3
15	bool
16	select CPU_HAS_INTEVT
17	select CPU_HAS_SR_RB
18
19config CPU_SH4
20	bool
21	select CPU_HAS_INTEVT
22	select CPU_HAS_SR_RB
23	select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2
24
25config CPU_SH4A
26	bool
27	select CPU_SH4
28
29config CPU_SH4AL_DSP
30	bool
31	select CPU_SH4A
32
33config CPU_SUBTYPE_ST40
34	bool
35	select CPU_SH4
36	select CPU_HAS_INTC2_IRQ
37
38config CPU_SHX2
39	bool
40
41#
42# Processor subtypes
43#
44
45comment "SH-2 Processor Support"
46
47config CPU_SUBTYPE_SH7604
48	bool "Support SH7604 processor"
49	select CPU_SH2
50
51config CPU_SUBTYPE_SH7619
52	bool "Support SH7619 processor"
53	select CPU_SH2
54
55comment "SH-2A Processor Support"
56
57config CPU_SUBTYPE_SH7206
58	bool "Support SH7206 processor"
59	select CPU_SH2A
60
61comment "SH-3 Processor Support"
62
63config CPU_SUBTYPE_SH7300
64	bool "Support SH7300 processor"
65	select CPU_SH3
66
67config CPU_SUBTYPE_SH7705
68	bool "Support SH7705 processor"
69	select CPU_SH3
70	select CPU_HAS_IPR_IRQ
71	select CPU_HAS_PINT_IRQ
72
73config CPU_SUBTYPE_SH7706
74	bool "Support SH7706 processor"
75	select CPU_SH3
76	select CPU_HAS_IPR_IRQ
77	help
78	  Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
79
80config CPU_SUBTYPE_SH7707
81	bool "Support SH7707 processor"
82	select CPU_SH3
83	select CPU_HAS_PINT_IRQ
84	help
85	  Select SH7707 if you have a  60 Mhz SH-3 HD6417707 CPU.
86
87config CPU_SUBTYPE_SH7708
88	bool "Support SH7708 processor"
89	select CPU_SH3
90	help
91	  Select SH7708 if you have a  60 Mhz SH-3 HD6417708S or
92	  if you have a 100 Mhz SH-3 HD6417708R CPU.
93
94config CPU_SUBTYPE_SH7709
95	bool "Support SH7709 processor"
96	select CPU_SH3
97	select CPU_HAS_IPR_IRQ
98	select CPU_HAS_PINT_IRQ
99	help
100	  Select SH7709 if you have a  80 Mhz SH-3 HD6417709 CPU.
101
102config CPU_SUBTYPE_SH7710
103	bool "Support SH7710 processor"
104	select CPU_SH3
105	select CPU_HAS_IPR_IRQ
106	help
107	  Select SH7710 if you have a SH3-DSP SH7710 CPU.
108
109config CPU_SUBTYPE_SH7712
110	bool "Support SH7712 processor"
111	select CPU_SH3
112	select CPU_HAS_IPR_IRQ
113	help
114	  Select SH7712 if you have a SH3-DSP SH7712 CPU.
115
116comment "SH-4 Processor Support"
117
118config CPU_SUBTYPE_SH7750
119	bool "Support SH7750 processor"
120	select CPU_SH4
121	select CPU_HAS_IPR_IRQ
122	help
123	  Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
124
125config CPU_SUBTYPE_SH7091
126	bool "Support SH7091 processor"
127	select CPU_SH4
128	select CPU_SUBTYPE_SH7750
129	help
130	  Select SH7091 if you have an SH-4 based Sega device (such as
131	  the Dreamcast, Naomi, and Naomi 2).
132
133config CPU_SUBTYPE_SH7750R
134	bool "Support SH7750R processor"
135	select CPU_SH4
136	select CPU_SUBTYPE_SH7750
137	select CPU_HAS_IPR_IRQ
138
139config CPU_SUBTYPE_SH7750S
140	bool "Support SH7750S processor"
141	select CPU_SH4
142	select CPU_SUBTYPE_SH7750
143	select CPU_HAS_IPR_IRQ
144
145config CPU_SUBTYPE_SH7751
146	bool "Support SH7751 processor"
147	select CPU_SH4
148	select CPU_HAS_IPR_IRQ
149	help
150	  Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
151	  or if you have a HD6417751R CPU.
152
153config CPU_SUBTYPE_SH7751R
154	bool "Support SH7751R processor"
155	select CPU_SH4
156	select CPU_SUBTYPE_SH7751
157	select CPU_HAS_IPR_IRQ
158
159config CPU_SUBTYPE_SH7760
160	bool "Support SH7760 processor"
161	select CPU_SH4
162	select CPU_HAS_INTC2_IRQ
163	select CPU_HAS_IPR_IRQ
164
165config CPU_SUBTYPE_SH4_202
166	bool "Support SH4-202 processor"
167	select CPU_SH4
168
169comment "ST40 Processor Support"
170
171config CPU_SUBTYPE_ST40STB1
172	bool "Support ST40STB1/ST40RA processors"
173	select CPU_SUBTYPE_ST40
174	help
175	  Select ST40STB1 if you have a ST40RA CPU.
176	  This was previously called the ST40STB1, hence the option name.
177
178config CPU_SUBTYPE_ST40GX1
179	bool "Support ST40GX1 processor"
180	select CPU_SUBTYPE_ST40
181	help
182	  Select ST40GX1 if you have a ST40GX1 CPU.
183
184comment "SH-4A Processor Support"
185
186config CPU_SUBTYPE_SH7770
187	bool "Support SH7770 processor"
188	select CPU_SH4A
189
190config CPU_SUBTYPE_SH7780
191	bool "Support SH7780 processor"
192	select CPU_SH4A
193	select CPU_HAS_INTC2_IRQ
194
195config CPU_SUBTYPE_SH7785
196	bool "Support SH7785 processor"
197	select CPU_SH4A
198	select CPU_SHX2
199	select CPU_HAS_INTC2_IRQ
200
201comment "SH4AL-DSP Processor Support"
202
203config CPU_SUBTYPE_SH73180
204	bool "Support SH73180 processor"
205	select CPU_SH4AL_DSP
206
207config CPU_SUBTYPE_SH7343
208	bool "Support SH7343 processor"
209	select CPU_SH4AL_DSP
210
211config CPU_SUBTYPE_SH7722
212	bool "Support SH7722 processor"
213	select CPU_SH4AL_DSP
214	select CPU_SHX2
215	select CPU_HAS_IPR_IRQ
216
217endmenu
218
219menu "Memory management options"
220
221config MMU
222        bool "Support for memory management hardware"
223	depends on !CPU_SH2
224	default y
225	help
226	  Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
227	  boot on these systems, this option must not be set.
228
229	  On other systems (such as the SH-3 and 4) where an MMU exists,
230	  turning this off will boot the kernel on these machines with the
231	  MMU implicitly switched off.
232
233config PAGE_OFFSET
234	hex
235	default "0x80000000" if MMU
236	default "0x00000000"
237
238config MEMORY_START
239	hex "Physical memory start address"
240	default "0x08000000"
241	---help---
242	  Computers built with Hitachi SuperH processors always
243	  map the ROM starting at address zero.  But the processor
244	  does not specify the range that RAM takes.
245
246	  The physical memory (RAM) start address will be automatically
247	  set to 08000000. Other platforms, such as the Solution Engine
248	  boards typically map RAM at 0C000000.
249
250	  Tweak this only when porting to a new machine which does not
251	  already have a defconfig. Changing it from the known correct
252	  value on any of the known systems will only lead to disaster.
253
254config MEMORY_SIZE
255	hex "Physical memory size"
256	default "0x00400000"
257	help
258	  This sets the default memory size assumed by your SH kernel. It can
259	  be overridden as normal by the 'mem=' argument on the kernel command
260	  line. If unsure, consult your board specifications or just leave it
261	  as 0x00400000 which was the default value before this became
262	  configurable.
263
264config 32BIT
265	bool "Support 32-bit physical addressing through PMB"
266	depends on CPU_SH4A && MMU && (!X2TLB || BROKEN)
267	default y
268	help
269	  If you say Y here, physical addressing will be extended to
270	  32-bits through the SH-4A PMB. If this is not set, legacy
271	  29-bit physical addressing will be used.
272
273config X2TLB
274	bool "Enable extended TLB mode"
275	depends on CPU_SHX2 && MMU && EXPERIMENTAL
276	help
277	  Selecting this option will enable the extended mode of the SH-X2
278	  TLB. For legacy SH-X behaviour and interoperability, say N. For
279	  all of the fun new features and a willingless to submit bug reports,
280	  say Y.
281
282config VSYSCALL
283	bool "Support vsyscall page"
284	depends on MMU
285	default y
286	help
287	  This will enable support for the kernel mapping a vDSO page
288	  in process space, and subsequently handing down the entry point
289	  to the libc through the ELF auxiliary vector.
290
291	  From the kernel side this is used for the signal trampoline.
292	  For systems with an MMU that can afford to give up a page,
293	  (the default value) say Y.
294
295config NODES_SHIFT
296	int
297	default "1"
298	depends on NEED_MULTIPLE_NODES
299
300config ARCH_FLATMEM_ENABLE
301	def_bool y
302
303config ARCH_POPULATES_NODE_MAP
304	def_bool y
305
306choice
307	prompt "Kernel page size"
308	default PAGE_SIZE_4KB
309
310config PAGE_SIZE_4KB
311	bool "4kB"
312	help
313	  This is the default page size used by all SuperH CPUs.
314
315config PAGE_SIZE_8KB
316	bool "8kB"
317	depends on EXPERIMENTAL && X2TLB
318	help
319	  This enables 8kB pages as supported by SH-X2 and later MMUs.
320
321config PAGE_SIZE_64KB
322	bool "64kB"
323	depends on EXPERIMENTAL && CPU_SH4
324	help
325	  This enables support for 64kB pages, possible on all SH-4
326	  CPUs and later. Highly experimental, not recommended.
327
328endchoice
329
330choice
331	prompt "HugeTLB page size"
332	depends on HUGETLB_PAGE && CPU_SH4 && MMU
333	default HUGETLB_PAGE_SIZE_64K
334
335config HUGETLB_PAGE_SIZE_64K
336	bool "64kB"
337
338config HUGETLB_PAGE_SIZE_256K
339	bool "256kB"
340	depends on X2TLB
341
342config HUGETLB_PAGE_SIZE_1MB
343	bool "1MB"
344
345config HUGETLB_PAGE_SIZE_4MB
346	bool "4MB"
347	depends on X2TLB
348
349config HUGETLB_PAGE_SIZE_64MB
350	bool "64MB"
351	depends on X2TLB
352
353endchoice
354
355source "mm/Kconfig"
356
357endmenu
358
359menu "Cache configuration"
360
361config SH7705_CACHE_32KB
362	bool "Enable 32KB cache size for SH7705"
363	depends on CPU_SUBTYPE_SH7705
364	default y
365
366config SH_DIRECT_MAPPED
367	bool "Use direct-mapped caching"
368	default n
369	help
370	  Selecting this option will configure the caches to be direct-mapped,
371	  even if the cache supports a 2 or 4-way mode. This is useful primarily
372	  for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
373	  SH4-202, SH4-501, etc.)
374
375	  Turn this option off for platforms that do not have a direct-mapped
376	  cache, and you have no need to run the caches in such a configuration.
377
378config SH_WRITETHROUGH
379	bool "Use write-through caching"
380	help
381	  Selecting this option will configure the caches in write-through
382	  mode, as opposed to the default write-back configuration.
383
384	  Since there's sill some aliasing issues on SH-4, this option will
385	  unfortunately still require the majority of flushing functions to
386	  be implemented to deal with aliasing.
387
388	  If unsure, say N.
389
390config SH_OCRAM
391	bool "Operand Cache RAM (OCRAM) support"
392	help
393	  Selecting this option will automatically tear down the number of
394	  sets in the dcache by half, which in turn exposes a memory range.
395
396	  The addresses for the OC RAM base will vary according to the
397	  processor version. Consult vendor documentation for specifics.
398
399	  If unsure, say N.
400
401endmenu
402