1menu "Memory management options" 2 3config QUICKLIST 4 def_bool y 5 6config MMU 7 bool "Support for memory management hardware" 8 depends on !CPU_SH2 9 default y 10 help 11 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to 12 boot on these systems, this option must not be set. 13 14 On other systems (such as the SH-3 and 4) where an MMU exists, 15 turning this off will boot the kernel on these machines with the 16 MMU implicitly switched off. 17 18config PAGE_OFFSET 19 hex 20 default "0x80000000" if MMU && SUPERH32 21 default "0x20000000" if MMU && SUPERH64 22 default "0x00000000" 23 24config FORCE_MAX_ZONEORDER 25 int "Maximum zone order" 26 range 9 64 if PAGE_SIZE_16KB 27 default "9" if PAGE_SIZE_16KB 28 range 7 64 if PAGE_SIZE_64KB 29 default "7" if PAGE_SIZE_64KB 30 range 11 64 31 default "14" if !MMU 32 default "11" 33 help 34 The kernel memory allocator divides physically contiguous memory 35 blocks into "zones", where each zone is a power of two number of 36 pages. This option selects the largest power of two that the kernel 37 keeps in the memory allocator. If you need to allocate very large 38 blocks of physically contiguous memory, then you may need to 39 increase this value. 40 41 This config option is actually maximum order plus one. For example, 42 a value of 11 means that the largest free memory block is 2^10 pages. 43 44 The page size is not necessarily 4KB. Keep this in mind when 45 choosing a value for this option. 46 47config MEMORY_START 48 hex "Physical memory start address" 49 default "0x08000000" 50 ---help--- 51 Computers built with Hitachi SuperH processors always 52 map the ROM starting at address zero. But the processor 53 does not specify the range that RAM takes. 54 55 The physical memory (RAM) start address will be automatically 56 set to 08000000. Other platforms, such as the Solution Engine 57 boards typically map RAM at 0C000000. 58 59 Tweak this only when porting to a new machine which does not 60 already have a defconfig. Changing it from the known correct 61 value on any of the known systems will only lead to disaster. 62 63config MEMORY_SIZE 64 hex "Physical memory size" 65 default "0x04000000" 66 help 67 This sets the default memory size assumed by your SH kernel. It can 68 be overridden as normal by the 'mem=' argument on the kernel command 69 line. If unsure, consult your board specifications or just leave it 70 as 0x04000000 which was the default value before this became 71 configurable. 72 73# Physical addressing modes 74 75config 29BIT 76 def_bool !32BIT 77 depends on SUPERH32 78 select UNCACHED_MAPPING 79 80config 32BIT 81 bool 82 default y if CPU_SH5 || !MMU 83 84config PMB 85 bool "Support 32-bit physical addressing through PMB" 86 depends on MMU && CPU_SH4A && !CPU_SH4AL_DSP 87 select 32BIT 88 select UNCACHED_MAPPING 89 help 90 If you say Y here, physical addressing will be extended to 91 32-bits through the SH-4A PMB. If this is not set, legacy 92 29-bit physical addressing will be used. 93 94config X2TLB 95 def_bool y 96 depends on (CPU_SHX2 || CPU_SHX3) && MMU 97 98config VSYSCALL 99 bool "Support vsyscall page" 100 depends on MMU && (CPU_SH3 || CPU_SH4) 101 default y 102 help 103 This will enable support for the kernel mapping a vDSO page 104 in process space, and subsequently handing down the entry point 105 to the libc through the ELF auxiliary vector. 106 107 From the kernel side this is used for the signal trampoline. 108 For systems with an MMU that can afford to give up a page, 109 (the default value) say Y. 110 111config NUMA 112 bool "Non Uniform Memory Access (NUMA) Support" 113 depends on MMU && SYS_SUPPORTS_NUMA 114 select ARCH_WANT_NUMA_VARIABLE_LOCALITY 115 default n 116 help 117 Some SH systems have many various memories scattered around 118 the address space, each with varying latencies. This enables 119 support for these blocks by binding them to nodes and allowing 120 memory policies to be used for prioritizing and controlling 121 allocation behaviour. 122 123config NODES_SHIFT 124 int 125 default "3" if CPU_SUBTYPE_SHX3 126 default "1" 127 depends on NEED_MULTIPLE_NODES 128 129config ARCH_FLATMEM_ENABLE 130 def_bool y 131 depends on !NUMA 132 133config ARCH_SPARSEMEM_ENABLE 134 def_bool y 135 select SPARSEMEM_STATIC 136 137config ARCH_SPARSEMEM_DEFAULT 138 def_bool y 139 140config ARCH_SELECT_MEMORY_MODEL 141 def_bool y 142 143config ARCH_ENABLE_MEMORY_HOTPLUG 144 def_bool y 145 depends on SPARSEMEM && MMU 146 147config ARCH_ENABLE_MEMORY_HOTREMOVE 148 def_bool y 149 depends on SPARSEMEM && MMU 150 151config ARCH_MEMORY_PROBE 152 def_bool y 153 depends on MEMORY_HOTPLUG 154 155config IOREMAP_FIXED 156 def_bool y 157 depends on X2TLB || SUPERH64 158 159config UNCACHED_MAPPING 160 bool 161 162config HAVE_SRAM_POOL 163 bool 164 select GENERIC_ALLOCATOR 165 166choice 167 prompt "Kernel page size" 168 default PAGE_SIZE_4KB 169 170config PAGE_SIZE_4KB 171 bool "4kB" 172 help 173 This is the default page size used by all SuperH CPUs. 174 175config PAGE_SIZE_8KB 176 bool "8kB" 177 depends on !MMU || X2TLB 178 help 179 This enables 8kB pages as supported by SH-X2 and later MMUs. 180 181config PAGE_SIZE_16KB 182 bool "16kB" 183 depends on !MMU 184 help 185 This enables 16kB pages on MMU-less SH systems. 186 187config PAGE_SIZE_64KB 188 bool "64kB" 189 depends on !MMU || CPU_SH4 || CPU_SH5 190 help 191 This enables support for 64kB pages, possible on all SH-4 192 CPUs and later. 193 194endchoice 195 196choice 197 prompt "HugeTLB page size" 198 depends on HUGETLB_PAGE 199 default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB 200 default HUGETLB_PAGE_SIZE_64K 201 202config HUGETLB_PAGE_SIZE_64K 203 bool "64kB" 204 depends on !PAGE_SIZE_64KB 205 206config HUGETLB_PAGE_SIZE_256K 207 bool "256kB" 208 depends on X2TLB 209 210config HUGETLB_PAGE_SIZE_1MB 211 bool "1MB" 212 213config HUGETLB_PAGE_SIZE_4MB 214 bool "4MB" 215 depends on X2TLB 216 217config HUGETLB_PAGE_SIZE_64MB 218 bool "64MB" 219 depends on X2TLB 220 221config HUGETLB_PAGE_SIZE_512MB 222 bool "512MB" 223 depends on CPU_SH5 224 225endchoice 226 227source "mm/Kconfig" 228 229config SCHED_MC 230 bool "Multi-core scheduler support" 231 depends on SMP 232 default y 233 help 234 Multi-core scheduler support improves the CPU scheduler's decision 235 making when dealing with multi-core CPU chips at a cost of slightly 236 increased overhead in some places. If unsure say N here. 237 238endmenu 239 240menu "Cache configuration" 241 242config SH7705_CACHE_32KB 243 bool "Enable 32KB cache size for SH7705" 244 depends on CPU_SUBTYPE_SH7705 245 default y 246 247choice 248 prompt "Cache mode" 249 default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5 250 default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A) 251 252config CACHE_WRITEBACK 253 bool "Write-back" 254 255config CACHE_WRITETHROUGH 256 bool "Write-through" 257 help 258 Selecting this option will configure the caches in write-through 259 mode, as opposed to the default write-back configuration. 260 261 Since there's sill some aliasing issues on SH-4, this option will 262 unfortunately still require the majority of flushing functions to 263 be implemented to deal with aliasing. 264 265 If unsure, say N. 266 267config CACHE_OFF 268 bool "Off" 269 270endchoice 271 272endmenu 273