xref: /openbmc/linux/arch/sh/mm/Kconfig (revision 02891844) 
1# SPDX-License-Identifier: GPL-2.0
2menu "Memory management options"
3
4config MMU
5        bool "Support for memory management hardware"
6	depends on !CPU_SH2
7	default y
8	help
9	  Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
10	  boot on these systems, this option must not be set.
11
12	  On other systems (such as the SH-3 and 4) where an MMU exists,
13	  turning this off will boot the kernel on these machines with the
14	  MMU implicitly switched off.
15
16config PAGE_OFFSET
17	hex
18	default "0x80000000" if MMU
19	default "0x00000000"
20
21config ARCH_FORCE_MAX_ORDER
22	int "Maximum zone order"
23	range 8 63 if PAGE_SIZE_16KB
24	default "8" if PAGE_SIZE_16KB
25	range 6 63 if PAGE_SIZE_64KB
26	default "6" if PAGE_SIZE_64KB
27	range 10 63
28	default "13" if !MMU
29	default "10"
30	help
31	  The kernel memory allocator divides physically contiguous memory
32	  blocks into "zones", where each zone is a power of two number of
33	  pages.  This option selects the largest power of two that the kernel
34	  keeps in the memory allocator.  If you need to allocate very large
35	  blocks of physically contiguous memory, then you may need to
36	  increase this value.
37
38	  The page size is not necessarily 4KB. Keep this in mind when
39	  choosing a value for this option.
40
41config MEMORY_START
42	hex "Physical memory start address"
43	default "0x08000000"
44	help
45	  Computers built with Hitachi SuperH processors always
46	  map the ROM starting at address zero.  But the processor
47	  does not specify the range that RAM takes.
48
49	  The physical memory (RAM) start address will be automatically
50	  set to 08000000. Other platforms, such as the Solution Engine
51	  boards typically map RAM at 0C000000.
52
53	  Tweak this only when porting to a new machine which does not
54	  already have a defconfig. Changing it from the known correct
55	  value on any of the known systems will only lead to disaster.
56
57config MEMORY_SIZE
58	hex "Physical memory size"
59	default "0x04000000"
60	help
61	  This sets the default memory size assumed by your SH kernel. It can
62	  be overridden as normal by the 'mem=' argument on the kernel command
63	  line. If unsure, consult your board specifications or just leave it
64	  as 0x04000000 which was the default value before this became
65	  configurable.
66
67# Physical addressing modes
68
69config 29BIT
70	def_bool !32BIT
71	select UNCACHED_MAPPING
72
73config 32BIT
74	bool
75	default !MMU
76
77config PMB
78	bool "Support 32-bit physical addressing through PMB"
79	depends on MMU && CPU_SH4A && !CPU_SH4AL_DSP
80	select 32BIT
81	select UNCACHED_MAPPING
82	help
83	  If you say Y here, physical addressing will be extended to
84	  32-bits through the SH-4A PMB. If this is not set, legacy
85	  29-bit physical addressing will be used.
86
87config X2TLB
88	def_bool y
89	depends on (CPU_SHX2 || CPU_SHX3) && MMU
90
91config VSYSCALL
92	bool "Support vsyscall page"
93	depends on MMU && (CPU_SH3 || CPU_SH4)
94	default y
95	help
96	  This will enable support for the kernel mapping a vDSO page
97	  in process space, and subsequently handing down the entry point
98	  to the libc through the ELF auxiliary vector.
99
100	  From the kernel side this is used for the signal trampoline.
101	  For systems with an MMU that can afford to give up a page,
102	  (the default value) say Y.
103
104config NUMA
105	bool "Non-Uniform Memory Access (NUMA) Support"
106	depends on MMU && SYS_SUPPORTS_NUMA
107	select ARCH_WANT_NUMA_VARIABLE_LOCALITY
108	default n
109	help
110	  Some SH systems have many various memories scattered around
111	  the address space, each with varying latencies. This enables
112	  support for these blocks by binding them to nodes and allowing
113	  memory policies to be used for prioritizing and controlling
114	  allocation behaviour.
115
116config NODES_SHIFT
117	int
118	default "3" if CPU_SUBTYPE_SHX3
119	default "1"
120	depends on NUMA
121
122config ARCH_FLATMEM_ENABLE
123	def_bool y
124	depends on !NUMA
125
126config ARCH_SPARSEMEM_ENABLE
127	def_bool y
128	select SPARSEMEM_STATIC
129
130config ARCH_SPARSEMEM_DEFAULT
131	def_bool y
132
133config ARCH_SELECT_MEMORY_MODEL
134	def_bool y
135
136config ARCH_MEMORY_PROBE
137	def_bool y
138	depends on MEMORY_HOTPLUG
139
140config IOREMAP_FIXED
141       def_bool y
142       depends on X2TLB
143
144config UNCACHED_MAPPING
145	bool
146
147config HAVE_SRAM_POOL
148	bool
149	select GENERIC_ALLOCATOR
150
151choice
152	prompt "Kernel page size"
153	default PAGE_SIZE_4KB
154
155config PAGE_SIZE_4KB
156	bool "4kB"
157	help
158	  This is the default page size used by all SuperH CPUs.
159
160config PAGE_SIZE_8KB
161	bool "8kB"
162	depends on !MMU || X2TLB
163	help
164	  This enables 8kB pages as supported by SH-X2 and later MMUs.
165
166config PAGE_SIZE_16KB
167	bool "16kB"
168	depends on !MMU
169	help
170	  This enables 16kB pages on MMU-less SH systems.
171
172config PAGE_SIZE_64KB
173	bool "64kB"
174	depends on !MMU || CPU_SH4
175	help
176	  This enables support for 64kB pages, possible on all SH-4
177	  CPUs and later.
178
179endchoice
180
181choice
182	prompt "HugeTLB page size"
183	depends on HUGETLB_PAGE
184	default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB
185	default HUGETLB_PAGE_SIZE_64K
186
187config HUGETLB_PAGE_SIZE_64K
188	bool "64kB"
189	depends on !PAGE_SIZE_64KB
190
191config HUGETLB_PAGE_SIZE_256K
192	bool "256kB"
193	depends on X2TLB
194
195config HUGETLB_PAGE_SIZE_1MB
196	bool "1MB"
197
198config HUGETLB_PAGE_SIZE_4MB
199	bool "4MB"
200	depends on X2TLB
201
202config HUGETLB_PAGE_SIZE_64MB
203	bool "64MB"
204	depends on X2TLB
205
206endchoice
207
208config SCHED_MC
209	bool "Multi-core scheduler support"
210	depends on SMP
211	default y
212	help
213	  Multi-core scheduler support improves the CPU scheduler's decision
214	  making when dealing with multi-core CPU chips at a cost of slightly
215	  increased overhead in some places. If unsure say N here.
216
217endmenu
218
219menu "Cache configuration"
220
221config SH7705_CACHE_32KB
222	bool "Enable 32KB cache size for SH7705"
223	depends on CPU_SUBTYPE_SH7705
224	default y
225
226choice
227	prompt "Cache mode"
228	default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4
229	default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
230
231config CACHE_WRITEBACK
232	bool "Write-back"
233
234config CACHE_WRITETHROUGH
235	bool "Write-through"
236	help
237	  Selecting this option will configure the caches in write-through
238	  mode, as opposed to the default write-back configuration.
239
240	  Since there's sill some aliasing issues on SH-4, this option will
241	  unfortunately still require the majority of flushing functions to
242	  be implemented to deal with aliasing.
243
244	  If unsure, say N.
245
246config CACHE_OFF
247	bool "Off"
248
249endchoice
250
251endmenu
252