1 /* 2 * 'traps.c' handles hardware traps and faults after we have saved some 3 * state in 'entry.S'. 4 * 5 * SuperH version: Copyright (C) 1999 Niibe Yutaka 6 * Copyright (C) 2000 Philipp Rumpf 7 * Copyright (C) 2000 David Howells 8 * Copyright (C) 2002 - 2007 Paul Mundt 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file "COPYING" in the main directory of this archive 12 * for more details. 13 */ 14 #include <linux/kernel.h> 15 #include <linux/ptrace.h> 16 #include <linux/hardirq.h> 17 #include <linux/init.h> 18 #include <linux/spinlock.h> 19 #include <linux/module.h> 20 #include <linux/kallsyms.h> 21 #include <linux/io.h> 22 #include <linux/bug.h> 23 #include <linux/debug_locks.h> 24 #include <linux/kdebug.h> 25 #include <linux/kexec.h> 26 #include <linux/limits.h> 27 #include <linux/proc_fs.h> 28 #include <asm/system.h> 29 #include <asm/uaccess.h> 30 #include <asm/fpu.h> 31 #include <asm/kprobes.h> 32 33 #ifdef CONFIG_CPU_SH2 34 # define TRAP_RESERVED_INST 4 35 # define TRAP_ILLEGAL_SLOT_INST 6 36 # define TRAP_ADDRESS_ERROR 9 37 # ifdef CONFIG_CPU_SH2A 38 # define TRAP_UBC 12 39 # define TRAP_FPU_ERROR 13 40 # define TRAP_DIVZERO_ERROR 17 41 # define TRAP_DIVOVF_ERROR 18 42 # endif 43 #else 44 #define TRAP_RESERVED_INST 12 45 #define TRAP_ILLEGAL_SLOT_INST 13 46 #endif 47 48 static unsigned long se_user; 49 static unsigned long se_sys; 50 static unsigned long se_half; 51 static unsigned long se_word; 52 static unsigned long se_dword; 53 static unsigned long se_multi; 54 /* bitfield: 1: warn 2: fixup 4: signal -> combinations 2|4 && 1|2|4 are not 55 valid! */ 56 static int se_usermode = 3; 57 /* 0: no warning 1: print a warning message */ 58 static int se_kernmode_warn = 1; 59 60 #ifdef CONFIG_PROC_FS 61 static const char *se_usermode_action[] = { 62 "ignored", 63 "warn", 64 "fixup", 65 "fixup+warn", 66 "signal", 67 "signal+warn" 68 }; 69 70 static int 71 proc_alignment_read(char *page, char **start, off_t off, int count, int *eof, 72 void *data) 73 { 74 char *p = page; 75 int len; 76 77 p += sprintf(p, "User:\t\t%lu\n", se_user); 78 p += sprintf(p, "System:\t\t%lu\n", se_sys); 79 p += sprintf(p, "Half:\t\t%lu\n", se_half); 80 p += sprintf(p, "Word:\t\t%lu\n", se_word); 81 p += sprintf(p, "DWord:\t\t%lu\n", se_dword); 82 p += sprintf(p, "Multi:\t\t%lu\n", se_multi); 83 p += sprintf(p, "User faults:\t%i (%s)\n", se_usermode, 84 se_usermode_action[se_usermode]); 85 p += sprintf(p, "Kernel faults:\t%i (fixup%s)\n", se_kernmode_warn, 86 se_kernmode_warn ? "+warn" : ""); 87 88 len = (p - page) - off; 89 if (len < 0) 90 len = 0; 91 92 *eof = (len <= count) ? 1 : 0; 93 *start = page + off; 94 95 return len; 96 } 97 98 static int proc_alignment_write(struct file *file, const char __user *buffer, 99 unsigned long count, void *data) 100 { 101 char mode; 102 103 if (count > 0) { 104 if (get_user(mode, buffer)) 105 return -EFAULT; 106 if (mode >= '0' && mode <= '5') 107 se_usermode = mode - '0'; 108 } 109 return count; 110 } 111 112 static int proc_alignment_kern_write(struct file *file, const char __user *buffer, 113 unsigned long count, void *data) 114 { 115 char mode; 116 117 if (count > 0) { 118 if (get_user(mode, buffer)) 119 return -EFAULT; 120 if (mode >= '0' && mode <= '1') 121 se_kernmode_warn = mode - '0'; 122 } 123 return count; 124 } 125 #endif 126 127 static void dump_mem(const char *str, unsigned long bottom, unsigned long top) 128 { 129 unsigned long p; 130 int i; 131 132 printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top); 133 134 for (p = bottom & ~31; p < top; ) { 135 printk("%04lx: ", p & 0xffff); 136 137 for (i = 0; i < 8; i++, p += 4) { 138 unsigned int val; 139 140 if (p < bottom || p >= top) 141 printk(" "); 142 else { 143 if (__get_user(val, (unsigned int __user *)p)) { 144 printk("\n"); 145 return; 146 } 147 printk("%08x ", val); 148 } 149 } 150 printk("\n"); 151 } 152 } 153 154 static DEFINE_SPINLOCK(die_lock); 155 156 void die(const char * str, struct pt_regs * regs, long err) 157 { 158 static int die_counter; 159 160 oops_enter(); 161 162 console_verbose(); 163 spin_lock_irq(&die_lock); 164 bust_spinlocks(1); 165 166 printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter); 167 168 print_modules(); 169 show_regs(regs); 170 171 printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm, 172 task_pid_nr(current), task_stack_page(current) + 1); 173 174 if (!user_mode(regs) || in_interrupt()) 175 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE + 176 (unsigned long)task_stack_page(current)); 177 178 notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV); 179 180 bust_spinlocks(0); 181 add_taint(TAINT_DIE); 182 spin_unlock_irq(&die_lock); 183 184 if (kexec_should_crash(current)) 185 crash_kexec(regs); 186 187 if (in_interrupt()) 188 panic("Fatal exception in interrupt"); 189 190 if (panic_on_oops) 191 panic("Fatal exception"); 192 193 oops_exit(); 194 do_exit(SIGSEGV); 195 } 196 197 static inline void die_if_kernel(const char *str, struct pt_regs *regs, 198 long err) 199 { 200 if (!user_mode(regs)) 201 die(str, regs, err); 202 } 203 204 /* 205 * try and fix up kernelspace address errors 206 * - userspace errors just cause EFAULT to be returned, resulting in SEGV 207 * - kernel/userspace interfaces cause a jump to an appropriate handler 208 * - other kernel errors are bad 209 */ 210 static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err) 211 { 212 if (!user_mode(regs)) { 213 const struct exception_table_entry *fixup; 214 fixup = search_exception_tables(regs->pc); 215 if (fixup) { 216 regs->pc = fixup->fixup; 217 return; 218 } 219 220 die(str, regs, err); 221 } 222 } 223 224 static inline void sign_extend(unsigned int count, unsigned char *dst) 225 { 226 #ifdef __LITTLE_ENDIAN__ 227 if ((count == 1) && dst[0] & 0x80) { 228 dst[1] = 0xff; 229 dst[2] = 0xff; 230 dst[3] = 0xff; 231 } 232 if ((count == 2) && dst[1] & 0x80) { 233 dst[2] = 0xff; 234 dst[3] = 0xff; 235 } 236 #else 237 if ((count == 1) && dst[3] & 0x80) { 238 dst[2] = 0xff; 239 dst[1] = 0xff; 240 dst[0] = 0xff; 241 } 242 if ((count == 2) && dst[2] & 0x80) { 243 dst[1] = 0xff; 244 dst[0] = 0xff; 245 } 246 #endif 247 } 248 249 static struct mem_access user_mem_access = { 250 copy_from_user, 251 copy_to_user, 252 }; 253 254 /* 255 * handle an instruction that does an unaligned memory access by emulating the 256 * desired behaviour 257 * - note that PC _may not_ point to the faulting instruction 258 * (if that instruction is in a branch delay slot) 259 * - return 0 if emulation okay, -EFAULT on existential error 260 */ 261 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs, 262 struct mem_access *ma) 263 { 264 int ret, index, count; 265 unsigned long *rm, *rn; 266 unsigned char *src, *dst; 267 unsigned char __user *srcu, *dstu; 268 269 index = (instruction>>8)&15; /* 0x0F00 */ 270 rn = ®s->regs[index]; 271 272 index = (instruction>>4)&15; /* 0x00F0 */ 273 rm = ®s->regs[index]; 274 275 count = 1<<(instruction&3); 276 277 switch (count) { 278 case 1: se_half += 1; break; 279 case 2: se_word += 1; break; 280 case 4: se_dword += 1; break; 281 case 8: se_multi += 1; break; /* ??? */ 282 } 283 284 ret = -EFAULT; 285 switch (instruction>>12) { 286 case 0: /* mov.[bwl] to/from memory via r0+rn */ 287 if (instruction & 8) { 288 /* from memory */ 289 srcu = (unsigned char __user *)*rm; 290 srcu += regs->regs[0]; 291 dst = (unsigned char *)rn; 292 *(unsigned long *)dst = 0; 293 294 #if !defined(__LITTLE_ENDIAN__) 295 dst += 4-count; 296 #endif 297 if (ma->from(dst, srcu, count)) 298 goto fetch_fault; 299 300 sign_extend(count, dst); 301 } else { 302 /* to memory */ 303 src = (unsigned char *)rm; 304 #if !defined(__LITTLE_ENDIAN__) 305 src += 4-count; 306 #endif 307 dstu = (unsigned char __user *)*rn; 308 dstu += regs->regs[0]; 309 310 if (ma->to(dstu, src, count)) 311 goto fetch_fault; 312 } 313 ret = 0; 314 break; 315 316 case 1: /* mov.l Rm,@(disp,Rn) */ 317 src = (unsigned char*) rm; 318 dstu = (unsigned char __user *)*rn; 319 dstu += (instruction&0x000F)<<2; 320 321 if (ma->to(dstu, src, 4)) 322 goto fetch_fault; 323 ret = 0; 324 break; 325 326 case 2: /* mov.[bwl] to memory, possibly with pre-decrement */ 327 if (instruction & 4) 328 *rn -= count; 329 src = (unsigned char*) rm; 330 dstu = (unsigned char __user *)*rn; 331 #if !defined(__LITTLE_ENDIAN__) 332 src += 4-count; 333 #endif 334 if (ma->to(dstu, src, count)) 335 goto fetch_fault; 336 ret = 0; 337 break; 338 339 case 5: /* mov.l @(disp,Rm),Rn */ 340 srcu = (unsigned char __user *)*rm; 341 srcu += (instruction & 0x000F) << 2; 342 dst = (unsigned char *)rn; 343 *(unsigned long *)dst = 0; 344 345 if (ma->from(dst, srcu, 4)) 346 goto fetch_fault; 347 ret = 0; 348 break; 349 350 case 6: /* mov.[bwl] from memory, possibly with post-increment */ 351 srcu = (unsigned char __user *)*rm; 352 if (instruction & 4) 353 *rm += count; 354 dst = (unsigned char*) rn; 355 *(unsigned long*)dst = 0; 356 357 #if !defined(__LITTLE_ENDIAN__) 358 dst += 4-count; 359 #endif 360 if (ma->from(dst, srcu, count)) 361 goto fetch_fault; 362 sign_extend(count, dst); 363 ret = 0; 364 break; 365 366 case 8: 367 switch ((instruction&0xFF00)>>8) { 368 case 0x81: /* mov.w R0,@(disp,Rn) */ 369 src = (unsigned char *) ®s->regs[0]; 370 #if !defined(__LITTLE_ENDIAN__) 371 src += 2; 372 #endif 373 dstu = (unsigned char __user *)*rm; /* called Rn in the spec */ 374 dstu += (instruction & 0x000F) << 1; 375 376 if (ma->to(dstu, src, 2)) 377 goto fetch_fault; 378 ret = 0; 379 break; 380 381 case 0x85: /* mov.w @(disp,Rm),R0 */ 382 srcu = (unsigned char __user *)*rm; 383 srcu += (instruction & 0x000F) << 1; 384 dst = (unsigned char *) ®s->regs[0]; 385 *(unsigned long *)dst = 0; 386 387 #if !defined(__LITTLE_ENDIAN__) 388 dst += 2; 389 #endif 390 if (ma->from(dst, srcu, 2)) 391 goto fetch_fault; 392 sign_extend(2, dst); 393 ret = 0; 394 break; 395 } 396 break; 397 } 398 return ret; 399 400 fetch_fault: 401 /* Argh. Address not only misaligned but also non-existent. 402 * Raise an EFAULT and see if it's trapped 403 */ 404 die_if_no_fixup("Fault in unaligned fixup", regs, 0); 405 return -EFAULT; 406 } 407 408 /* 409 * emulate the instruction in the delay slot 410 * - fetches the instruction from PC+2 411 */ 412 static inline int handle_delayslot(struct pt_regs *regs, 413 insn_size_t old_instruction, 414 struct mem_access *ma) 415 { 416 insn_size_t instruction; 417 void __user *addr = (void __user *)(regs->pc + 418 instruction_size(old_instruction)); 419 420 if (copy_from_user(&instruction, addr, sizeof(instruction))) { 421 /* the instruction-fetch faulted */ 422 if (user_mode(regs)) 423 return -EFAULT; 424 425 /* kernel */ 426 die("delay-slot-insn faulting in handle_unaligned_delayslot", 427 regs, 0); 428 } 429 430 return handle_unaligned_ins(instruction, regs, ma); 431 } 432 433 /* 434 * handle an instruction that does an unaligned memory access 435 * - have to be careful of branch delay-slot instructions that fault 436 * SH3: 437 * - if the branch would be taken PC points to the branch 438 * - if the branch would not be taken, PC points to delay-slot 439 * SH4: 440 * - PC always points to delayed branch 441 * - return 0 if handled, -EFAULT if failed (may not return if in kernel) 442 */ 443 444 /* Macros to determine offset from current PC for branch instructions */ 445 /* Explicit type coercion is used to force sign extension where needed */ 446 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4) 447 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4) 448 449 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, 450 struct mem_access *ma, int expected) 451 { 452 u_int rm; 453 int ret, index; 454 455 /* 456 * XXX: We can't handle mixed 16/32-bit instructions yet 457 */ 458 if (instruction_size(instruction) != 2) 459 return -EINVAL; 460 461 index = (instruction>>8)&15; /* 0x0F00 */ 462 rm = regs->regs[index]; 463 464 /* shout about fixups */ 465 if (!expected && printk_ratelimit()) 466 printk(KERN_NOTICE "Fixing up unaligned %s access " 467 "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n", 468 user_mode(regs) ? "userspace" : "kernel", 469 current->comm, task_pid_nr(current), 470 (void *)regs->pc, instruction); 471 472 ret = -EFAULT; 473 switch (instruction&0xF000) { 474 case 0x0000: 475 if (instruction==0x000B) { 476 /* rts */ 477 ret = handle_delayslot(regs, instruction, ma); 478 if (ret==0) 479 regs->pc = regs->pr; 480 } 481 else if ((instruction&0x00FF)==0x0023) { 482 /* braf @Rm */ 483 ret = handle_delayslot(regs, instruction, ma); 484 if (ret==0) 485 regs->pc += rm + 4; 486 } 487 else if ((instruction&0x00FF)==0x0003) { 488 /* bsrf @Rm */ 489 ret = handle_delayslot(regs, instruction, ma); 490 if (ret==0) { 491 regs->pr = regs->pc + 4; 492 regs->pc += rm + 4; 493 } 494 } 495 else { 496 /* mov.[bwl] to/from memory via r0+rn */ 497 goto simple; 498 } 499 break; 500 501 case 0x1000: /* mov.l Rm,@(disp,Rn) */ 502 goto simple; 503 504 case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */ 505 goto simple; 506 507 case 0x4000: 508 if ((instruction&0x00FF)==0x002B) { 509 /* jmp @Rm */ 510 ret = handle_delayslot(regs, instruction, ma); 511 if (ret==0) 512 regs->pc = rm; 513 } 514 else if ((instruction&0x00FF)==0x000B) { 515 /* jsr @Rm */ 516 ret = handle_delayslot(regs, instruction, ma); 517 if (ret==0) { 518 regs->pr = regs->pc + 4; 519 regs->pc = rm; 520 } 521 } 522 else { 523 /* mov.[bwl] to/from memory via r0+rn */ 524 goto simple; 525 } 526 break; 527 528 case 0x5000: /* mov.l @(disp,Rm),Rn */ 529 goto simple; 530 531 case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */ 532 goto simple; 533 534 case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */ 535 switch (instruction&0x0F00) { 536 case 0x0100: /* mov.w R0,@(disp,Rm) */ 537 goto simple; 538 case 0x0500: /* mov.w @(disp,Rm),R0 */ 539 goto simple; 540 case 0x0B00: /* bf lab - no delayslot*/ 541 break; 542 case 0x0F00: /* bf/s lab */ 543 ret = handle_delayslot(regs, instruction, ma); 544 if (ret==0) { 545 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) 546 if ((regs->sr & 0x00000001) != 0) 547 regs->pc += 4; /* next after slot */ 548 else 549 #endif 550 regs->pc += SH_PC_8BIT_OFFSET(instruction); 551 } 552 break; 553 case 0x0900: /* bt lab - no delayslot */ 554 break; 555 case 0x0D00: /* bt/s lab */ 556 ret = handle_delayslot(regs, instruction, ma); 557 if (ret==0) { 558 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) 559 if ((regs->sr & 0x00000001) == 0) 560 regs->pc += 4; /* next after slot */ 561 else 562 #endif 563 regs->pc += SH_PC_8BIT_OFFSET(instruction); 564 } 565 break; 566 } 567 break; 568 569 case 0xA000: /* bra label */ 570 ret = handle_delayslot(regs, instruction, ma); 571 if (ret==0) 572 regs->pc += SH_PC_12BIT_OFFSET(instruction); 573 break; 574 575 case 0xB000: /* bsr label */ 576 ret = handle_delayslot(regs, instruction, ma); 577 if (ret==0) { 578 regs->pr = regs->pc + 4; 579 regs->pc += SH_PC_12BIT_OFFSET(instruction); 580 } 581 break; 582 } 583 return ret; 584 585 /* handle non-delay-slot instruction */ 586 simple: 587 ret = handle_unaligned_ins(instruction, regs, ma); 588 if (ret==0) 589 regs->pc += instruction_size(instruction); 590 return ret; 591 } 592 593 /* 594 * Handle various address error exceptions: 595 * - instruction address error: 596 * misaligned PC 597 * PC >= 0x80000000 in user mode 598 * - data address error (read and write) 599 * misaligned data access 600 * access to >= 0x80000000 is user mode 601 * Unfortuntaly we can't distinguish between instruction address error 602 * and data address errors caused by read accesses. 603 */ 604 asmlinkage void do_address_error(struct pt_regs *regs, 605 unsigned long writeaccess, 606 unsigned long address) 607 { 608 unsigned long error_code = 0; 609 mm_segment_t oldfs; 610 siginfo_t info; 611 insn_size_t instruction; 612 int tmp; 613 614 /* Intentional ifdef */ 615 #ifdef CONFIG_CPU_HAS_SR_RB 616 error_code = lookup_exception_vector(); 617 #endif 618 619 oldfs = get_fs(); 620 621 if (user_mode(regs)) { 622 int si_code = BUS_ADRERR; 623 624 local_irq_enable(); 625 626 se_user += 1; 627 628 set_fs(USER_DS); 629 if (copy_from_user(&instruction, (insn_size_t *)(regs->pc & ~1), 630 sizeof(instruction))) { 631 set_fs(oldfs); 632 goto uspace_segv; 633 } 634 set_fs(oldfs); 635 636 /* shout about userspace fixups */ 637 if (se_usermode & 1) 638 printk(KERN_NOTICE "Unaligned userspace access " 639 "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n", 640 current->comm, current->pid, (void *)regs->pc, 641 instruction); 642 643 if (se_usermode & 2) 644 goto fixup; 645 646 if (se_usermode & 4) 647 goto uspace_segv; 648 else { 649 /* ignore */ 650 regs->pc += instruction_size(instruction); 651 return; 652 } 653 654 fixup: 655 /* bad PC is not something we can fix */ 656 if (regs->pc & 1) { 657 si_code = BUS_ADRALN; 658 goto uspace_segv; 659 } 660 661 set_fs(USER_DS); 662 tmp = handle_unaligned_access(instruction, regs, 663 &user_mem_access, 0); 664 set_fs(oldfs); 665 666 if (tmp==0) 667 return; /* sorted */ 668 uspace_segv: 669 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned " 670 "access (PC %lx PR %lx)\n", current->comm, regs->pc, 671 regs->pr); 672 673 info.si_signo = SIGBUS; 674 info.si_errno = 0; 675 info.si_code = si_code; 676 info.si_addr = (void __user *)address; 677 force_sig_info(SIGBUS, &info, current); 678 } else { 679 se_sys += 1; 680 681 if (regs->pc & 1) 682 die("unaligned program counter", regs, error_code); 683 684 set_fs(KERNEL_DS); 685 if (copy_from_user(&instruction, (void __user *)(regs->pc), 686 sizeof(instruction))) { 687 /* Argh. Fault on the instruction itself. 688 This should never happen non-SMP 689 */ 690 set_fs(oldfs); 691 die("insn faulting in do_address_error", regs, 0); 692 } 693 694 if (se_kernmode_warn) 695 printk(KERN_NOTICE "Unaligned kernel access " 696 "on behalf of \"%s\" pid=%d pc=0x%p ins=0x%04hx\n", 697 current->comm, current->pid, (void *)regs->pc, 698 instruction); 699 700 handle_unaligned_access(instruction, regs, 701 &user_mem_access, 0); 702 set_fs(oldfs); 703 } 704 } 705 706 #ifdef CONFIG_SH_DSP 707 /* 708 * SH-DSP support gerg@snapgear.com. 709 */ 710 int is_dsp_inst(struct pt_regs *regs) 711 { 712 unsigned short inst = 0; 713 714 /* 715 * Safe guard if DSP mode is already enabled or we're lacking 716 * the DSP altogether. 717 */ 718 if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP)) 719 return 0; 720 721 get_user(inst, ((unsigned short *) regs->pc)); 722 723 inst &= 0xf000; 724 725 /* Check for any type of DSP or support instruction */ 726 if ((inst == 0xf000) || (inst == 0x4000)) 727 return 1; 728 729 return 0; 730 } 731 #else 732 #define is_dsp_inst(regs) (0) 733 #endif /* CONFIG_SH_DSP */ 734 735 #ifdef CONFIG_CPU_SH2A 736 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5, 737 unsigned long r6, unsigned long r7, 738 struct pt_regs __regs) 739 { 740 siginfo_t info; 741 742 switch (r4) { 743 case TRAP_DIVZERO_ERROR: 744 info.si_code = FPE_INTDIV; 745 break; 746 case TRAP_DIVOVF_ERROR: 747 info.si_code = FPE_INTOVF; 748 break; 749 } 750 751 force_sig_info(SIGFPE, &info, current); 752 } 753 #endif 754 755 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5, 756 unsigned long r6, unsigned long r7, 757 struct pt_regs __regs) 758 { 759 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); 760 unsigned long error_code; 761 struct task_struct *tsk = current; 762 763 #ifdef CONFIG_SH_FPU_EMU 764 unsigned short inst = 0; 765 int err; 766 767 get_user(inst, (unsigned short*)regs->pc); 768 769 err = do_fpu_inst(inst, regs); 770 if (!err) { 771 regs->pc += instruction_size(inst); 772 return; 773 } 774 /* not a FPU inst. */ 775 #endif 776 777 #ifdef CONFIG_SH_DSP 778 /* Check if it's a DSP instruction */ 779 if (is_dsp_inst(regs)) { 780 /* Enable DSP mode, and restart instruction. */ 781 regs->sr |= SR_DSP; 782 /* Save DSP mode */ 783 tsk->thread.dsp_status.status |= SR_DSP; 784 return; 785 } 786 #endif 787 788 error_code = lookup_exception_vector(); 789 790 local_irq_enable(); 791 force_sig(SIGILL, tsk); 792 die_if_no_fixup("reserved instruction", regs, error_code); 793 } 794 795 #ifdef CONFIG_SH_FPU_EMU 796 static int emulate_branch(unsigned short inst, struct pt_regs *regs) 797 { 798 /* 799 * bfs: 8fxx: PC+=d*2+4; 800 * bts: 8dxx: PC+=d*2+4; 801 * bra: axxx: PC+=D*2+4; 802 * bsr: bxxx: PC+=D*2+4 after PR=PC+4; 803 * braf:0x23: PC+=Rn*2+4; 804 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4; 805 * jmp: 4x2b: PC=Rn; 806 * jsr: 4x0b: PC=Rn after PR=PC+4; 807 * rts: 000b: PC=PR; 808 */ 809 if (((inst & 0xf000) == 0xb000) || /* bsr */ 810 ((inst & 0xf0ff) == 0x0003) || /* bsrf */ 811 ((inst & 0xf0ff) == 0x400b)) /* jsr */ 812 regs->pr = regs->pc + 4; 813 814 if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */ 815 regs->pc += SH_PC_8BIT_OFFSET(inst); 816 return 0; 817 } 818 819 if ((inst & 0xe000) == 0xa000) { /* bra, bsr */ 820 regs->pc += SH_PC_12BIT_OFFSET(inst); 821 return 0; 822 } 823 824 if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */ 825 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4; 826 return 0; 827 } 828 829 if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */ 830 regs->pc = regs->regs[(inst & 0x0f00) >> 8]; 831 return 0; 832 } 833 834 if ((inst & 0xffff) == 0x000b) { /* rts */ 835 regs->pc = regs->pr; 836 return 0; 837 } 838 839 return 1; 840 } 841 #endif 842 843 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5, 844 unsigned long r6, unsigned long r7, 845 struct pt_regs __regs) 846 { 847 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); 848 unsigned long inst; 849 struct task_struct *tsk = current; 850 851 if (kprobe_handle_illslot(regs->pc) == 0) 852 return; 853 854 #ifdef CONFIG_SH_FPU_EMU 855 get_user(inst, (unsigned short *)regs->pc + 1); 856 if (!do_fpu_inst(inst, regs)) { 857 get_user(inst, (unsigned short *)regs->pc); 858 if (!emulate_branch(inst, regs)) 859 return; 860 /* fault in branch.*/ 861 } 862 /* not a FPU inst. */ 863 #endif 864 865 inst = lookup_exception_vector(); 866 867 local_irq_enable(); 868 force_sig(SIGILL, tsk); 869 die_if_no_fixup("illegal slot instruction", regs, inst); 870 } 871 872 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5, 873 unsigned long r6, unsigned long r7, 874 struct pt_regs __regs) 875 { 876 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); 877 long ex; 878 879 ex = lookup_exception_vector(); 880 die_if_kernel("exception", regs, ex); 881 } 882 883 #if defined(CONFIG_SH_STANDARD_BIOS) 884 void *gdb_vbr_vector; 885 886 static inline void __init gdb_vbr_init(void) 887 { 888 register unsigned long vbr; 889 890 /* 891 * Read the old value of the VBR register to initialise 892 * the vector through which debug and BIOS traps are 893 * delegated by the Linux trap handler. 894 */ 895 asm volatile("stc vbr, %0" : "=r" (vbr)); 896 897 gdb_vbr_vector = (void *)(vbr + 0x100); 898 printk("Setting GDB trap vector to 0x%08lx\n", 899 (unsigned long)gdb_vbr_vector); 900 } 901 #endif 902 903 void __cpuinit per_cpu_trap_init(void) 904 { 905 extern void *vbr_base; 906 907 #ifdef CONFIG_SH_STANDARD_BIOS 908 if (raw_smp_processor_id() == 0) 909 gdb_vbr_init(); 910 #endif 911 912 /* NOTE: The VBR value should be at P1 913 (or P2, virtural "fixed" address space). 914 It's definitely should not in physical address. */ 915 916 asm volatile("ldc %0, vbr" 917 : /* no output */ 918 : "r" (&vbr_base) 919 : "memory"); 920 } 921 922 void *set_exception_table_vec(unsigned int vec, void *handler) 923 { 924 extern void *exception_handling_table[]; 925 void *old_handler; 926 927 old_handler = exception_handling_table[vec]; 928 exception_handling_table[vec] = handler; 929 return old_handler; 930 } 931 932 void __init trap_init(void) 933 { 934 set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst); 935 set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst); 936 937 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \ 938 defined(CONFIG_SH_FPU_EMU) 939 /* 940 * For SH-4 lacking an FPU, treat floating point instructions as 941 * reserved. They'll be handled in the math-emu case, or faulted on 942 * otherwise. 943 */ 944 set_exception_table_evt(0x800, do_reserved_inst); 945 set_exception_table_evt(0x820, do_illegal_slot_inst); 946 #elif defined(CONFIG_SH_FPU) 947 #ifdef CONFIG_CPU_SUBTYPE_SHX3 948 set_exception_table_evt(0xd80, fpu_state_restore_trap_handler); 949 set_exception_table_evt(0xda0, fpu_state_restore_trap_handler); 950 #else 951 set_exception_table_evt(0x800, fpu_state_restore_trap_handler); 952 set_exception_table_evt(0x820, fpu_state_restore_trap_handler); 953 #endif 954 #endif 955 956 #ifdef CONFIG_CPU_SH2 957 set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler); 958 #endif 959 #ifdef CONFIG_CPU_SH2A 960 set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error); 961 set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error); 962 #ifdef CONFIG_SH_FPU 963 set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler); 964 #endif 965 #endif 966 967 #ifdef TRAP_UBC 968 set_exception_table_vec(TRAP_UBC, break_point_trap); 969 #endif 970 971 /* Setup VBR for boot cpu */ 972 per_cpu_trap_init(); 973 } 974 975 void show_stack(struct task_struct *tsk, unsigned long *sp) 976 { 977 unsigned long stack; 978 979 if (!tsk) 980 tsk = current; 981 if (tsk == current) 982 sp = (unsigned long *)current_stack_pointer; 983 else 984 sp = (unsigned long *)tsk->thread.sp; 985 986 stack = (unsigned long)sp; 987 dump_mem("Stack: ", stack, THREAD_SIZE + 988 (unsigned long)task_stack_page(tsk)); 989 show_trace(tsk, sp, NULL); 990 } 991 992 void dump_stack(void) 993 { 994 show_stack(NULL, NULL); 995 } 996 EXPORT_SYMBOL(dump_stack); 997 998 #ifdef CONFIG_PROC_FS 999 /* 1000 * This needs to be done after sysctl_init, otherwise sys/ will be 1001 * overwritten. Actually, this shouldn't be in sys/ at all since 1002 * it isn't a sysctl, and it doesn't contain sysctl information. 1003 * We now locate it in /proc/cpu/alignment instead. 1004 */ 1005 static int __init alignment_init(void) 1006 { 1007 struct proc_dir_entry *dir, *res; 1008 1009 dir = proc_mkdir("cpu", NULL); 1010 if (!dir) 1011 return -ENOMEM; 1012 1013 res = create_proc_entry("alignment", S_IWUSR | S_IRUGO, dir); 1014 if (!res) 1015 return -ENOMEM; 1016 1017 res->read_proc = proc_alignment_read; 1018 res->write_proc = proc_alignment_write; 1019 1020 res = create_proc_entry("kernel_alignment", S_IWUSR | S_IRUGO, dir); 1021 if (!res) 1022 return -ENOMEM; 1023 1024 res->read_proc = proc_alignment_read; 1025 res->write_proc = proc_alignment_kern_write; 1026 1027 return 0; 1028 } 1029 1030 fs_initcall(alignment_init); 1031 #endif 1032