1 /* 2 * 'traps.c' handles hardware traps and faults after we have saved some 3 * state in 'entry.S'. 4 * 5 * SuperH version: Copyright (C) 1999 Niibe Yutaka 6 * Copyright (C) 2000 Philipp Rumpf 7 * Copyright (C) 2000 David Howells 8 * Copyright (C) 2002 - 2007 Paul Mundt 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file "COPYING" in the main directory of this archive 12 * for more details. 13 */ 14 #include <linux/kernel.h> 15 #include <linux/ptrace.h> 16 #include <linux/hardirq.h> 17 #include <linux/init.h> 18 #include <linux/spinlock.h> 19 #include <linux/module.h> 20 #include <linux/kallsyms.h> 21 #include <linux/io.h> 22 #include <linux/bug.h> 23 #include <linux/debug_locks.h> 24 #include <linux/kdebug.h> 25 #include <linux/kexec.h> 26 #include <linux/limits.h> 27 #include <linux/sysfs.h> 28 #include <linux/uaccess.h> 29 #include <asm/system.h> 30 #include <asm/alignment.h> 31 #include <asm/fpu.h> 32 #include <asm/kprobes.h> 33 34 #ifdef CONFIG_CPU_SH2 35 # define TRAP_RESERVED_INST 4 36 # define TRAP_ILLEGAL_SLOT_INST 6 37 # define TRAP_ADDRESS_ERROR 9 38 # ifdef CONFIG_CPU_SH2A 39 # define TRAP_UBC 12 40 # define TRAP_FPU_ERROR 13 41 # define TRAP_DIVZERO_ERROR 17 42 # define TRAP_DIVOVF_ERROR 18 43 # endif 44 #else 45 #define TRAP_RESERVED_INST 12 46 #define TRAP_ILLEGAL_SLOT_INST 13 47 #endif 48 49 static void dump_mem(const char *str, unsigned long bottom, unsigned long top) 50 { 51 unsigned long p; 52 int i; 53 54 printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top); 55 56 for (p = bottom & ~31; p < top; ) { 57 printk("%04lx: ", p & 0xffff); 58 59 for (i = 0; i < 8; i++, p += 4) { 60 unsigned int val; 61 62 if (p < bottom || p >= top) 63 printk(" "); 64 else { 65 if (__get_user(val, (unsigned int __user *)p)) { 66 printk("\n"); 67 return; 68 } 69 printk("%08x ", val); 70 } 71 } 72 printk("\n"); 73 } 74 } 75 76 static DEFINE_SPINLOCK(die_lock); 77 78 void die(const char * str, struct pt_regs * regs, long err) 79 { 80 static int die_counter; 81 82 oops_enter(); 83 84 spin_lock_irq(&die_lock); 85 console_verbose(); 86 bust_spinlocks(1); 87 88 printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter); 89 sysfs_printk_last_file(); 90 print_modules(); 91 show_regs(regs); 92 93 printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm, 94 task_pid_nr(current), task_stack_page(current) + 1); 95 96 if (!user_mode(regs) || in_interrupt()) 97 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE + 98 (unsigned long)task_stack_page(current)); 99 100 notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV); 101 102 bust_spinlocks(0); 103 add_taint(TAINT_DIE); 104 spin_unlock_irq(&die_lock); 105 oops_exit(); 106 107 if (kexec_should_crash(current)) 108 crash_kexec(regs); 109 110 if (in_interrupt()) 111 panic("Fatal exception in interrupt"); 112 113 if (panic_on_oops) 114 panic("Fatal exception"); 115 116 do_exit(SIGSEGV); 117 } 118 119 static inline void die_if_kernel(const char *str, struct pt_regs *regs, 120 long err) 121 { 122 if (!user_mode(regs)) 123 die(str, regs, err); 124 } 125 126 /* 127 * try and fix up kernelspace address errors 128 * - userspace errors just cause EFAULT to be returned, resulting in SEGV 129 * - kernel/userspace interfaces cause a jump to an appropriate handler 130 * - other kernel errors are bad 131 */ 132 static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err) 133 { 134 if (!user_mode(regs)) { 135 const struct exception_table_entry *fixup; 136 fixup = search_exception_tables(regs->pc); 137 if (fixup) { 138 regs->pc = fixup->fixup; 139 return; 140 } 141 142 die(str, regs, err); 143 } 144 } 145 146 static inline void sign_extend(unsigned int count, unsigned char *dst) 147 { 148 #ifdef __LITTLE_ENDIAN__ 149 if ((count == 1) && dst[0] & 0x80) { 150 dst[1] = 0xff; 151 dst[2] = 0xff; 152 dst[3] = 0xff; 153 } 154 if ((count == 2) && dst[1] & 0x80) { 155 dst[2] = 0xff; 156 dst[3] = 0xff; 157 } 158 #else 159 if ((count == 1) && dst[3] & 0x80) { 160 dst[2] = 0xff; 161 dst[1] = 0xff; 162 dst[0] = 0xff; 163 } 164 if ((count == 2) && dst[2] & 0x80) { 165 dst[1] = 0xff; 166 dst[0] = 0xff; 167 } 168 #endif 169 } 170 171 static struct mem_access user_mem_access = { 172 copy_from_user, 173 copy_to_user, 174 }; 175 176 /* 177 * handle an instruction that does an unaligned memory access by emulating the 178 * desired behaviour 179 * - note that PC _may not_ point to the faulting instruction 180 * (if that instruction is in a branch delay slot) 181 * - return 0 if emulation okay, -EFAULT on existential error 182 */ 183 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs, 184 struct mem_access *ma) 185 { 186 int ret, index, count; 187 unsigned long *rm, *rn; 188 unsigned char *src, *dst; 189 unsigned char __user *srcu, *dstu; 190 191 index = (instruction>>8)&15; /* 0x0F00 */ 192 rn = ®s->regs[index]; 193 194 index = (instruction>>4)&15; /* 0x00F0 */ 195 rm = ®s->regs[index]; 196 197 count = 1<<(instruction&3); 198 199 switch (count) { 200 case 1: inc_unaligned_byte_access(); break; 201 case 2: inc_unaligned_word_access(); break; 202 case 4: inc_unaligned_dword_access(); break; 203 case 8: inc_unaligned_multi_access(); break; 204 } 205 206 ret = -EFAULT; 207 switch (instruction>>12) { 208 case 0: /* mov.[bwl] to/from memory via r0+rn */ 209 if (instruction & 8) { 210 /* from memory */ 211 srcu = (unsigned char __user *)*rm; 212 srcu += regs->regs[0]; 213 dst = (unsigned char *)rn; 214 *(unsigned long *)dst = 0; 215 216 #if !defined(__LITTLE_ENDIAN__) 217 dst += 4-count; 218 #endif 219 if (ma->from(dst, srcu, count)) 220 goto fetch_fault; 221 222 sign_extend(count, dst); 223 } else { 224 /* to memory */ 225 src = (unsigned char *)rm; 226 #if !defined(__LITTLE_ENDIAN__) 227 src += 4-count; 228 #endif 229 dstu = (unsigned char __user *)*rn; 230 dstu += regs->regs[0]; 231 232 if (ma->to(dstu, src, count)) 233 goto fetch_fault; 234 } 235 ret = 0; 236 break; 237 238 case 1: /* mov.l Rm,@(disp,Rn) */ 239 src = (unsigned char*) rm; 240 dstu = (unsigned char __user *)*rn; 241 dstu += (instruction&0x000F)<<2; 242 243 if (ma->to(dstu, src, 4)) 244 goto fetch_fault; 245 ret = 0; 246 break; 247 248 case 2: /* mov.[bwl] to memory, possibly with pre-decrement */ 249 if (instruction & 4) 250 *rn -= count; 251 src = (unsigned char*) rm; 252 dstu = (unsigned char __user *)*rn; 253 #if !defined(__LITTLE_ENDIAN__) 254 src += 4-count; 255 #endif 256 if (ma->to(dstu, src, count)) 257 goto fetch_fault; 258 ret = 0; 259 break; 260 261 case 5: /* mov.l @(disp,Rm),Rn */ 262 srcu = (unsigned char __user *)*rm; 263 srcu += (instruction & 0x000F) << 2; 264 dst = (unsigned char *)rn; 265 *(unsigned long *)dst = 0; 266 267 if (ma->from(dst, srcu, 4)) 268 goto fetch_fault; 269 ret = 0; 270 break; 271 272 case 6: /* mov.[bwl] from memory, possibly with post-increment */ 273 srcu = (unsigned char __user *)*rm; 274 if (instruction & 4) 275 *rm += count; 276 dst = (unsigned char*) rn; 277 *(unsigned long*)dst = 0; 278 279 #if !defined(__LITTLE_ENDIAN__) 280 dst += 4-count; 281 #endif 282 if (ma->from(dst, srcu, count)) 283 goto fetch_fault; 284 sign_extend(count, dst); 285 ret = 0; 286 break; 287 288 case 8: 289 switch ((instruction&0xFF00)>>8) { 290 case 0x81: /* mov.w R0,@(disp,Rn) */ 291 src = (unsigned char *) ®s->regs[0]; 292 #if !defined(__LITTLE_ENDIAN__) 293 src += 2; 294 #endif 295 dstu = (unsigned char __user *)*rm; /* called Rn in the spec */ 296 dstu += (instruction & 0x000F) << 1; 297 298 if (ma->to(dstu, src, 2)) 299 goto fetch_fault; 300 ret = 0; 301 break; 302 303 case 0x85: /* mov.w @(disp,Rm),R0 */ 304 srcu = (unsigned char __user *)*rm; 305 srcu += (instruction & 0x000F) << 1; 306 dst = (unsigned char *) ®s->regs[0]; 307 *(unsigned long *)dst = 0; 308 309 #if !defined(__LITTLE_ENDIAN__) 310 dst += 2; 311 #endif 312 if (ma->from(dst, srcu, 2)) 313 goto fetch_fault; 314 sign_extend(2, dst); 315 ret = 0; 316 break; 317 } 318 break; 319 } 320 return ret; 321 322 fetch_fault: 323 /* Argh. Address not only misaligned but also non-existent. 324 * Raise an EFAULT and see if it's trapped 325 */ 326 die_if_no_fixup("Fault in unaligned fixup", regs, 0); 327 return -EFAULT; 328 } 329 330 /* 331 * emulate the instruction in the delay slot 332 * - fetches the instruction from PC+2 333 */ 334 static inline int handle_delayslot(struct pt_regs *regs, 335 insn_size_t old_instruction, 336 struct mem_access *ma) 337 { 338 insn_size_t instruction; 339 void __user *addr = (void __user *)(regs->pc + 340 instruction_size(old_instruction)); 341 342 if (copy_from_user(&instruction, addr, sizeof(instruction))) { 343 /* the instruction-fetch faulted */ 344 if (user_mode(regs)) 345 return -EFAULT; 346 347 /* kernel */ 348 die("delay-slot-insn faulting in handle_unaligned_delayslot", 349 regs, 0); 350 } 351 352 return handle_unaligned_ins(instruction, regs, ma); 353 } 354 355 /* 356 * handle an instruction that does an unaligned memory access 357 * - have to be careful of branch delay-slot instructions that fault 358 * SH3: 359 * - if the branch would be taken PC points to the branch 360 * - if the branch would not be taken, PC points to delay-slot 361 * SH4: 362 * - PC always points to delayed branch 363 * - return 0 if handled, -EFAULT if failed (may not return if in kernel) 364 */ 365 366 /* Macros to determine offset from current PC for branch instructions */ 367 /* Explicit type coercion is used to force sign extension where needed */ 368 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4) 369 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4) 370 371 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, 372 struct mem_access *ma, int expected) 373 { 374 u_int rm; 375 int ret, index; 376 377 /* 378 * XXX: We can't handle mixed 16/32-bit instructions yet 379 */ 380 if (instruction_size(instruction) != 2) 381 return -EINVAL; 382 383 index = (instruction>>8)&15; /* 0x0F00 */ 384 rm = regs->regs[index]; 385 386 /* shout about fixups */ 387 if (!expected) 388 unaligned_fixups_notify(current, instruction, regs); 389 390 ret = -EFAULT; 391 switch (instruction&0xF000) { 392 case 0x0000: 393 if (instruction==0x000B) { 394 /* rts */ 395 ret = handle_delayslot(regs, instruction, ma); 396 if (ret==0) 397 regs->pc = regs->pr; 398 } 399 else if ((instruction&0x00FF)==0x0023) { 400 /* braf @Rm */ 401 ret = handle_delayslot(regs, instruction, ma); 402 if (ret==0) 403 regs->pc += rm + 4; 404 } 405 else if ((instruction&0x00FF)==0x0003) { 406 /* bsrf @Rm */ 407 ret = handle_delayslot(regs, instruction, ma); 408 if (ret==0) { 409 regs->pr = regs->pc + 4; 410 regs->pc += rm + 4; 411 } 412 } 413 else { 414 /* mov.[bwl] to/from memory via r0+rn */ 415 goto simple; 416 } 417 break; 418 419 case 0x1000: /* mov.l Rm,@(disp,Rn) */ 420 goto simple; 421 422 case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */ 423 goto simple; 424 425 case 0x4000: 426 if ((instruction&0x00FF)==0x002B) { 427 /* jmp @Rm */ 428 ret = handle_delayslot(regs, instruction, ma); 429 if (ret==0) 430 regs->pc = rm; 431 } 432 else if ((instruction&0x00FF)==0x000B) { 433 /* jsr @Rm */ 434 ret = handle_delayslot(regs, instruction, ma); 435 if (ret==0) { 436 regs->pr = regs->pc + 4; 437 regs->pc = rm; 438 } 439 } 440 else { 441 /* mov.[bwl] to/from memory via r0+rn */ 442 goto simple; 443 } 444 break; 445 446 case 0x5000: /* mov.l @(disp,Rm),Rn */ 447 goto simple; 448 449 case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */ 450 goto simple; 451 452 case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */ 453 switch (instruction&0x0F00) { 454 case 0x0100: /* mov.w R0,@(disp,Rm) */ 455 goto simple; 456 case 0x0500: /* mov.w @(disp,Rm),R0 */ 457 goto simple; 458 case 0x0B00: /* bf lab - no delayslot*/ 459 break; 460 case 0x0F00: /* bf/s lab */ 461 ret = handle_delayslot(regs, instruction, ma); 462 if (ret==0) { 463 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) 464 if ((regs->sr & 0x00000001) != 0) 465 regs->pc += 4; /* next after slot */ 466 else 467 #endif 468 regs->pc += SH_PC_8BIT_OFFSET(instruction); 469 } 470 break; 471 case 0x0900: /* bt lab - no delayslot */ 472 break; 473 case 0x0D00: /* bt/s lab */ 474 ret = handle_delayslot(regs, instruction, ma); 475 if (ret==0) { 476 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) 477 if ((regs->sr & 0x00000001) == 0) 478 regs->pc += 4; /* next after slot */ 479 else 480 #endif 481 regs->pc += SH_PC_8BIT_OFFSET(instruction); 482 } 483 break; 484 } 485 break; 486 487 case 0xA000: /* bra label */ 488 ret = handle_delayslot(regs, instruction, ma); 489 if (ret==0) 490 regs->pc += SH_PC_12BIT_OFFSET(instruction); 491 break; 492 493 case 0xB000: /* bsr label */ 494 ret = handle_delayslot(regs, instruction, ma); 495 if (ret==0) { 496 regs->pr = regs->pc + 4; 497 regs->pc += SH_PC_12BIT_OFFSET(instruction); 498 } 499 break; 500 } 501 return ret; 502 503 /* handle non-delay-slot instruction */ 504 simple: 505 ret = handle_unaligned_ins(instruction, regs, ma); 506 if (ret==0) 507 regs->pc += instruction_size(instruction); 508 return ret; 509 } 510 511 /* 512 * Handle various address error exceptions: 513 * - instruction address error: 514 * misaligned PC 515 * PC >= 0x80000000 in user mode 516 * - data address error (read and write) 517 * misaligned data access 518 * access to >= 0x80000000 is user mode 519 * Unfortuntaly we can't distinguish between instruction address error 520 * and data address errors caused by read accesses. 521 */ 522 asmlinkage void do_address_error(struct pt_regs *regs, 523 unsigned long writeaccess, 524 unsigned long address) 525 { 526 unsigned long error_code = 0; 527 mm_segment_t oldfs; 528 siginfo_t info; 529 insn_size_t instruction; 530 int tmp; 531 532 /* Intentional ifdef */ 533 #ifdef CONFIG_CPU_HAS_SR_RB 534 error_code = lookup_exception_vector(); 535 #endif 536 537 oldfs = get_fs(); 538 539 if (user_mode(regs)) { 540 int si_code = BUS_ADRERR; 541 unsigned int user_action; 542 543 local_irq_enable(); 544 inc_unaligned_user_access(); 545 546 set_fs(USER_DS); 547 if (copy_from_user(&instruction, (insn_size_t *)(regs->pc & ~1), 548 sizeof(instruction))) { 549 set_fs(oldfs); 550 goto uspace_segv; 551 } 552 set_fs(oldfs); 553 554 /* shout about userspace fixups */ 555 unaligned_fixups_notify(current, instruction, regs); 556 557 user_action = unaligned_user_action(); 558 if (user_action & UM_FIXUP) 559 goto fixup; 560 if (user_action & UM_SIGNAL) 561 goto uspace_segv; 562 else { 563 /* ignore */ 564 regs->pc += instruction_size(instruction); 565 return; 566 } 567 568 fixup: 569 /* bad PC is not something we can fix */ 570 if (regs->pc & 1) { 571 si_code = BUS_ADRALN; 572 goto uspace_segv; 573 } 574 575 set_fs(USER_DS); 576 tmp = handle_unaligned_access(instruction, regs, 577 &user_mem_access, 0); 578 set_fs(oldfs); 579 580 if (tmp == 0) 581 return; /* sorted */ 582 uspace_segv: 583 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned " 584 "access (PC %lx PR %lx)\n", current->comm, regs->pc, 585 regs->pr); 586 587 info.si_signo = SIGBUS; 588 info.si_errno = 0; 589 info.si_code = si_code; 590 info.si_addr = (void __user *)address; 591 force_sig_info(SIGBUS, &info, current); 592 } else { 593 inc_unaligned_kernel_access(); 594 595 if (regs->pc & 1) 596 die("unaligned program counter", regs, error_code); 597 598 set_fs(KERNEL_DS); 599 if (copy_from_user(&instruction, (void __user *)(regs->pc), 600 sizeof(instruction))) { 601 /* Argh. Fault on the instruction itself. 602 This should never happen non-SMP 603 */ 604 set_fs(oldfs); 605 die("insn faulting in do_address_error", regs, 0); 606 } 607 608 unaligned_fixups_notify(current, instruction, regs); 609 610 handle_unaligned_access(instruction, regs, 611 &user_mem_access, 0); 612 set_fs(oldfs); 613 } 614 } 615 616 #ifdef CONFIG_SH_DSP 617 /* 618 * SH-DSP support gerg@snapgear.com. 619 */ 620 int is_dsp_inst(struct pt_regs *regs) 621 { 622 unsigned short inst = 0; 623 624 /* 625 * Safe guard if DSP mode is already enabled or we're lacking 626 * the DSP altogether. 627 */ 628 if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP)) 629 return 0; 630 631 get_user(inst, ((unsigned short *) regs->pc)); 632 633 inst &= 0xf000; 634 635 /* Check for any type of DSP or support instruction */ 636 if ((inst == 0xf000) || (inst == 0x4000)) 637 return 1; 638 639 return 0; 640 } 641 #else 642 #define is_dsp_inst(regs) (0) 643 #endif /* CONFIG_SH_DSP */ 644 645 #ifdef CONFIG_CPU_SH2A 646 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5, 647 unsigned long r6, unsigned long r7, 648 struct pt_regs __regs) 649 { 650 siginfo_t info; 651 652 switch (r4) { 653 case TRAP_DIVZERO_ERROR: 654 info.si_code = FPE_INTDIV; 655 break; 656 case TRAP_DIVOVF_ERROR: 657 info.si_code = FPE_INTOVF; 658 break; 659 } 660 661 force_sig_info(SIGFPE, &info, current); 662 } 663 #endif 664 665 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5, 666 unsigned long r6, unsigned long r7, 667 struct pt_regs __regs) 668 { 669 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); 670 unsigned long error_code; 671 struct task_struct *tsk = current; 672 673 #ifdef CONFIG_SH_FPU_EMU 674 unsigned short inst = 0; 675 int err; 676 677 get_user(inst, (unsigned short*)regs->pc); 678 679 err = do_fpu_inst(inst, regs); 680 if (!err) { 681 regs->pc += instruction_size(inst); 682 return; 683 } 684 /* not a FPU inst. */ 685 #endif 686 687 #ifdef CONFIG_SH_DSP 688 /* Check if it's a DSP instruction */ 689 if (is_dsp_inst(regs)) { 690 /* Enable DSP mode, and restart instruction. */ 691 regs->sr |= SR_DSP; 692 /* Save DSP mode */ 693 tsk->thread.dsp_status.status |= SR_DSP; 694 return; 695 } 696 #endif 697 698 error_code = lookup_exception_vector(); 699 700 local_irq_enable(); 701 force_sig(SIGILL, tsk); 702 die_if_no_fixup("reserved instruction", regs, error_code); 703 } 704 705 #ifdef CONFIG_SH_FPU_EMU 706 static int emulate_branch(unsigned short inst, struct pt_regs *regs) 707 { 708 /* 709 * bfs: 8fxx: PC+=d*2+4; 710 * bts: 8dxx: PC+=d*2+4; 711 * bra: axxx: PC+=D*2+4; 712 * bsr: bxxx: PC+=D*2+4 after PR=PC+4; 713 * braf:0x23: PC+=Rn*2+4; 714 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4; 715 * jmp: 4x2b: PC=Rn; 716 * jsr: 4x0b: PC=Rn after PR=PC+4; 717 * rts: 000b: PC=PR; 718 */ 719 if (((inst & 0xf000) == 0xb000) || /* bsr */ 720 ((inst & 0xf0ff) == 0x0003) || /* bsrf */ 721 ((inst & 0xf0ff) == 0x400b)) /* jsr */ 722 regs->pr = regs->pc + 4; 723 724 if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */ 725 regs->pc += SH_PC_8BIT_OFFSET(inst); 726 return 0; 727 } 728 729 if ((inst & 0xe000) == 0xa000) { /* bra, bsr */ 730 regs->pc += SH_PC_12BIT_OFFSET(inst); 731 return 0; 732 } 733 734 if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */ 735 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4; 736 return 0; 737 } 738 739 if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */ 740 regs->pc = regs->regs[(inst & 0x0f00) >> 8]; 741 return 0; 742 } 743 744 if ((inst & 0xffff) == 0x000b) { /* rts */ 745 regs->pc = regs->pr; 746 return 0; 747 } 748 749 return 1; 750 } 751 #endif 752 753 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5, 754 unsigned long r6, unsigned long r7, 755 struct pt_regs __regs) 756 { 757 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); 758 unsigned long inst; 759 struct task_struct *tsk = current; 760 761 if (kprobe_handle_illslot(regs->pc) == 0) 762 return; 763 764 #ifdef CONFIG_SH_FPU_EMU 765 get_user(inst, (unsigned short *)regs->pc + 1); 766 if (!do_fpu_inst(inst, regs)) { 767 get_user(inst, (unsigned short *)regs->pc); 768 if (!emulate_branch(inst, regs)) 769 return; 770 /* fault in branch.*/ 771 } 772 /* not a FPU inst. */ 773 #endif 774 775 inst = lookup_exception_vector(); 776 777 local_irq_enable(); 778 force_sig(SIGILL, tsk); 779 die_if_no_fixup("illegal slot instruction", regs, inst); 780 } 781 782 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5, 783 unsigned long r6, unsigned long r7, 784 struct pt_regs __regs) 785 { 786 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); 787 long ex; 788 789 ex = lookup_exception_vector(); 790 die_if_kernel("exception", regs, ex); 791 } 792 793 void __cpuinit per_cpu_trap_init(void) 794 { 795 extern void *vbr_base; 796 797 /* NOTE: The VBR value should be at P1 798 (or P2, virtural "fixed" address space). 799 It's definitely should not in physical address. */ 800 801 asm volatile("ldc %0, vbr" 802 : /* no output */ 803 : "r" (&vbr_base) 804 : "memory"); 805 } 806 807 void *set_exception_table_vec(unsigned int vec, void *handler) 808 { 809 extern void *exception_handling_table[]; 810 void *old_handler; 811 812 old_handler = exception_handling_table[vec]; 813 exception_handling_table[vec] = handler; 814 return old_handler; 815 } 816 817 void __init trap_init(void) 818 { 819 set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst); 820 set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst); 821 822 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \ 823 defined(CONFIG_SH_FPU_EMU) 824 /* 825 * For SH-4 lacking an FPU, treat floating point instructions as 826 * reserved. They'll be handled in the math-emu case, or faulted on 827 * otherwise. 828 */ 829 set_exception_table_evt(0x800, do_reserved_inst); 830 set_exception_table_evt(0x820, do_illegal_slot_inst); 831 #elif defined(CONFIG_SH_FPU) 832 set_exception_table_evt(0x800, fpu_state_restore_trap_handler); 833 set_exception_table_evt(0x820, fpu_state_restore_trap_handler); 834 #endif 835 836 #ifdef CONFIG_CPU_SH2 837 set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler); 838 #endif 839 #ifdef CONFIG_CPU_SH2A 840 set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error); 841 set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error); 842 #ifdef CONFIG_SH_FPU 843 set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler); 844 #endif 845 #endif 846 847 #ifdef TRAP_UBC 848 set_exception_table_vec(TRAP_UBC, breakpoint_trap_handler); 849 #endif 850 } 851 852 void show_stack(struct task_struct *tsk, unsigned long *sp) 853 { 854 unsigned long stack; 855 856 if (!tsk) 857 tsk = current; 858 if (tsk == current) 859 sp = (unsigned long *)current_stack_pointer; 860 else 861 sp = (unsigned long *)tsk->thread.sp; 862 863 stack = (unsigned long)sp; 864 dump_mem("Stack: ", stack, THREAD_SIZE + 865 (unsigned long)task_stack_page(tsk)); 866 show_trace(tsk, sp, NULL); 867 } 868 869 void dump_stack(void) 870 { 871 show_stack(NULL, NULL); 872 } 873 EXPORT_SYMBOL(dump_stack); 874