1 /* 2 * 'traps.c' handles hardware traps and faults after we have saved some 3 * state in 'entry.S'. 4 * 5 * SuperH version: Copyright (C) 1999 Niibe Yutaka 6 * Copyright (C) 2000 Philipp Rumpf 7 * Copyright (C) 2000 David Howells 8 * Copyright (C) 2002 - 2007 Paul Mundt 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file "COPYING" in the main directory of this archive 12 * for more details. 13 */ 14 #include <linux/kernel.h> 15 #include <linux/ptrace.h> 16 #include <linux/init.h> 17 #include <linux/spinlock.h> 18 #include <linux/module.h> 19 #include <linux/kallsyms.h> 20 #include <linux/io.h> 21 #include <linux/bug.h> 22 #include <linux/debug_locks.h> 23 #include <linux/kdebug.h> 24 #include <linux/kexec.h> 25 #include <linux/limits.h> 26 #include <asm/system.h> 27 #include <asm/uaccess.h> 28 29 #ifdef CONFIG_SH_KGDB 30 #include <asm/kgdb.h> 31 #define CHK_REMOTE_DEBUG(regs) \ 32 { \ 33 if (kgdb_debug_hook && !user_mode(regs))\ 34 (*kgdb_debug_hook)(regs); \ 35 } 36 #else 37 #define CHK_REMOTE_DEBUG(regs) 38 #endif 39 40 #ifdef CONFIG_CPU_SH2 41 # define TRAP_RESERVED_INST 4 42 # define TRAP_ILLEGAL_SLOT_INST 6 43 # define TRAP_ADDRESS_ERROR 9 44 # ifdef CONFIG_CPU_SH2A 45 # define TRAP_DIVZERO_ERROR 17 46 # define TRAP_DIVOVF_ERROR 18 47 # endif 48 #else 49 #define TRAP_RESERVED_INST 12 50 #define TRAP_ILLEGAL_SLOT_INST 13 51 #endif 52 53 static void dump_mem(const char *str, unsigned long bottom, unsigned long top) 54 { 55 unsigned long p; 56 int i; 57 58 printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top); 59 60 for (p = bottom & ~31; p < top; ) { 61 printk("%04lx: ", p & 0xffff); 62 63 for (i = 0; i < 8; i++, p += 4) { 64 unsigned int val; 65 66 if (p < bottom || p >= top) 67 printk(" "); 68 else { 69 if (__get_user(val, (unsigned int __user *)p)) { 70 printk("\n"); 71 return; 72 } 73 printk("%08x ", val); 74 } 75 } 76 printk("\n"); 77 } 78 } 79 80 static DEFINE_SPINLOCK(die_lock); 81 82 void die(const char * str, struct pt_regs * regs, long err) 83 { 84 static int die_counter; 85 86 oops_enter(); 87 88 console_verbose(); 89 spin_lock_irq(&die_lock); 90 bust_spinlocks(1); 91 92 printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter); 93 94 CHK_REMOTE_DEBUG(regs); 95 print_modules(); 96 show_regs(regs); 97 98 printk("Process: %s (pid: %d, stack limit = %p)\n", 99 current->comm, current->pid, task_stack_page(current) + 1); 100 101 if (!user_mode(regs) || in_interrupt()) 102 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE + 103 (unsigned long)task_stack_page(current)); 104 105 bust_spinlocks(0); 106 add_taint(TAINT_DIE); 107 spin_unlock_irq(&die_lock); 108 109 if (kexec_should_crash(current)) 110 crash_kexec(regs); 111 112 if (in_interrupt()) 113 panic("Fatal exception in interrupt"); 114 115 if (panic_on_oops) 116 panic("Fatal exception"); 117 118 oops_exit(); 119 do_exit(SIGSEGV); 120 } 121 122 static inline void die_if_kernel(const char *str, struct pt_regs *regs, 123 long err) 124 { 125 if (!user_mode(regs)) 126 die(str, regs, err); 127 } 128 129 /* 130 * try and fix up kernelspace address errors 131 * - userspace errors just cause EFAULT to be returned, resulting in SEGV 132 * - kernel/userspace interfaces cause a jump to an appropriate handler 133 * - other kernel errors are bad 134 * - return 0 if fixed-up, -EFAULT if non-fatal (to the kernel) fault 135 */ 136 static int die_if_no_fixup(const char * str, struct pt_regs * regs, long err) 137 { 138 if (!user_mode(regs)) { 139 const struct exception_table_entry *fixup; 140 fixup = search_exception_tables(regs->pc); 141 if (fixup) { 142 regs->pc = fixup->fixup; 143 return 0; 144 } 145 die(str, regs, err); 146 } 147 return -EFAULT; 148 } 149 150 /* 151 * handle an instruction that does an unaligned memory access by emulating the 152 * desired behaviour 153 * - note that PC _may not_ point to the faulting instruction 154 * (if that instruction is in a branch delay slot) 155 * - return 0 if emulation okay, -EFAULT on existential error 156 */ 157 static int handle_unaligned_ins(u16 instruction, struct pt_regs *regs) 158 { 159 int ret, index, count; 160 unsigned long *rm, *rn; 161 unsigned char *src, *dst; 162 163 index = (instruction>>8)&15; /* 0x0F00 */ 164 rn = ®s->regs[index]; 165 166 index = (instruction>>4)&15; /* 0x00F0 */ 167 rm = ®s->regs[index]; 168 169 count = 1<<(instruction&3); 170 171 ret = -EFAULT; 172 switch (instruction>>12) { 173 case 0: /* mov.[bwl] to/from memory via r0+rn */ 174 if (instruction & 8) { 175 /* from memory */ 176 src = (unsigned char*) *rm; 177 src += regs->regs[0]; 178 dst = (unsigned char*) rn; 179 *(unsigned long*)dst = 0; 180 181 #ifdef __LITTLE_ENDIAN__ 182 if (copy_from_user(dst, src, count)) 183 goto fetch_fault; 184 185 if ((count == 2) && dst[1] & 0x80) { 186 dst[2] = 0xff; 187 dst[3] = 0xff; 188 } 189 #else 190 dst += 4-count; 191 192 if (__copy_user(dst, src, count)) 193 goto fetch_fault; 194 195 if ((count == 2) && dst[2] & 0x80) { 196 dst[0] = 0xff; 197 dst[1] = 0xff; 198 } 199 #endif 200 } else { 201 /* to memory */ 202 src = (unsigned char*) rm; 203 #if !defined(__LITTLE_ENDIAN__) 204 src += 4-count; 205 #endif 206 dst = (unsigned char*) *rn; 207 dst += regs->regs[0]; 208 209 if (copy_to_user(dst, src, count)) 210 goto fetch_fault; 211 } 212 ret = 0; 213 break; 214 215 case 1: /* mov.l Rm,@(disp,Rn) */ 216 src = (unsigned char*) rm; 217 dst = (unsigned char*) *rn; 218 dst += (instruction&0x000F)<<2; 219 220 if (copy_to_user(dst,src,4)) 221 goto fetch_fault; 222 ret = 0; 223 break; 224 225 case 2: /* mov.[bwl] to memory, possibly with pre-decrement */ 226 if (instruction & 4) 227 *rn -= count; 228 src = (unsigned char*) rm; 229 dst = (unsigned char*) *rn; 230 #if !defined(__LITTLE_ENDIAN__) 231 src += 4-count; 232 #endif 233 if (copy_to_user(dst, src, count)) 234 goto fetch_fault; 235 ret = 0; 236 break; 237 238 case 5: /* mov.l @(disp,Rm),Rn */ 239 src = (unsigned char*) *rm; 240 src += (instruction&0x000F)<<2; 241 dst = (unsigned char*) rn; 242 *(unsigned long*)dst = 0; 243 244 if (copy_from_user(dst,src,4)) 245 goto fetch_fault; 246 ret = 0; 247 break; 248 249 case 6: /* mov.[bwl] from memory, possibly with post-increment */ 250 src = (unsigned char*) *rm; 251 if (instruction & 4) 252 *rm += count; 253 dst = (unsigned char*) rn; 254 *(unsigned long*)dst = 0; 255 256 #ifdef __LITTLE_ENDIAN__ 257 if (copy_from_user(dst, src, count)) 258 goto fetch_fault; 259 260 if ((count == 2) && dst[1] & 0x80) { 261 dst[2] = 0xff; 262 dst[3] = 0xff; 263 } 264 #else 265 dst += 4-count; 266 267 if (copy_from_user(dst, src, count)) 268 goto fetch_fault; 269 270 if ((count == 2) && dst[2] & 0x80) { 271 dst[0] = 0xff; 272 dst[1] = 0xff; 273 } 274 #endif 275 ret = 0; 276 break; 277 278 case 8: 279 switch ((instruction&0xFF00)>>8) { 280 case 0x81: /* mov.w R0,@(disp,Rn) */ 281 src = (unsigned char*) ®s->regs[0]; 282 #if !defined(__LITTLE_ENDIAN__) 283 src += 2; 284 #endif 285 dst = (unsigned char*) *rm; /* called Rn in the spec */ 286 dst += (instruction&0x000F)<<1; 287 288 if (copy_to_user(dst, src, 2)) 289 goto fetch_fault; 290 ret = 0; 291 break; 292 293 case 0x85: /* mov.w @(disp,Rm),R0 */ 294 src = (unsigned char*) *rm; 295 src += (instruction&0x000F)<<1; 296 dst = (unsigned char*) ®s->regs[0]; 297 *(unsigned long*)dst = 0; 298 299 #if !defined(__LITTLE_ENDIAN__) 300 dst += 2; 301 #endif 302 303 if (copy_from_user(dst, src, 2)) 304 goto fetch_fault; 305 306 #ifdef __LITTLE_ENDIAN__ 307 if (dst[1] & 0x80) { 308 dst[2] = 0xff; 309 dst[3] = 0xff; 310 } 311 #else 312 if (dst[2] & 0x80) { 313 dst[0] = 0xff; 314 dst[1] = 0xff; 315 } 316 #endif 317 ret = 0; 318 break; 319 } 320 break; 321 } 322 return ret; 323 324 fetch_fault: 325 /* Argh. Address not only misaligned but also non-existent. 326 * Raise an EFAULT and see if it's trapped 327 */ 328 return die_if_no_fixup("Fault in unaligned fixup", regs, 0); 329 } 330 331 /* 332 * emulate the instruction in the delay slot 333 * - fetches the instruction from PC+2 334 */ 335 static inline int handle_unaligned_delayslot(struct pt_regs *regs) 336 { 337 u16 instruction; 338 339 if (copy_from_user(&instruction, (u16 *)(regs->pc+2), 2)) { 340 /* the instruction-fetch faulted */ 341 if (user_mode(regs)) 342 return -EFAULT; 343 344 /* kernel */ 345 die("delay-slot-insn faulting in handle_unaligned_delayslot", 346 regs, 0); 347 } 348 349 return handle_unaligned_ins(instruction,regs); 350 } 351 352 /* 353 * handle an instruction that does an unaligned memory access 354 * - have to be careful of branch delay-slot instructions that fault 355 * SH3: 356 * - if the branch would be taken PC points to the branch 357 * - if the branch would not be taken, PC points to delay-slot 358 * SH4: 359 * - PC always points to delayed branch 360 * - return 0 if handled, -EFAULT if failed (may not return if in kernel) 361 */ 362 363 /* Macros to determine offset from current PC for branch instructions */ 364 /* Explicit type coercion is used to force sign extension where needed */ 365 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4) 366 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4) 367 368 /* 369 * XXX: SH-2A needs this too, but it needs an overhaul thanks to mixed 32-bit 370 * opcodes.. 371 */ 372 #ifndef CONFIG_CPU_SH2A 373 static int handle_unaligned_notify_count = 10; 374 375 static int handle_unaligned_access(u16 instruction, struct pt_regs *regs) 376 { 377 u_int rm; 378 int ret, index; 379 380 index = (instruction>>8)&15; /* 0x0F00 */ 381 rm = regs->regs[index]; 382 383 /* shout about the first ten userspace fixups */ 384 if (user_mode(regs) && handle_unaligned_notify_count>0) { 385 handle_unaligned_notify_count--; 386 387 printk(KERN_NOTICE "Fixing up unaligned userspace access " 388 "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n", 389 current->comm,current->pid,(u16*)regs->pc,instruction); 390 } 391 392 ret = -EFAULT; 393 switch (instruction&0xF000) { 394 case 0x0000: 395 if (instruction==0x000B) { 396 /* rts */ 397 ret = handle_unaligned_delayslot(regs); 398 if (ret==0) 399 regs->pc = regs->pr; 400 } 401 else if ((instruction&0x00FF)==0x0023) { 402 /* braf @Rm */ 403 ret = handle_unaligned_delayslot(regs); 404 if (ret==0) 405 regs->pc += rm + 4; 406 } 407 else if ((instruction&0x00FF)==0x0003) { 408 /* bsrf @Rm */ 409 ret = handle_unaligned_delayslot(regs); 410 if (ret==0) { 411 regs->pr = regs->pc + 4; 412 regs->pc += rm + 4; 413 } 414 } 415 else { 416 /* mov.[bwl] to/from memory via r0+rn */ 417 goto simple; 418 } 419 break; 420 421 case 0x1000: /* mov.l Rm,@(disp,Rn) */ 422 goto simple; 423 424 case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */ 425 goto simple; 426 427 case 0x4000: 428 if ((instruction&0x00FF)==0x002B) { 429 /* jmp @Rm */ 430 ret = handle_unaligned_delayslot(regs); 431 if (ret==0) 432 regs->pc = rm; 433 } 434 else if ((instruction&0x00FF)==0x000B) { 435 /* jsr @Rm */ 436 ret = handle_unaligned_delayslot(regs); 437 if (ret==0) { 438 regs->pr = regs->pc + 4; 439 regs->pc = rm; 440 } 441 } 442 else { 443 /* mov.[bwl] to/from memory via r0+rn */ 444 goto simple; 445 } 446 break; 447 448 case 0x5000: /* mov.l @(disp,Rm),Rn */ 449 goto simple; 450 451 case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */ 452 goto simple; 453 454 case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */ 455 switch (instruction&0x0F00) { 456 case 0x0100: /* mov.w R0,@(disp,Rm) */ 457 goto simple; 458 case 0x0500: /* mov.w @(disp,Rm),R0 */ 459 goto simple; 460 case 0x0B00: /* bf lab - no delayslot*/ 461 break; 462 case 0x0F00: /* bf/s lab */ 463 ret = handle_unaligned_delayslot(regs); 464 if (ret==0) { 465 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) 466 if ((regs->sr & 0x00000001) != 0) 467 regs->pc += 4; /* next after slot */ 468 else 469 #endif 470 regs->pc += SH_PC_8BIT_OFFSET(instruction); 471 } 472 break; 473 case 0x0900: /* bt lab - no delayslot */ 474 break; 475 case 0x0D00: /* bt/s lab */ 476 ret = handle_unaligned_delayslot(regs); 477 if (ret==0) { 478 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) 479 if ((regs->sr & 0x00000001) == 0) 480 regs->pc += 4; /* next after slot */ 481 else 482 #endif 483 regs->pc += SH_PC_8BIT_OFFSET(instruction); 484 } 485 break; 486 } 487 break; 488 489 case 0xA000: /* bra label */ 490 ret = handle_unaligned_delayslot(regs); 491 if (ret==0) 492 regs->pc += SH_PC_12BIT_OFFSET(instruction); 493 break; 494 495 case 0xB000: /* bsr label */ 496 ret = handle_unaligned_delayslot(regs); 497 if (ret==0) { 498 regs->pr = regs->pc + 4; 499 regs->pc += SH_PC_12BIT_OFFSET(instruction); 500 } 501 break; 502 } 503 return ret; 504 505 /* handle non-delay-slot instruction */ 506 simple: 507 ret = handle_unaligned_ins(instruction,regs); 508 if (ret==0) 509 regs->pc += instruction_size(instruction); 510 return ret; 511 } 512 #endif /* CONFIG_CPU_SH2A */ 513 514 #ifdef CONFIG_CPU_HAS_SR_RB 515 #define lookup_exception_vector(x) \ 516 __asm__ __volatile__ ("stc r2_bank, %0\n\t" : "=r" ((x))) 517 #else 518 #define lookup_exception_vector(x) \ 519 __asm__ __volatile__ ("mov r4, %0\n\t" : "=r" ((x))) 520 #endif 521 522 /* 523 * Handle various address error exceptions: 524 * - instruction address error: 525 * misaligned PC 526 * PC >= 0x80000000 in user mode 527 * - data address error (read and write) 528 * misaligned data access 529 * access to >= 0x80000000 is user mode 530 * Unfortuntaly we can't distinguish between instruction address error 531 * and data address errors caused by read accesses. 532 */ 533 asmlinkage void do_address_error(struct pt_regs *regs, 534 unsigned long writeaccess, 535 unsigned long address) 536 { 537 unsigned long error_code = 0; 538 mm_segment_t oldfs; 539 siginfo_t info; 540 #ifndef CONFIG_CPU_SH2A 541 u16 instruction; 542 int tmp; 543 #endif 544 545 /* Intentional ifdef */ 546 #ifdef CONFIG_CPU_HAS_SR_RB 547 lookup_exception_vector(error_code); 548 #endif 549 550 oldfs = get_fs(); 551 552 if (user_mode(regs)) { 553 int si_code = BUS_ADRERR; 554 555 local_irq_enable(); 556 557 /* bad PC is not something we can fix */ 558 if (regs->pc & 1) { 559 si_code = BUS_ADRALN; 560 goto uspace_segv; 561 } 562 563 #ifndef CONFIG_CPU_SH2A 564 set_fs(USER_DS); 565 if (copy_from_user(&instruction, (u16 *)(regs->pc), 2)) { 566 /* Argh. Fault on the instruction itself. 567 This should never happen non-SMP 568 */ 569 set_fs(oldfs); 570 goto uspace_segv; 571 } 572 573 tmp = handle_unaligned_access(instruction, regs); 574 set_fs(oldfs); 575 576 if (tmp==0) 577 return; /* sorted */ 578 #endif 579 580 uspace_segv: 581 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned " 582 "access (PC %lx PR %lx)\n", current->comm, regs->pc, 583 regs->pr); 584 585 info.si_signo = SIGBUS; 586 info.si_errno = 0; 587 info.si_code = si_code; 588 info.si_addr = (void __user *)address; 589 force_sig_info(SIGBUS, &info, current); 590 } else { 591 if (regs->pc & 1) 592 die("unaligned program counter", regs, error_code); 593 594 #ifndef CONFIG_CPU_SH2A 595 set_fs(KERNEL_DS); 596 if (copy_from_user(&instruction, (u16 *)(regs->pc), 2)) { 597 /* Argh. Fault on the instruction itself. 598 This should never happen non-SMP 599 */ 600 set_fs(oldfs); 601 die("insn faulting in do_address_error", regs, 0); 602 } 603 604 handle_unaligned_access(instruction, regs); 605 set_fs(oldfs); 606 #else 607 printk(KERN_NOTICE "Killing process \"%s\" due to unaligned " 608 "access\n", current->comm); 609 610 force_sig(SIGSEGV, current); 611 #endif 612 } 613 } 614 615 #ifdef CONFIG_SH_DSP 616 /* 617 * SH-DSP support gerg@snapgear.com. 618 */ 619 int is_dsp_inst(struct pt_regs *regs) 620 { 621 unsigned short inst = 0; 622 623 /* 624 * Safe guard if DSP mode is already enabled or we're lacking 625 * the DSP altogether. 626 */ 627 if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP)) 628 return 0; 629 630 get_user(inst, ((unsigned short *) regs->pc)); 631 632 inst &= 0xf000; 633 634 /* Check for any type of DSP or support instruction */ 635 if ((inst == 0xf000) || (inst == 0x4000)) 636 return 1; 637 638 return 0; 639 } 640 #else 641 #define is_dsp_inst(regs) (0) 642 #endif /* CONFIG_SH_DSP */ 643 644 #ifdef CONFIG_CPU_SH2A 645 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5, 646 unsigned long r6, unsigned long r7, 647 struct pt_regs __regs) 648 { 649 siginfo_t info; 650 651 switch (r4) { 652 case TRAP_DIVZERO_ERROR: 653 info.si_code = FPE_INTDIV; 654 break; 655 case TRAP_DIVOVF_ERROR: 656 info.si_code = FPE_INTOVF; 657 break; 658 } 659 660 force_sig_info(SIGFPE, &info, current); 661 } 662 #endif 663 664 /* arch/sh/kernel/cpu/sh4/fpu.c */ 665 extern int do_fpu_inst(unsigned short, struct pt_regs *); 666 extern asmlinkage void do_fpu_state_restore(unsigned long r4, unsigned long r5, 667 unsigned long r6, unsigned long r7, struct pt_regs __regs); 668 669 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5, 670 unsigned long r6, unsigned long r7, 671 struct pt_regs __regs) 672 { 673 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); 674 unsigned long error_code; 675 struct task_struct *tsk = current; 676 677 #ifdef CONFIG_SH_FPU_EMU 678 unsigned short inst = 0; 679 int err; 680 681 get_user(inst, (unsigned short*)regs->pc); 682 683 err = do_fpu_inst(inst, regs); 684 if (!err) { 685 regs->pc += instruction_size(inst); 686 return; 687 } 688 /* not a FPU inst. */ 689 #endif 690 691 #ifdef CONFIG_SH_DSP 692 /* Check if it's a DSP instruction */ 693 if (is_dsp_inst(regs)) { 694 /* Enable DSP mode, and restart instruction. */ 695 regs->sr |= SR_DSP; 696 return; 697 } 698 #endif 699 700 lookup_exception_vector(error_code); 701 702 local_irq_enable(); 703 CHK_REMOTE_DEBUG(regs); 704 force_sig(SIGILL, tsk); 705 die_if_no_fixup("reserved instruction", regs, error_code); 706 } 707 708 #ifdef CONFIG_SH_FPU_EMU 709 static int emulate_branch(unsigned short inst, struct pt_regs* regs) 710 { 711 /* 712 * bfs: 8fxx: PC+=d*2+4; 713 * bts: 8dxx: PC+=d*2+4; 714 * bra: axxx: PC+=D*2+4; 715 * bsr: bxxx: PC+=D*2+4 after PR=PC+4; 716 * braf:0x23: PC+=Rn*2+4; 717 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4; 718 * jmp: 4x2b: PC=Rn; 719 * jsr: 4x0b: PC=Rn after PR=PC+4; 720 * rts: 000b: PC=PR; 721 */ 722 if ((inst & 0xfd00) == 0x8d00) { 723 regs->pc += SH_PC_8BIT_OFFSET(inst); 724 return 0; 725 } 726 727 if ((inst & 0xe000) == 0xa000) { 728 regs->pc += SH_PC_12BIT_OFFSET(inst); 729 return 0; 730 } 731 732 if ((inst & 0xf0df) == 0x0003) { 733 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4; 734 return 0; 735 } 736 737 if ((inst & 0xf0df) == 0x400b) { 738 regs->pc = regs->regs[(inst & 0x0f00) >> 8]; 739 return 0; 740 } 741 742 if ((inst & 0xffff) == 0x000b) { 743 regs->pc = regs->pr; 744 return 0; 745 } 746 747 return 1; 748 } 749 #endif 750 751 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5, 752 unsigned long r6, unsigned long r7, 753 struct pt_regs __regs) 754 { 755 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); 756 unsigned long error_code; 757 struct task_struct *tsk = current; 758 #ifdef CONFIG_SH_FPU_EMU 759 unsigned short inst = 0; 760 761 get_user(inst, (unsigned short *)regs->pc + 1); 762 if (!do_fpu_inst(inst, regs)) { 763 get_user(inst, (unsigned short *)regs->pc); 764 if (!emulate_branch(inst, regs)) 765 return; 766 /* fault in branch.*/ 767 } 768 /* not a FPU inst. */ 769 #endif 770 771 lookup_exception_vector(error_code); 772 773 local_irq_enable(); 774 CHK_REMOTE_DEBUG(regs); 775 force_sig(SIGILL, tsk); 776 die_if_no_fixup("illegal slot instruction", regs, error_code); 777 } 778 779 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5, 780 unsigned long r6, unsigned long r7, 781 struct pt_regs __regs) 782 { 783 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); 784 long ex; 785 786 lookup_exception_vector(ex); 787 die_if_kernel("exception", regs, ex); 788 } 789 790 #if defined(CONFIG_SH_STANDARD_BIOS) 791 void *gdb_vbr_vector; 792 793 static inline void __init gdb_vbr_init(void) 794 { 795 register unsigned long vbr; 796 797 /* 798 * Read the old value of the VBR register to initialise 799 * the vector through which debug and BIOS traps are 800 * delegated by the Linux trap handler. 801 */ 802 asm volatile("stc vbr, %0" : "=r" (vbr)); 803 804 gdb_vbr_vector = (void *)(vbr + 0x100); 805 printk("Setting GDB trap vector to 0x%08lx\n", 806 (unsigned long)gdb_vbr_vector); 807 } 808 #endif 809 810 void __cpuinit per_cpu_trap_init(void) 811 { 812 extern void *vbr_base; 813 814 #ifdef CONFIG_SH_STANDARD_BIOS 815 if (raw_smp_processor_id() == 0) 816 gdb_vbr_init(); 817 #endif 818 819 /* NOTE: The VBR value should be at P1 820 (or P2, virtural "fixed" address space). 821 It's definitely should not in physical address. */ 822 823 asm volatile("ldc %0, vbr" 824 : /* no output */ 825 : "r" (&vbr_base) 826 : "memory"); 827 } 828 829 void *set_exception_table_vec(unsigned int vec, void *handler) 830 { 831 extern void *exception_handling_table[]; 832 void *old_handler; 833 834 old_handler = exception_handling_table[vec]; 835 exception_handling_table[vec] = handler; 836 return old_handler; 837 } 838 839 extern asmlinkage void address_error_handler(unsigned long r4, unsigned long r5, 840 unsigned long r6, unsigned long r7, 841 struct pt_regs __regs); 842 843 void __init trap_init(void) 844 { 845 set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst); 846 set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst); 847 848 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \ 849 defined(CONFIG_SH_FPU_EMU) 850 /* 851 * For SH-4 lacking an FPU, treat floating point instructions as 852 * reserved. They'll be handled in the math-emu case, or faulted on 853 * otherwise. 854 */ 855 set_exception_table_evt(0x800, do_reserved_inst); 856 set_exception_table_evt(0x820, do_illegal_slot_inst); 857 #elif defined(CONFIG_SH_FPU) 858 #ifdef CONFIG_CPU_SUBTYPE_SHX3 859 set_exception_table_evt(0xd80, do_fpu_state_restore); 860 set_exception_table_evt(0xda0, do_fpu_state_restore); 861 #else 862 set_exception_table_evt(0x800, do_fpu_state_restore); 863 set_exception_table_evt(0x820, do_fpu_state_restore); 864 #endif 865 #endif 866 867 #ifdef CONFIG_CPU_SH2 868 set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_handler); 869 #endif 870 #ifdef CONFIG_CPU_SH2A 871 set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error); 872 set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error); 873 #endif 874 875 /* Setup VBR for boot cpu */ 876 per_cpu_trap_init(); 877 } 878 879 #ifdef CONFIG_BUG 880 void handle_BUG(struct pt_regs *regs) 881 { 882 enum bug_trap_type tt; 883 tt = report_bug(regs->pc, regs); 884 if (tt == BUG_TRAP_TYPE_WARN) { 885 regs->pc += 2; 886 return; 887 } 888 889 die("Kernel BUG", regs, TRAPA_BUG_OPCODE & 0xff); 890 } 891 892 int is_valid_bugaddr(unsigned long addr) 893 { 894 return addr >= PAGE_OFFSET; 895 } 896 #endif 897 898 void show_trace(struct task_struct *tsk, unsigned long *sp, 899 struct pt_regs *regs) 900 { 901 unsigned long addr; 902 903 if (regs && user_mode(regs)) 904 return; 905 906 printk("\nCall trace: "); 907 #ifdef CONFIG_KALLSYMS 908 printk("\n"); 909 #endif 910 911 while (!kstack_end(sp)) { 912 addr = *sp++; 913 if (kernel_text_address(addr)) 914 print_ip_sym(addr); 915 } 916 917 printk("\n"); 918 919 if (!tsk) 920 tsk = current; 921 922 debug_show_held_locks(tsk); 923 } 924 925 void show_stack(struct task_struct *tsk, unsigned long *sp) 926 { 927 unsigned long stack; 928 929 if (!tsk) 930 tsk = current; 931 if (tsk == current) 932 sp = (unsigned long *)current_stack_pointer; 933 else 934 sp = (unsigned long *)tsk->thread.sp; 935 936 stack = (unsigned long)sp; 937 dump_mem("Stack: ", stack, THREAD_SIZE + 938 (unsigned long)task_stack_page(tsk)); 939 show_trace(tsk, sp, NULL); 940 } 941 942 void dump_stack(void) 943 { 944 show_stack(NULL, NULL); 945 } 946 EXPORT_SYMBOL(dump_stack); 947