1 /* 2 * arch/sh/kernel/time.c 3 * 4 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka 5 * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org> 6 * Copyright (C) 2002, 2003, 2004 Paul Mundt 7 * Copyright (C) 2002 M. R. Brown <mrbrown@linux-sh.org> 8 * 9 * Some code taken from i386 version. 10 * Copyright (C) 1991, 1992, 1995 Linus Torvalds 11 */ 12 13 #include <linux/config.h> 14 #include <linux/errno.h> 15 #include <linux/module.h> 16 #include <linux/sched.h> 17 #include <linux/kernel.h> 18 #include <linux/param.h> 19 #include <linux/string.h> 20 #include <linux/mm.h> 21 #include <linux/interrupt.h> 22 #include <linux/time.h> 23 #include <linux/delay.h> 24 #include <linux/init.h> 25 #include <linux/smp.h> 26 #include <linux/profile.h> 27 28 #include <asm/processor.h> 29 #include <asm/uaccess.h> 30 #include <asm/io.h> 31 #include <asm/irq.h> 32 #include <asm/delay.h> 33 #include <asm/machvec.h> 34 #include <asm/rtc.h> 35 #include <asm/freq.h> 36 #include <asm/cpu/timer.h> 37 #ifdef CONFIG_SH_KGDB 38 #include <asm/kgdb.h> 39 #endif 40 41 #include <linux/timex.h> 42 #include <linux/irq.h> 43 44 #define TMU_TOCR_INIT 0x00 45 #define TMU0_TCR_INIT 0x0020 46 #define TMU_TSTR_INIT 1 47 48 #define TMU0_TCR_CALIB 0x0000 49 50 #ifdef CONFIG_CPU_SUBTYPE_ST40STB1 51 #define CLOCKGEN_MEMCLKCR 0xbb040038 52 #define MEMCLKCR_RATIO_MASK 0x7 53 #endif /* CONFIG_CPU_SUBTYPE_ST40STB1 */ 54 55 extern unsigned long wall_jiffies; 56 #define TICK_SIZE (tick_nsec / 1000) 57 DEFINE_SPINLOCK(tmu0_lock); 58 59 u64 jiffies_64 = INITIAL_JIFFIES; 60 61 EXPORT_SYMBOL(jiffies_64); 62 63 /* XXX: Can we initialize this in a routine somewhere? Dreamcast doesn't want 64 * these routines anywhere... */ 65 #ifdef CONFIG_SH_RTC 66 void (*rtc_get_time)(struct timespec *) = sh_rtc_gettimeofday; 67 int (*rtc_set_time)(const time_t) = sh_rtc_settimeofday; 68 #else 69 void (*rtc_get_time)(struct timespec *); 70 int (*rtc_set_time)(const time_t); 71 #endif 72 73 #if defined(CONFIG_CPU_SUBTYPE_SH7300) 74 static int md_table[] = { 1, 2, 3, 4, 6, 8, 12 }; 75 #endif 76 #if defined(CONFIG_CPU_SH3) 77 static int stc_multipliers[] = { 1, 2, 3, 4, 6, 1, 1, 1 }; 78 static int stc_values[] = { 0, 1, 4, 2, 5, 0, 0, 0 }; 79 #define bfc_divisors stc_multipliers 80 #define bfc_values stc_values 81 static int ifc_divisors[] = { 1, 2, 3, 4, 1, 1, 1, 1 }; 82 static int ifc_values[] = { 0, 1, 4, 2, 0, 0, 0, 0 }; 83 static int pfc_divisors[] = { 1, 2, 3, 4, 6, 1, 1, 1 }; 84 static int pfc_values[] = { 0, 1, 4, 2, 5, 0, 0, 0 }; 85 #elif defined(CONFIG_CPU_SH4) 86 #if defined(CONFIG_CPU_SUBTYPE_SH73180) 87 static int ifc_divisors[] = { 1, 2, 3, 4, 6, 8, 12, 16 }; 88 static int ifc_values[] = { 0, 1, 2, 3, 4, 5, 6, 7 }; 89 #define bfc_divisors ifc_divisors /* Same */ 90 #define bfc_values ifc_values 91 #define pfc_divisors ifc_divisors /* Same */ 92 #define pfc_values ifc_values 93 #else 94 static int ifc_divisors[] = { 1, 2, 3, 4, 6, 8, 1, 1 }; 95 static int ifc_values[] = { 0, 1, 2, 3, 0, 4, 0, 5 }; 96 #define bfc_divisors ifc_divisors /* Same */ 97 #define bfc_values ifc_values 98 static int pfc_divisors[] = { 2, 3, 4, 6, 8, 2, 2, 2 }; 99 static int pfc_values[] = { 0, 0, 1, 2, 0, 3, 0, 4 }; 100 #endif 101 #else 102 #error "Unknown ifc/bfc/pfc/stc values for this processor" 103 #endif 104 105 /* 106 * Scheduler clock - returns current time in nanosec units. 107 */ 108 unsigned long long sched_clock(void) 109 { 110 return (unsigned long long)jiffies * (1000000000 / HZ); 111 } 112 113 static unsigned long do_gettimeoffset(void) 114 { 115 int count; 116 unsigned long flags; 117 118 static int count_p = 0x7fffffff; /* for the first call after boot */ 119 static unsigned long jiffies_p = 0; 120 121 /* 122 * cache volatile jiffies temporarily; we have IRQs turned off. 123 */ 124 unsigned long jiffies_t; 125 126 spin_lock_irqsave(&tmu0_lock, flags); 127 /* timer count may underflow right here */ 128 count = ctrl_inl(TMU0_TCNT); /* read the latched count */ 129 130 jiffies_t = jiffies; 131 132 /* 133 * avoiding timer inconsistencies (they are rare, but they happen)... 134 * there is one kind of problem that must be avoided here: 135 * 1. the timer counter underflows 136 */ 137 138 if( jiffies_t == jiffies_p ) { 139 if( count > count_p ) { 140 /* the nutcase */ 141 142 if(ctrl_inw(TMU0_TCR) & 0x100) { /* Check UNF bit */ 143 /* 144 * We cannot detect lost timer interrupts ... 145 * well, that's why we call them lost, don't we? :) 146 * [hmm, on the Pentium and Alpha we can ... sort of] 147 */ 148 count -= LATCH; 149 } else { 150 printk("do_slow_gettimeoffset(): hardware timer problem?\n"); 151 } 152 } 153 } else 154 jiffies_p = jiffies_t; 155 156 count_p = count; 157 spin_unlock_irqrestore(&tmu0_lock, flags); 158 159 count = ((LATCH-1) - count) * TICK_SIZE; 160 count = (count + LATCH/2) / LATCH; 161 162 return count; 163 } 164 165 void do_gettimeofday(struct timeval *tv) 166 { 167 unsigned long seq; 168 unsigned long usec, sec; 169 unsigned long lost; 170 171 do { 172 seq = read_seqbegin(&xtime_lock); 173 usec = do_gettimeoffset(); 174 175 lost = jiffies - wall_jiffies; 176 if (lost) 177 usec += lost * (1000000 / HZ); 178 179 sec = xtime.tv_sec; 180 usec += xtime.tv_nsec / 1000; 181 } while (read_seqretry(&xtime_lock, seq)); 182 183 while (usec >= 1000000) { 184 usec -= 1000000; 185 sec++; 186 } 187 188 tv->tv_sec = sec; 189 tv->tv_usec = usec; 190 } 191 192 EXPORT_SYMBOL(do_gettimeofday); 193 194 int do_settimeofday(struct timespec *tv) 195 { 196 time_t wtm_sec, sec = tv->tv_sec; 197 long wtm_nsec, nsec = tv->tv_nsec; 198 199 if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC) 200 return -EINVAL; 201 202 write_seqlock_irq(&xtime_lock); 203 /* 204 * This is revolting. We need to set "xtime" correctly. However, the 205 * value in this location is the value at the most recent update of 206 * wall time. Discover what correction gettimeofday() would have 207 * made, and then undo it! 208 */ 209 nsec -= 1000 * (do_gettimeoffset() + 210 (jiffies - wall_jiffies) * (1000000 / HZ)); 211 212 wtm_sec = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec); 213 wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec); 214 215 set_normalized_timespec(&xtime, sec, nsec); 216 set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); 217 218 time_adjust = 0; /* stop active adjtime() */ 219 time_status |= STA_UNSYNC; 220 time_maxerror = NTP_PHASE_LIMIT; 221 time_esterror = NTP_PHASE_LIMIT; 222 write_sequnlock_irq(&xtime_lock); 223 clock_was_set(); 224 225 return 0; 226 } 227 228 EXPORT_SYMBOL(do_settimeofday); 229 230 /* last time the RTC clock got updated */ 231 static long last_rtc_update; 232 233 /* 234 * timer_interrupt() needs to keep up the real-time clock, 235 * as well as call the "do_timer()" routine every clocktick 236 */ 237 static inline void do_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) 238 { 239 do_timer(regs); 240 #ifndef CONFIG_SMP 241 update_process_times(user_mode(regs)); 242 #endif 243 profile_tick(CPU_PROFILING, regs); 244 245 #ifdef CONFIG_HEARTBEAT 246 if (sh_mv.mv_heartbeat != NULL) 247 sh_mv.mv_heartbeat(); 248 #endif 249 250 /* 251 * If we have an externally synchronized Linux clock, then update 252 * RTC clock accordingly every ~11 minutes. Set_rtc_mmss() has to be 253 * called as close as possible to 500 ms before the new second starts. 254 */ 255 if ((time_status & STA_UNSYNC) == 0 && 256 xtime.tv_sec > last_rtc_update + 660 && 257 (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 && 258 (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) { 259 if (rtc_set_time(xtime.tv_sec) == 0) 260 last_rtc_update = xtime.tv_sec; 261 else 262 last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */ 263 } 264 } 265 266 /* 267 * This is the same as the above, except we _also_ save the current 268 * Time Stamp Counter value at the time of the timer interrupt, so that 269 * we later on can estimate the time of day more exactly. 270 */ 271 static irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) 272 { 273 unsigned long timer_status; 274 275 /* Clear UNF bit */ 276 timer_status = ctrl_inw(TMU0_TCR); 277 timer_status &= ~0x100; 278 ctrl_outw(timer_status, TMU0_TCR); 279 280 /* 281 * Here we are in the timer irq handler. We just have irqs locally 282 * disabled but we don't know if the timer_bh is running on the other 283 * CPU. We need to avoid to SMP race with it. NOTE: we don' t need 284 * the irq version of write_lock because as just said we have irq 285 * locally disabled. -arca 286 */ 287 write_seqlock(&xtime_lock); 288 do_timer_interrupt(irq, NULL, regs); 289 write_sequnlock(&xtime_lock); 290 291 return IRQ_HANDLED; 292 } 293 294 /* 295 * Hah! We'll see if this works (switching from usecs to nsecs). 296 */ 297 static unsigned int __init get_timer_frequency(void) 298 { 299 u32 freq; 300 struct timespec ts1, ts2; 301 unsigned long diff_nsec; 302 unsigned long factor; 303 304 /* Setup the timer: We don't want to generate interrupts, just 305 * have it count down at its natural rate. 306 */ 307 ctrl_outb(0, TMU_TSTR); 308 #if !defined(CONFIG_CPU_SUBTYPE_SH7300) 309 ctrl_outb(TMU_TOCR_INIT, TMU_TOCR); 310 #endif 311 ctrl_outw(TMU0_TCR_CALIB, TMU0_TCR); 312 ctrl_outl(0xffffffff, TMU0_TCOR); 313 ctrl_outl(0xffffffff, TMU0_TCNT); 314 315 rtc_get_time(&ts2); 316 317 do { 318 rtc_get_time(&ts1); 319 } while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec); 320 321 /* actually start the timer */ 322 ctrl_outb(TMU_TSTR_INIT, TMU_TSTR); 323 324 do { 325 rtc_get_time(&ts2); 326 } while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec); 327 328 freq = 0xffffffff - ctrl_inl(TMU0_TCNT); 329 if (ts2.tv_nsec < ts1.tv_nsec) { 330 ts2.tv_nsec += 1000000000; 331 ts2.tv_sec--; 332 } 333 334 diff_nsec = (ts2.tv_sec - ts1.tv_sec) * 1000000000 + (ts2.tv_nsec - ts1.tv_nsec); 335 336 /* this should work well if the RTC has a precision of n Hz, where 337 * n is an integer. I don't think we have to worry about the other 338 * cases. */ 339 factor = (1000000000 + diff_nsec/2) / diff_nsec; 340 341 if (factor * diff_nsec > 1100000000 || 342 factor * diff_nsec < 900000000) 343 panic("weird RTC (diff_nsec %ld)", diff_nsec); 344 345 return freq * factor; 346 } 347 348 void (*board_time_init)(void); 349 void (*board_timer_setup)(struct irqaction *irq); 350 351 static unsigned int sh_pclk_freq __initdata = CONFIG_SH_PCLK_FREQ; 352 353 static int __init sh_pclk_setup(char *str) 354 { 355 unsigned int freq; 356 357 if (get_option(&str, &freq)) 358 sh_pclk_freq = freq; 359 360 return 1; 361 } 362 __setup("sh_pclk=", sh_pclk_setup); 363 364 static struct irqaction irq0 = { timer_interrupt, SA_INTERRUPT, CPU_MASK_NONE, "timer", NULL, NULL}; 365 366 void get_current_frequency_divisors(unsigned int *ifc, unsigned int *bfc, unsigned int *pfc) 367 { 368 unsigned int frqcr = ctrl_inw(FRQCR); 369 370 #if defined(CONFIG_CPU_SH3) 371 #if defined(CONFIG_CPU_SUBTYPE_SH7300) 372 *ifc = md_table[((frqcr & 0x0070) >> 4)]; 373 *bfc = md_table[((frqcr & 0x0700) >> 8)]; 374 *pfc = md_table[frqcr & 0x0007]; 375 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) 376 *bfc = stc_multipliers[(frqcr & 0x0300) >> 8]; 377 *ifc = ifc_divisors[(frqcr & 0x0030) >> 4]; 378 *pfc = pfc_divisors[frqcr & 0x0003]; 379 #else 380 unsigned int tmp; 381 382 tmp = (frqcr & 0x8000) >> 13; 383 tmp |= (frqcr & 0x0030) >> 4; 384 *bfc = stc_multipliers[tmp]; 385 tmp = (frqcr & 0x4000) >> 12; 386 tmp |= (frqcr & 0x000c) >> 2; 387 *ifc = ifc_divisors[tmp]; 388 tmp = (frqcr & 0x2000) >> 11; 389 tmp |= frqcr & 0x0003; 390 *pfc = pfc_divisors[tmp]; 391 #endif 392 #elif defined(CONFIG_CPU_SH4) 393 #if defined(CONFIG_CPU_SUBTYPE_SH73180) 394 *ifc = ifc_divisors[(frqcr>> 20) & 0x0007]; 395 *bfc = bfc_divisors[(frqcr>> 12) & 0x0007]; 396 *pfc = pfc_divisors[frqcr & 0x0007]; 397 #else 398 *ifc = ifc_divisors[(frqcr >> 6) & 0x0007]; 399 *bfc = bfc_divisors[(frqcr >> 3) & 0x0007]; 400 *pfc = pfc_divisors[frqcr & 0x0007]; 401 #endif 402 #endif 403 } 404 405 /* 406 * This bit of ugliness builds up accessor routines to get at both 407 * the divisors and the physical values. 408 */ 409 #define _FREQ_TABLE(x) \ 410 unsigned int get_##x##_divisor(unsigned int value) \ 411 { return x##_divisors[value]; } \ 412 \ 413 unsigned int get_##x##_value(unsigned int divisor) \ 414 { return x##_values[(divisor - 1)]; } 415 416 _FREQ_TABLE(ifc); 417 _FREQ_TABLE(bfc); 418 _FREQ_TABLE(pfc); 419 420 #ifdef CONFIG_CPU_SUBTYPE_ST40STB1 421 422 /* 423 * The ST40 divisors are totally different so we set the cpu data 424 * clocks using a different algorithm 425 * 426 * I've just plugged this from the 2.4 code 427 * - Alex Bennee <kernel-hacker@bennee.com> 428 */ 429 #define CCN_PVR_CHIP_SHIFT 24 430 #define CCN_PVR_CHIP_MASK 0xff 431 #define CCN_PVR_CHIP_ST40STB1 0x4 432 433 434 struct frqcr_data { 435 unsigned short frqcr; 436 437 struct { 438 unsigned char multiplier; 439 unsigned char divisor; 440 } factor[3]; 441 }; 442 443 static struct frqcr_data st40_frqcr_table[] = { 444 { 0x000, {{1,1}, {1,1}, {1,2}}}, 445 { 0x002, {{1,1}, {1,1}, {1,4}}}, 446 { 0x004, {{1,1}, {1,1}, {1,8}}}, 447 { 0x008, {{1,1}, {1,2}, {1,2}}}, 448 { 0x00A, {{1,1}, {1,2}, {1,4}}}, 449 { 0x00C, {{1,1}, {1,2}, {1,8}}}, 450 { 0x011, {{1,1}, {2,3}, {1,6}}}, 451 { 0x013, {{1,1}, {2,3}, {1,3}}}, 452 { 0x01A, {{1,1}, {1,2}, {1,4}}}, 453 { 0x01C, {{1,1}, {1,2}, {1,8}}}, 454 { 0x023, {{1,1}, {2,3}, {1,3}}}, 455 { 0x02C, {{1,1}, {1,2}, {1,8}}}, 456 { 0x048, {{1,2}, {1,2}, {1,4}}}, 457 { 0x04A, {{1,2}, {1,2}, {1,6}}}, 458 { 0x04C, {{1,2}, {1,2}, {1,8}}}, 459 { 0x05A, {{1,2}, {1,3}, {1,6}}}, 460 { 0x05C, {{1,2}, {1,3}, {1,6}}}, 461 { 0x063, {{1,2}, {1,4}, {1,4}}}, 462 { 0x06C, {{1,2}, {1,4}, {1,8}}}, 463 { 0x091, {{1,3}, {1,3}, {1,6}}}, 464 { 0x093, {{1,3}, {1,3}, {1,6}}}, 465 { 0x0A3, {{1,3}, {1,6}, {1,6}}}, 466 { 0x0DA, {{1,4}, {1,4}, {1,8}}}, 467 { 0x0DC, {{1,4}, {1,4}, {1,8}}}, 468 { 0x0EC, {{1,4}, {1,8}, {1,8}}}, 469 { 0x123, {{1,4}, {1,4}, {1,8}}}, 470 { 0x16C, {{1,4}, {1,8}, {1,8}}}, 471 }; 472 473 struct memclk_data { 474 unsigned char multiplier; 475 unsigned char divisor; 476 }; 477 478 static struct memclk_data st40_memclk_table[8] = { 479 {1,1}, // 000 480 {1,2}, // 001 481 {1,3}, // 010 482 {2,3}, // 011 483 {1,4}, // 100 484 {1,6}, // 101 485 {1,8}, // 110 486 {1,8} // 111 487 }; 488 489 static void st40_specific_time_init(unsigned int module_clock, unsigned short frqcr) 490 { 491 unsigned int cpu_clock, master_clock, bus_clock, memory_clock; 492 struct frqcr_data *d; 493 int a; 494 unsigned long memclkcr; 495 struct memclk_data *e; 496 497 for (a = 0; a < ARRAY_SIZE(st40_frqcr_table); a++) { 498 d = &st40_frqcr_table[a]; 499 500 if (d->frqcr == (frqcr & 0x1ff)) 501 break; 502 } 503 504 if (a == ARRAY_SIZE(st40_frqcr_table)) { 505 d = st40_frqcr_table; 506 507 printk("ERROR: Unrecognised FRQCR value (0x%x), " 508 "using default multipliers\n", frqcr); 509 } 510 511 memclkcr = ctrl_inl(CLOCKGEN_MEMCLKCR); 512 e = &st40_memclk_table[memclkcr & MEMCLKCR_RATIO_MASK]; 513 514 printk(KERN_INFO "Clock multipliers: CPU: %d/%d Bus: %d/%d " 515 "Mem: %d/%d Periph: %d/%d\n", 516 d->factor[0].multiplier, d->factor[0].divisor, 517 d->factor[1].multiplier, d->factor[1].divisor, 518 e->multiplier, e->divisor, 519 d->factor[2].multiplier, d->factor[2].divisor); 520 521 master_clock = module_clock * d->factor[2].divisor 522 / d->factor[2].multiplier; 523 bus_clock = master_clock * d->factor[1].multiplier 524 / d->factor[1].divisor; 525 memory_clock = master_clock * e->multiplier 526 / e->divisor; 527 cpu_clock = master_clock * d->factor[0].multiplier 528 / d->factor[0].divisor; 529 530 current_cpu_data.cpu_clock = cpu_clock; 531 current_cpu_data.master_clock = master_clock; 532 current_cpu_data.bus_clock = bus_clock; 533 current_cpu_data.memory_clock = memory_clock; 534 current_cpu_data.module_clock = module_clock; 535 } 536 #endif 537 538 void __init time_init(void) 539 { 540 unsigned int timer_freq = 0; 541 unsigned int ifc, pfc, bfc; 542 unsigned long interval; 543 #ifdef CONFIG_CPU_SUBTYPE_ST40STB1 544 unsigned long pvr; 545 unsigned short frqcr; 546 #endif 547 548 if (board_time_init) 549 board_time_init(); 550 551 /* 552 * If we don't have an RTC (such as with the SH7300), don't attempt to 553 * probe the timer frequency. Rely on an either hardcoded peripheral 554 * clock value, or on the sh_pclk command line option. Note that we 555 * still need to have CONFIG_SH_PCLK_FREQ set in order for things like 556 * CLOCK_TICK_RATE to be sane. 557 */ 558 current_cpu_data.module_clock = sh_pclk_freq; 559 560 #ifdef CONFIG_SH_PCLK_CALC 561 /* XXX: Switch this over to a more generic test. */ 562 { 563 unsigned int freq; 564 565 /* 566 * If we've specified a peripheral clock frequency, and we have 567 * an RTC, compare it against the autodetected value. Complain 568 * if there's a mismatch. 569 */ 570 timer_freq = get_timer_frequency(); 571 freq = timer_freq * 4; 572 573 if (sh_pclk_freq && (sh_pclk_freq/100*99 > freq || sh_pclk_freq/100*101 < freq)) { 574 printk(KERN_NOTICE "Calculated peripheral clock value " 575 "%d differs from sh_pclk value %d, fixing..\n", 576 freq, sh_pclk_freq); 577 current_cpu_data.module_clock = freq; 578 } 579 } 580 #endif 581 582 #ifdef CONFIG_CPU_SUBTYPE_ST40STB1 583 /* XXX: Update ST40 code to use board_time_init() */ 584 pvr = ctrl_inl(CCN_PVR); 585 frqcr = ctrl_inw(FRQCR); 586 printk("time.c ST40 Probe: PVR %08lx, FRQCR %04hx\n", pvr, frqcr); 587 588 if (((pvr >> CCN_PVR_CHIP_SHIFT) & CCN_PVR_CHIP_MASK) == CCN_PVR_CHIP_ST40STB1) 589 st40_specific_time_init(current_cpu_data.module_clock, frqcr); 590 else 591 #endif 592 get_current_frequency_divisors(&ifc, &bfc, &pfc); 593 594 if (rtc_get_time) { 595 rtc_get_time(&xtime); 596 } else { 597 xtime.tv_sec = mktime(2000, 1, 1, 0, 0, 0); 598 xtime.tv_nsec = 0; 599 } 600 601 set_normalized_timespec(&wall_to_monotonic, 602 -xtime.tv_sec, -xtime.tv_nsec); 603 604 if (board_timer_setup) { 605 board_timer_setup(&irq0); 606 } else { 607 setup_irq(TIMER_IRQ, &irq0); 608 } 609 610 /* 611 * for ST40 chips the current_cpu_data should already be set 612 * so not having valid pfc/bfc/ifc shouldn't be a problem 613 */ 614 if (!current_cpu_data.master_clock) 615 current_cpu_data.master_clock = current_cpu_data.module_clock * pfc; 616 if (!current_cpu_data.bus_clock) 617 current_cpu_data.bus_clock = current_cpu_data.master_clock / bfc; 618 if (!current_cpu_data.cpu_clock) 619 current_cpu_data.cpu_clock = current_cpu_data.master_clock / ifc; 620 621 printk("CPU clock: %d.%02dMHz\n", 622 (current_cpu_data.cpu_clock / 1000000), 623 (current_cpu_data.cpu_clock % 1000000)/10000); 624 printk("Bus clock: %d.%02dMHz\n", 625 (current_cpu_data.bus_clock / 1000000), 626 (current_cpu_data.bus_clock % 1000000)/10000); 627 #ifdef CONFIG_CPU_SUBTYPE_ST40STB1 628 printk("Memory clock: %d.%02dMHz\n", 629 (current_cpu_data.memory_clock / 1000000), 630 (current_cpu_data.memory_clock % 1000000)/10000); 631 #endif 632 printk("Module clock: %d.%02dMHz\n", 633 (current_cpu_data.module_clock / 1000000), 634 (current_cpu_data.module_clock % 1000000)/10000); 635 636 interval = (current_cpu_data.module_clock/4 + HZ/2) / HZ; 637 638 printk("Interval = %ld\n", interval); 639 640 /* Start TMU0 */ 641 ctrl_outb(0, TMU_TSTR); 642 #if !defined(CONFIG_CPU_SUBTYPE_SH7300) 643 ctrl_outb(TMU_TOCR_INIT, TMU_TOCR); 644 #endif 645 ctrl_outw(TMU0_TCR_INIT, TMU0_TCR); 646 ctrl_outl(interval, TMU0_TCOR); 647 ctrl_outl(interval, TMU0_TCNT); 648 ctrl_outb(TMU_TSTR_INIT, TMU_TSTR); 649 650 #if defined(CONFIG_SH_KGDB) 651 /* 652 * Set up kgdb as requested. We do it here because the serial 653 * init uses the timer vars we just set up for figuring baud. 654 */ 655 kgdb_init(); 656 #endif 657 } 658