1/* $Id: head.S,v 1.7 2003/09/01 17:58:19 lethal Exp $ 2 * 3 * arch/sh/kernel/head.S 4 * 5 * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 * 11 * Head.S contains the SH exception handlers and startup code. 12 */ 13#include <linux/linkage.h> 14#include <asm/thread_info.h> 15 16#ifdef CONFIG_CPU_SH4A 17#define SYNCO() synco 18 19#define PREFI(label, reg) \ 20 mov.l label, reg; \ 21 prefi @reg 22#else 23#define SYNCO() 24#define PREFI(label, reg) 25#endif 26 27 .section .empty_zero_page, "aw" 28ENTRY(empty_zero_page) 29 .long 1 /* MOUNT_ROOT_RDONLY */ 30 .long 0 /* RAMDISK_FLAGS */ 31 .long 0x0200 /* ORIG_ROOT_DEV */ 32 .long 1 /* LOADER_TYPE */ 33 .long 0x00000000 /* INITRD_START */ 34 .long 0x00000000 /* INITRD_SIZE */ 35#ifdef CONFIG_32BIT 36 .long 0x53453f00 + 32 /* "SE?" = 32 bit */ 37#else 38 .long 0x53453f00 + 29 /* "SE?" = 29 bit */ 39#endif 401: 41 .skip PAGE_SIZE - empty_zero_page - 1b 42 43 .section .text.head, "ax" 44 45/* 46 * Condition at the entry of _stext: 47 * 48 * BSC has already been initialized. 49 * INTC may or may not be initialized. 50 * VBR may or may not be initialized. 51 * MMU may or may not be initialized. 52 * Cache may or may not be initialized. 53 * Hardware (including on-chip modules) may or may not be initialized. 54 * 55 */ 56ENTRY(_stext) 57 ! Initialize Status Register 58 mov.l 1f, r0 ! MD=1, RB=0, BL=0, IMASK=0xF 59 ldc r0, sr 60 ! Initialize global interrupt mask 61#ifdef CONFIG_CPU_HAS_SR_RB 62 mov #0, r0 63 ldc r0, r6_bank 64#endif 65 66 /* 67 * Prefetch if possible to reduce cache miss penalty. 68 * 69 * We do this early on for SH-4A as a micro-optimization, 70 * as later on we will have speculative execution enabled 71 * and this will become less of an issue. 72 */ 73 PREFI(5f, r0) 74 PREFI(6f, r0) 75 76 ! 77 mov.l 2f, r0 78 mov r0, r15 ! Set initial r15 (stack pointer) 79#ifdef CONFIG_CPU_HAS_SR_RB 80 mov.l 7f, r0 81 ldc r0, r7_bank ! ... and initial thread_info 82#endif 83 84#ifndef CONFIG_SH_NO_BSS_INIT 85 /* 86 * Don't clear BSS if running on slow platforms such as an RTL simulation, 87 * remote memory via SHdebug link, etc. For these the memory can be guaranteed 88 * to be all zero on boot anyway. 89 */ 90 ! Clear BSS area 91#ifdef CONFIG_SMP 92 mov.l 3f, r0 93 cmp/eq #0, r0 ! skip clear if set to zero 94 bt 10f 95#endif 96 97 mov.l 3f, r1 98 add #4, r1 99 mov.l 4f, r2 100 mov #0, r0 1019: cmp/hs r2, r1 102 bf/s 9b ! while (r1 < r2) 103 mov.l r0,@-r2 104 10510: 106#endif 107 108 ! Additional CPU initialization 109 mov.l 6f, r0 110 jsr @r0 111 nop 112 113 SYNCO() ! Wait for pending instructions.. 114 115 ! Start kernel 116 mov.l 5f, r0 117 jmp @r0 118 nop 119 120 .balign 4 121#if defined(CONFIG_CPU_SH2) 1221: .long 0x000000F0 ! IMASK=0xF 123#else 1241: .long 0x400080F0 ! MD=1, RB=0, BL=0, FD=1, IMASK=0xF 125#endif 126ENTRY(stack_start) 1272: .long init_thread_union+THREAD_SIZE 1283: .long __bss_start 1294: .long _end 1305: .long start_kernel 1316: .long sh_cpu_init 1327: .long init_thread_union 133