1 /*
2  * SH7786 Setup
3  *
4  * Copyright (C) 2009 - 2011  Renesas Solutions Corp.
5  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6  * Paul Mundt <paul.mundt@renesas.com>
7  *
8  * Based on SH7785 Setup
9  *
10  *  Copyright (C) 2007  Paul Mundt
11  *
12  * This file is subject to the terms and conditions of the GNU General Public
13  * License.  See the file "COPYING" in the main directory of this archive
14  * for more details.
15  */
16 #include <linux/platform_device.h>
17 #include <linux/init.h>
18 #include <linux/serial.h>
19 #include <linux/serial_sci.h>
20 #include <linux/io.h>
21 #include <linux/mm.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/sh_timer.h>
24 #include <linux/sh_dma.h>
25 #include <linux/sh_intc.h>
26 #include <cpu/dma-register.h>
27 #include <asm/mmzone.h>
28 
29 static struct plat_sci_port scif0_platform_data = {
30 	.mapbase	= 0xffea0000,
31 	.flags		= UPF_BOOT_AUTOCONF,
32 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
33 	.scbrr_algo_id	= SCBRR_ALGO_1,
34 	.type		= PORT_SCIF,
35 	.irqs		= { evt2irq(0x700),
36 			    evt2irq(0x720),
37 			    evt2irq(0x760),
38 			    evt2irq(0x740) },
39 	.regtype	= SCIx_SH4_SCIF_FIFODATA_REGTYPE,
40 };
41 
42 static struct platform_device scif0_device = {
43 	.name		= "sh-sci",
44 	.id		= 0,
45 	.dev		= {
46 		.platform_data	= &scif0_platform_data,
47 	},
48 };
49 
50 /*
51  * The rest of these all have multiplexed IRQs
52  */
53 static struct plat_sci_port scif1_platform_data = {
54 	.mapbase	= 0xffeb0000,
55 	.flags		= UPF_BOOT_AUTOCONF,
56 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
57 	.scbrr_algo_id	= SCBRR_ALGO_1,
58 	.type		= PORT_SCIF,
59 	.irqs		= SCIx_IRQ_MUXED(evt2irq(0x780)),
60 	.regtype	= SCIx_SH4_SCIF_FIFODATA_REGTYPE,
61 };
62 
63 static struct platform_device scif1_device = {
64 	.name		= "sh-sci",
65 	.id		= 1,
66 	.dev		= {
67 		.platform_data	= &scif1_platform_data,
68 	},
69 };
70 
71 static struct plat_sci_port scif2_platform_data = {
72 	.mapbase	= 0xffec0000,
73 	.flags		= UPF_BOOT_AUTOCONF,
74 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
75 	.scbrr_algo_id	= SCBRR_ALGO_1,
76 	.type		= PORT_SCIF,
77 	.irqs		= SCIx_IRQ_MUXED(evt2irq(0x840)),
78 	.regtype	= SCIx_SH4_SCIF_FIFODATA_REGTYPE,
79 };
80 
81 static struct platform_device scif2_device = {
82 	.name		= "sh-sci",
83 	.id		= 2,
84 	.dev		= {
85 		.platform_data	= &scif2_platform_data,
86 	},
87 };
88 
89 static struct plat_sci_port scif3_platform_data = {
90 	.mapbase	= 0xffed0000,
91 	.flags		= UPF_BOOT_AUTOCONF,
92 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
93 	.scbrr_algo_id	= SCBRR_ALGO_1,
94 	.type		= PORT_SCIF,
95 	.irqs		= SCIx_IRQ_MUXED(evt2irq(0x860)),
96 	.regtype	= SCIx_SH4_SCIF_FIFODATA_REGTYPE,
97 };
98 
99 static struct platform_device scif3_device = {
100 	.name		= "sh-sci",
101 	.id		= 3,
102 	.dev		= {
103 		.platform_data	= &scif3_platform_data,
104 	},
105 };
106 
107 static struct plat_sci_port scif4_platform_data = {
108 	.mapbase	= 0xffee0000,
109 	.flags		= UPF_BOOT_AUTOCONF,
110 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
111 	.scbrr_algo_id	= SCBRR_ALGO_1,
112 	.type		= PORT_SCIF,
113 	.irqs		= SCIx_IRQ_MUXED(evt2irq(0x880)),
114 	.regtype	= SCIx_SH4_SCIF_FIFODATA_REGTYPE,
115 };
116 
117 static struct platform_device scif4_device = {
118 	.name		= "sh-sci",
119 	.id		= 4,
120 	.dev		= {
121 		.platform_data	= &scif4_platform_data,
122 	},
123 };
124 
125 static struct plat_sci_port scif5_platform_data = {
126 	.mapbase	= 0xffef0000,
127 	.flags		= UPF_BOOT_AUTOCONF,
128 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
129 	.scbrr_algo_id	= SCBRR_ALGO_1,
130 	.type		= PORT_SCIF,
131 	.irqs		= SCIx_IRQ_MUXED(evt2irq(0x8a0)),
132 	.regtype	= SCIx_SH4_SCIF_FIFODATA_REGTYPE,
133 };
134 
135 static struct platform_device scif5_device = {
136 	.name		= "sh-sci",
137 	.id		= 5,
138 	.dev		= {
139 		.platform_data	= &scif5_platform_data,
140 	},
141 };
142 
143 static struct sh_timer_config tmu0_platform_data = {
144 	.channel_offset = 0x04,
145 	.timer_bit = 0,
146 	.clockevent_rating = 200,
147 };
148 
149 static struct resource tmu0_resources[] = {
150 	[0] = {
151 		.start	= 0xffd80008,
152 		.end	= 0xffd80013,
153 		.flags	= IORESOURCE_MEM,
154 	},
155 	[1] = {
156 		.start	= evt2irq(0x400),
157 		.flags	= IORESOURCE_IRQ,
158 	},
159 };
160 
161 static struct platform_device tmu0_device = {
162 	.name		= "sh_tmu",
163 	.id		= 0,
164 	.dev = {
165 		.platform_data	= &tmu0_platform_data,
166 	},
167 	.resource	= tmu0_resources,
168 	.num_resources	= ARRAY_SIZE(tmu0_resources),
169 };
170 
171 static struct sh_timer_config tmu1_platform_data = {
172 	.channel_offset = 0x10,
173 	.timer_bit = 1,
174 	.clocksource_rating = 200,
175 };
176 
177 static struct resource tmu1_resources[] = {
178 	[0] = {
179 		.start	= 0xffd80014,
180 		.end	= 0xffd8001f,
181 		.flags	= IORESOURCE_MEM,
182 	},
183 	[1] = {
184 		.start	= evt2irq(0x420),
185 		.flags	= IORESOURCE_IRQ,
186 	},
187 };
188 
189 static struct platform_device tmu1_device = {
190 	.name		= "sh_tmu",
191 	.id		= 1,
192 	.dev = {
193 		.platform_data	= &tmu1_platform_data,
194 	},
195 	.resource	= tmu1_resources,
196 	.num_resources	= ARRAY_SIZE(tmu1_resources),
197 };
198 
199 static struct sh_timer_config tmu2_platform_data = {
200 	.channel_offset = 0x1c,
201 	.timer_bit = 2,
202 };
203 
204 static struct resource tmu2_resources[] = {
205 	[0] = {
206 		.start	= 0xffd80020,
207 		.end	= 0xffd8002f,
208 		.flags	= IORESOURCE_MEM,
209 	},
210 	[1] = {
211 		.start	= evt2irq(0x440),
212 		.flags	= IORESOURCE_IRQ,
213 	},
214 };
215 
216 static struct platform_device tmu2_device = {
217 	.name		= "sh_tmu",
218 	.id		= 2,
219 	.dev = {
220 		.platform_data	= &tmu2_platform_data,
221 	},
222 	.resource	= tmu2_resources,
223 	.num_resources	= ARRAY_SIZE(tmu2_resources),
224 };
225 
226 static struct sh_timer_config tmu3_platform_data = {
227 	.channel_offset = 0x04,
228 	.timer_bit = 0,
229 };
230 
231 static struct resource tmu3_resources[] = {
232 	[0] = {
233 		.start	= 0xffda0008,
234 		.end	= 0xffda0013,
235 		.flags	= IORESOURCE_MEM,
236 	},
237 	[1] = {
238 		.start	= evt2irq(0x480),
239 		.flags	= IORESOURCE_IRQ,
240 	},
241 };
242 
243 static struct platform_device tmu3_device = {
244 	.name		= "sh_tmu",
245 	.id		= 3,
246 	.dev = {
247 		.platform_data	= &tmu3_platform_data,
248 	},
249 	.resource	= tmu3_resources,
250 	.num_resources	= ARRAY_SIZE(tmu3_resources),
251 };
252 
253 static struct sh_timer_config tmu4_platform_data = {
254 	.channel_offset = 0x10,
255 	.timer_bit = 1,
256 };
257 
258 static struct resource tmu4_resources[] = {
259 	[0] = {
260 		.start	= 0xffda0014,
261 		.end	= 0xffda001f,
262 		.flags	= IORESOURCE_MEM,
263 	},
264 	[1] = {
265 		.start	= evt2irq(0x4a0),
266 		.flags	= IORESOURCE_IRQ,
267 	},
268 };
269 
270 static struct platform_device tmu4_device = {
271 	.name		= "sh_tmu",
272 	.id		= 4,
273 	.dev = {
274 		.platform_data	= &tmu4_platform_data,
275 	},
276 	.resource	= tmu4_resources,
277 	.num_resources	= ARRAY_SIZE(tmu4_resources),
278 };
279 
280 static struct sh_timer_config tmu5_platform_data = {
281 	.channel_offset = 0x1c,
282 	.timer_bit = 2,
283 };
284 
285 static struct resource tmu5_resources[] = {
286 	[0] = {
287 		.start	= 0xffda0020,
288 		.end	= 0xffda002b,
289 		.flags	= IORESOURCE_MEM,
290 	},
291 	[1] = {
292 		.start	= evt2irq(0x4c0),
293 		.flags	= IORESOURCE_IRQ,
294 	},
295 };
296 
297 static struct platform_device tmu5_device = {
298 	.name		= "sh_tmu",
299 	.id		= 5,
300 	.dev = {
301 		.platform_data	= &tmu5_platform_data,
302 	},
303 	.resource	= tmu5_resources,
304 	.num_resources	= ARRAY_SIZE(tmu5_resources),
305 };
306 
307 static struct sh_timer_config tmu6_platform_data = {
308 	.channel_offset = 0x04,
309 	.timer_bit = 0,
310 };
311 
312 static struct resource tmu6_resources[] = {
313 	[0] = {
314 		.start	= 0xffdc0008,
315 		.end	= 0xffdc0013,
316 		.flags	= IORESOURCE_MEM,
317 	},
318 	[1] = {
319 		.start	= evt2irq(0x7a0),
320 		.flags	= IORESOURCE_IRQ,
321 	},
322 };
323 
324 static struct platform_device tmu6_device = {
325 	.name		= "sh_tmu",
326 	.id		= 6,
327 	.dev = {
328 		.platform_data	= &tmu6_platform_data,
329 	},
330 	.resource	= tmu6_resources,
331 	.num_resources	= ARRAY_SIZE(tmu6_resources),
332 };
333 
334 static struct sh_timer_config tmu7_platform_data = {
335 	.channel_offset = 0x10,
336 	.timer_bit = 1,
337 };
338 
339 static struct resource tmu7_resources[] = {
340 	[0] = {
341 		.start	= 0xffdc0014,
342 		.end	= 0xffdc001f,
343 		.flags	= IORESOURCE_MEM,
344 	},
345 	[1] = {
346 		.start	= evt2irq(0x7a0),
347 		.flags	= IORESOURCE_IRQ,
348 	},
349 };
350 
351 static struct platform_device tmu7_device = {
352 	.name		= "sh_tmu",
353 	.id		= 7,
354 	.dev = {
355 		.platform_data	= &tmu7_platform_data,
356 	},
357 	.resource	= tmu7_resources,
358 	.num_resources	= ARRAY_SIZE(tmu7_resources),
359 };
360 
361 static struct sh_timer_config tmu8_platform_data = {
362 	.channel_offset = 0x1c,
363 	.timer_bit = 2,
364 };
365 
366 static struct resource tmu8_resources[] = {
367 	[0] = {
368 		.start	= 0xffdc0020,
369 		.end	= 0xffdc002b,
370 		.flags	= IORESOURCE_MEM,
371 	},
372 	[1] = {
373 		.start	= evt2irq(0x7a0),
374 		.flags	= IORESOURCE_IRQ,
375 	},
376 };
377 
378 static struct platform_device tmu8_device = {
379 	.name		= "sh_tmu",
380 	.id		= 8,
381 	.dev = {
382 		.platform_data	= &tmu8_platform_data,
383 	},
384 	.resource	= tmu8_resources,
385 	.num_resources	= ARRAY_SIZE(tmu8_resources),
386 };
387 
388 static struct sh_timer_config tmu9_platform_data = {
389 	.channel_offset = 0x04,
390 	.timer_bit = 0,
391 };
392 
393 static struct resource tmu9_resources[] = {
394 	[0] = {
395 		.start	= 0xffde0008,
396 		.end	= 0xffde0013,
397 		.flags	= IORESOURCE_MEM,
398 	},
399 	[1] = {
400 		.start	= evt2irq(0x7c0),
401 		.flags	= IORESOURCE_IRQ,
402 	},
403 };
404 
405 static struct platform_device tmu9_device = {
406 	.name		= "sh_tmu",
407 	.id		= 9,
408 	.dev = {
409 		.platform_data	= &tmu9_platform_data,
410 	},
411 	.resource	= tmu9_resources,
412 	.num_resources	= ARRAY_SIZE(tmu9_resources),
413 };
414 
415 static struct sh_timer_config tmu10_platform_data = {
416 	.channel_offset = 0x10,
417 	.timer_bit = 1,
418 };
419 
420 static struct resource tmu10_resources[] = {
421 	[0] = {
422 		.start	= 0xffde0014,
423 		.end	= 0xffde001f,
424 		.flags	= IORESOURCE_MEM,
425 	},
426 	[1] = {
427 		.start	= evt2irq(0x7c0),
428 		.flags	= IORESOURCE_IRQ,
429 	},
430 };
431 
432 static struct platform_device tmu10_device = {
433 	.name		= "sh_tmu",
434 	.id		= 10,
435 	.dev = {
436 		.platform_data	= &tmu10_platform_data,
437 	},
438 	.resource	= tmu10_resources,
439 	.num_resources	= ARRAY_SIZE(tmu10_resources),
440 };
441 
442 static struct sh_timer_config tmu11_platform_data = {
443 	.channel_offset = 0x1c,
444 	.timer_bit = 2,
445 };
446 
447 static struct resource tmu11_resources[] = {
448 	[0] = {
449 		.start	= 0xffde0020,
450 		.end	= 0xffde002b,
451 		.flags	= IORESOURCE_MEM,
452 	},
453 	[1] = {
454 		.start	= evt2irq(0x7c0),
455 		.flags	= IORESOURCE_IRQ,
456 	},
457 };
458 
459 static struct platform_device tmu11_device = {
460 	.name		= "sh_tmu",
461 	.id		= 11,
462 	.dev = {
463 		.platform_data	= &tmu11_platform_data,
464 	},
465 	.resource	= tmu11_resources,
466 	.num_resources	= ARRAY_SIZE(tmu11_resources),
467 };
468 
469 static const struct sh_dmae_channel dmac0_channels[] = {
470 	{
471 		.offset = 0,
472 		.dmars = 0,
473 		.dmars_bit = 0,
474 	}, {
475 		.offset = 0x10,
476 		.dmars = 0,
477 		.dmars_bit = 8,
478 	}, {
479 		.offset = 0x20,
480 		.dmars = 4,
481 		.dmars_bit = 0,
482 	}, {
483 		.offset = 0x30,
484 		.dmars = 4,
485 		.dmars_bit = 8,
486 	}, {
487 		.offset = 0x50,
488 		.dmars = 8,
489 		.dmars_bit = 0,
490 	}, {
491 		.offset = 0x60,
492 		.dmars = 8,
493 		.dmars_bit = 8,
494 	}
495 };
496 
497 static const unsigned int ts_shift[] = TS_SHIFT;
498 
499 static struct sh_dmae_pdata dma0_platform_data = {
500 	.channel	= dmac0_channels,
501 	.channel_num	= ARRAY_SIZE(dmac0_channels),
502 	.ts_low_shift	= CHCR_TS_LOW_SHIFT,
503 	.ts_low_mask	= CHCR_TS_LOW_MASK,
504 	.ts_high_shift	= CHCR_TS_HIGH_SHIFT,
505 	.ts_high_mask	= CHCR_TS_HIGH_MASK,
506 	.ts_shift	= ts_shift,
507 	.ts_shift_num	= ARRAY_SIZE(ts_shift),
508 	.dmaor_init	= DMAOR_INIT,
509 };
510 
511 /* Resource order important! */
512 static struct resource dmac0_resources[] = {
513 	{
514 		/* Channel registers and DMAOR */
515 		.start	= 0xfe008020,
516 		.end	= 0xfe00808f,
517 		.flags	= IORESOURCE_MEM,
518 	}, {
519 		/* DMARSx */
520 		.start	= 0xfe009000,
521 		.end	= 0xfe00900b,
522 		.flags	= IORESOURCE_MEM,
523 	}, {
524 		.name	= "error_irq",
525 		.start	= evt2irq(0x5c0),
526 		.end	= evt2irq(0x5c0),
527 		.flags	= IORESOURCE_IRQ,
528 	}, {
529 		/* IRQ for channels 0-5 */
530 		.start	= evt2irq(0x500),
531 		.end	= evt2irq(0x5a0),
532 		.flags	= IORESOURCE_IRQ,
533 	},
534 };
535 
536 static struct platform_device dma0_device = {
537 	.name		= "sh-dma-engine",
538 	.id		= 0,
539 	.resource	= dmac0_resources,
540 	.num_resources	= ARRAY_SIZE(dmac0_resources),
541 	.dev		= {
542 		.platform_data	= &dma0_platform_data,
543 	},
544 };
545 
546 #define USB_EHCI_START 0xffe70000
547 #define USB_OHCI_START 0xffe70400
548 
549 static struct resource usb_ehci_resources[] = {
550 	[0] = {
551 		.start	= USB_EHCI_START,
552 		.end	= USB_EHCI_START + 0x3ff,
553 		.flags	= IORESOURCE_MEM,
554 	},
555 	[1] = {
556 		.start	= evt2irq(0xba0),
557 		.end	= evt2irq(0xba0),
558 		.flags	= IORESOURCE_IRQ,
559 	},
560 };
561 
562 static struct platform_device usb_ehci_device = {
563 	.name		= "sh_ehci",
564 	.id		= -1,
565 	.dev = {
566 		.dma_mask		= &usb_ehci_device.dev.coherent_dma_mask,
567 		.coherent_dma_mask	= DMA_BIT_MASK(32),
568 	},
569 	.num_resources	= ARRAY_SIZE(usb_ehci_resources),
570 	.resource	= usb_ehci_resources,
571 };
572 
573 static struct resource usb_ohci_resources[] = {
574 	[0] = {
575 		.start	= USB_OHCI_START,
576 		.end	= USB_OHCI_START + 0x3ff,
577 		.flags	= IORESOURCE_MEM,
578 	},
579 	[1] = {
580 		.start	= evt2irq(0xba0),
581 		.end	= evt2irq(0xba0),
582 		.flags	= IORESOURCE_IRQ,
583 	},
584 };
585 
586 static struct platform_device usb_ohci_device = {
587 	.name		= "sh_ohci",
588 	.id		= -1,
589 	.dev = {
590 		.dma_mask		= &usb_ohci_device.dev.coherent_dma_mask,
591 		.coherent_dma_mask	= DMA_BIT_MASK(32),
592 	},
593 	.num_resources	= ARRAY_SIZE(usb_ohci_resources),
594 	.resource	= usb_ohci_resources,
595 };
596 
597 static struct platform_device *sh7786_early_devices[] __initdata = {
598 	&scif0_device,
599 	&scif1_device,
600 	&scif2_device,
601 	&scif3_device,
602 	&scif4_device,
603 	&scif5_device,
604 	&tmu0_device,
605 	&tmu1_device,
606 	&tmu2_device,
607 	&tmu3_device,
608 	&tmu4_device,
609 	&tmu5_device,
610 	&tmu6_device,
611 	&tmu7_device,
612 	&tmu8_device,
613 	&tmu9_device,
614 	&tmu10_device,
615 	&tmu11_device,
616 };
617 
618 static struct platform_device *sh7786_devices[] __initdata = {
619 	&dma0_device,
620 	&usb_ehci_device,
621 	&usb_ohci_device,
622 };
623 
624 /*
625  * Please call this function if your platform board
626  * use external clock for USB
627  * */
628 #define USBCTL0		0xffe70858
629 #define CLOCK_MODE_MASK 0xffffff7f
630 #define EXT_CLOCK_MODE  0x00000080
631 
632 void __init sh7786_usb_use_exclock(void)
633 {
634 	u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
635 	__raw_writel(val | EXT_CLOCK_MODE, USBCTL0);
636 }
637 
638 #define USBINITREG1	0xffe70094
639 #define USBINITREG2	0xffe7009c
640 #define USBINITVAL1	0x00ff0040
641 #define USBINITVAL2	0x00000001
642 
643 #define USBPCTL1	0xffe70804
644 #define USBST		0xffe70808
645 #define PHY_ENB		0x00000001
646 #define PLL_ENB		0x00000002
647 #define PHY_RST		0x00000004
648 #define ACT_PLL_STATUS	0xc0000000
649 
650 static void __init sh7786_usb_setup(void)
651 {
652 	int i = 1000000;
653 
654 	/*
655 	 * USB initial settings
656 	 *
657 	 * The following settings are necessary
658 	 * for using the USB modules.
659 	 *
660 	 * see "USB Initial Settings" for detail
661 	 */
662 	__raw_writel(USBINITVAL1, USBINITREG1);
663 	__raw_writel(USBINITVAL2, USBINITREG2);
664 
665 	/*
666 	 * Set the PHY and PLL enable bit
667 	 */
668 	__raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
669 	while (i--) {
670 		if (ACT_PLL_STATUS == (__raw_readl(USBST) & ACT_PLL_STATUS)) {
671 			/* Set the PHY RST bit */
672 			__raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
673 			printk(KERN_INFO "sh7786 usb setup done\n");
674 			break;
675 		}
676 		cpu_relax();
677 	}
678 }
679 
680 enum {
681 	UNUSED = 0,
682 
683 	/* interrupt sources */
684 	IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
685 	IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
686 	IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
687 	IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
688 
689 	IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
690 	IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
691 	IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
692 	IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
693 
694 	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
695 	WDT,
696 	TMU0_0, TMU0_1, TMU0_2, TMU0_3,
697 	TMU1_0, TMU1_1, TMU1_2,
698 	DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
699 	HUDI1, HUDI0,
700 	DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
701 	HPB_0, HPB_1, HPB_2,
702 	SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
703 	SCIF1,
704 	TMU2, TMU3,
705 	SCIF2, SCIF3, SCIF4, SCIF5,
706 	Eth_0, Eth_1,
707 	PCIeC0_0, PCIeC0_1, PCIeC0_2,
708 	PCIeC1_0, PCIeC1_1, PCIeC1_2,
709 	USB,
710 	I2C0, I2C1,
711 	DU,
712 	SSI0, SSI1, SSI2, SSI3,
713 	PCIeC2_0, PCIeC2_1, PCIeC2_2,
714 	HAC0, HAC1,
715 	FLCTL,
716 	HSPI,
717 	GPIO0, GPIO1,
718 	Thermal,
719 	INTICI0, INTICI1, INTICI2, INTICI3,
720 	INTICI4, INTICI5, INTICI6, INTICI7,
721 
722 	/* Muxed sub-events */
723 	TXI1, BRI1, RXI1, ERI1,
724 };
725 
726 static struct intc_vect sh7786_vectors[] __initdata = {
727 	INTC_VECT(WDT, 0x3e0),
728 	INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
729 	INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
730 	INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
731 	INTC_VECT(TMU1_2, 0x4c0),
732 	INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
733 	INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
734 	INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
735 	INTC_VECT(DMAC0_6, 0x5c0),
736 	INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
737 	INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
738 	INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
739 	INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
740 	INTC_VECT(HPB_2, 0x6e0),
741 	INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
742 	INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
743 	INTC_VECT(SCIF1, 0x780),
744 	INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
745 	INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
746 	INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
747 	INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
748 	INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
749 	INTC_VECT(PCIeC0_2, 0xb20),
750 	INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
751 	INTC_VECT(PCIeC1_2, 0xb80),
752 	INTC_VECT(USB, 0xba0),
753 	INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
754 	INTC_VECT(DU, 0xd00),
755 	INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
756 	INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
757 	INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
758 	INTC_VECT(PCIeC2_2, 0xde0),
759 	INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
760 	INTC_VECT(FLCTL, 0xe40),
761 	INTC_VECT(HSPI, 0xe80),
762 	INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
763 	INTC_VECT(Thermal, 0xee0),
764 	INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
765 	INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
766 	INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
767 	INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
768 };
769 
770 #define CnINTMSK0	0xfe410030
771 #define CnINTMSK1	0xfe410040
772 #define CnINTMSKCLR0	0xfe410050
773 #define CnINTMSKCLR1	0xfe410060
774 #define CnINT2MSKR0	0xfe410a20
775 #define CnINT2MSKR1	0xfe410a24
776 #define CnINT2MSKR2	0xfe410a28
777 #define CnINT2MSKR3	0xfe410a2c
778 #define CnINT2MSKCR0	0xfe410a30
779 #define CnINT2MSKCR1	0xfe410a34
780 #define CnINT2MSKCR2	0xfe410a38
781 #define CnINT2MSKCR3	0xfe410a3c
782 #define INTMSK2		0xfe410068
783 #define INTMSKCLR2	0xfe41006c
784 
785 #define INTDISTCR0	0xfe4100b0
786 #define INTDISTCR1	0xfe4100b4
787 #define INT2DISTCR0	0xfe410900
788 #define INT2DISTCR1	0xfe410904
789 #define INT2DISTCR2	0xfe410908
790 #define INT2DISTCR3	0xfe41090c
791 
792 static struct intc_mask_reg sh7786_mask_registers[] __initdata = {
793 	{ CnINTMSK0, CnINTMSKCLR0, 32,
794 	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 },
795 	    INTC_SMP_BALANCING(INTDISTCR0) },
796 	{ INTMSK2, INTMSKCLR2, 32,
797 	  { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
798 	    IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
799 	    IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
800 	    IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
801 	    IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
802 	    IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
803 	    IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
804 	    IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
805 	{ CnINT2MSKR0, CnINT2MSKCR0 , 32,
806 	  { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
807 	    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT },
808 	    INTC_SMP_BALANCING(INT2DISTCR0) },
809 	{ CnINT2MSKR1, CnINT2MSKCR1, 32,
810 	  { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
811 	    DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
812 	    HUDI1, HUDI0,
813 	    DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
814 	    HPB_0, HPB_1, HPB_2,
815 	    SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
816 	    SCIF1,
817 	    TMU2, TMU3, 0, }, INTC_SMP_BALANCING(INT2DISTCR1) },
818 	{ CnINT2MSKR2, CnINT2MSKCR2, 32,
819 	  { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
820 	    Eth_0, Eth_1,
821 	    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
822 	    PCIeC0_0, PCIeC0_1, PCIeC0_2,
823 	    PCIeC1_0, PCIeC1_1, PCIeC1_2,
824 	    USB, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR2) },
825 	{ CnINT2MSKR3, CnINT2MSKCR3, 32,
826 	  { 0, 0, 0, 0, 0, 0,
827 	    I2C0, I2C1,
828 	    DU, SSI0, SSI1, SSI2, SSI3,
829 	    PCIeC2_0, PCIeC2_1, PCIeC2_2,
830 	    HAC0, HAC1,
831 	    FLCTL, 0,
832 	    HSPI, GPIO0, GPIO1, Thermal,
833 	    0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) },
834 };
835 
836 static struct intc_prio_reg sh7786_prio_registers[] __initdata = {
837 	{ 0xfe410010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
838 						 IRQ4, IRQ5, IRQ6, IRQ7 } },
839 	{ 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
840 	{ 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
841 						 TMU0_2, TMU0_3 } },
842 	{ 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
843 						 TMU1_2, 0 } },
844 	{ 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
845 						 DMAC0_2, DMAC0_3 } },
846 	{ 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
847 						 DMAC0_6, HUDI1 } },
848 	{ 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
849 						 DMAC1_1, DMAC1_2 } },
850 	{ 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
851 						 HPB_1, HPB_2 } },
852 	{ 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
853 						 SCIF0_2, SCIF0_3 } },
854 	{ 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
855 	{ 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
856 	{ 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
857 						  Eth_0, Eth_1 } },
858 	{ 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
859 	{ 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
860 	{ 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
861 	{ 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
862 	{ 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
863 						  PCIeC1_0, PCIeC1_1 } },
864 	{ 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
865 	{ 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
866 	{ 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
867 	{ 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
868 	{ 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
869 						  PCIeC2_1, PCIeC2_2 } },
870 	{ 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
871 	{ 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
872 						  GPIO1, Thermal } },
873 	{ 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
874 	{ 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
875 	{ 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
876 	  { INTICI7, INTICI6, INTICI5, INTICI4,
877 	    INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
878 };
879 
880 static struct intc_subgroup sh7786_subgroups[] __initdata = {
881 	{ 0xfe410c20, 32, SCIF1,
882 	  { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
883 	    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, TXI1, BRI1, RXI1, ERI1 } },
884 };
885 
886 static struct intc_desc sh7786_intc_desc __initdata = {
887 	.name		= "sh7786",
888 	.hw		= {
889 		.vectors	= sh7786_vectors,
890 		.nr_vectors	= ARRAY_SIZE(sh7786_vectors),
891 		.mask_regs	= sh7786_mask_registers,
892 		.nr_mask_regs	= ARRAY_SIZE(sh7786_mask_registers),
893 		.subgroups	= sh7786_subgroups,
894 		.nr_subgroups	= ARRAY_SIZE(sh7786_subgroups),
895 		.prio_regs	= sh7786_prio_registers,
896 		.nr_prio_regs	= ARRAY_SIZE(sh7786_prio_registers),
897 	},
898 };
899 
900 /* Support for external interrupt pins in IRQ mode */
901 static struct intc_vect vectors_irq0123[] __initdata = {
902 	INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
903 	INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
904 };
905 
906 static struct intc_vect vectors_irq4567[] __initdata = {
907 	INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
908 	INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
909 };
910 
911 static struct intc_sense_reg sh7786_sense_registers[] __initdata = {
912 	{ 0xfe41001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
913 					    IRQ4, IRQ5, IRQ6, IRQ7 } },
914 };
915 
916 static struct intc_mask_reg sh7786_ack_registers[] __initdata = {
917 	{ 0xfe410024, 0, 32, /* INTREQ */
918 	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
919 };
920 
921 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
922 			     vectors_irq0123, NULL, sh7786_mask_registers,
923 			     sh7786_prio_registers, sh7786_sense_registers,
924 			     sh7786_ack_registers);
925 
926 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
927 			     vectors_irq4567, NULL, sh7786_mask_registers,
928 			     sh7786_prio_registers, sh7786_sense_registers,
929 			     sh7786_ack_registers);
930 
931 /* External interrupt pins in IRL mode */
932 
933 static struct intc_vect vectors_irl0123[] __initdata = {
934 	INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
935 	INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
936 	INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
937 	INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
938 	INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
939 	INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
940 	INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
941 	INTC_VECT(IRL0_HHHL, 0x3c0),
942 };
943 
944 static struct intc_vect vectors_irl4567[] __initdata = {
945 	INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
946 	INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
947 	INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
948 	INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
949 	INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
950 	INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
951 	INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
952 	INTC_VECT(IRL4_HHHL, 0xac0),
953 };
954 
955 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
956 			 NULL, sh7786_mask_registers, NULL, NULL);
957 
958 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
959 			 NULL, sh7786_mask_registers, NULL, NULL);
960 
961 #define INTC_ICR0	0xfe410000
962 #define INTC_INTMSK0	CnINTMSK0
963 #define INTC_INTMSK1	CnINTMSK1
964 #define INTC_INTMSK2	INTMSK2
965 #define INTC_INTMSKCLR1	CnINTMSKCLR1
966 #define INTC_INTMSKCLR2	INTMSKCLR2
967 
968 void __init plat_irq_setup(void)
969 {
970 	/* disable IRQ3-0 + IRQ7-4 */
971 	__raw_writel(0xff000000, INTC_INTMSK0);
972 
973 	/* disable IRL3-0 + IRL7-4 */
974 	__raw_writel(0xc0000000, INTC_INTMSK1);
975 	__raw_writel(0xfffefffe, INTC_INTMSK2);
976 
977 	/* select IRL mode for IRL3-0 + IRL7-4 */
978 	__raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
979 
980 	register_intc_controller(&sh7786_intc_desc);
981 }
982 
983 void __init plat_irq_setup_pins(int mode)
984 {
985 	switch (mode) {
986 	case IRQ_MODE_IRQ7654:
987 		/* select IRQ mode for IRL7-4 */
988 		__raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
989 		register_intc_controller(&intc_desc_irq4567);
990 		break;
991 	case IRQ_MODE_IRQ3210:
992 		/* select IRQ mode for IRL3-0 */
993 		__raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
994 		register_intc_controller(&intc_desc_irq0123);
995 		break;
996 	case IRQ_MODE_IRL7654:
997 		/* enable IRL7-4 but don't provide any masking */
998 		__raw_writel(0x40000000, INTC_INTMSKCLR1);
999 		__raw_writel(0x0000fffe, INTC_INTMSKCLR2);
1000 		break;
1001 	case IRQ_MODE_IRL3210:
1002 		/* enable IRL0-3 but don't provide any masking */
1003 		__raw_writel(0x80000000, INTC_INTMSKCLR1);
1004 		__raw_writel(0xfffe0000, INTC_INTMSKCLR2);
1005 		break;
1006 	case IRQ_MODE_IRL7654_MASK:
1007 		/* enable IRL7-4 and mask using cpu intc controller */
1008 		__raw_writel(0x40000000, INTC_INTMSKCLR1);
1009 		register_intc_controller(&intc_desc_irl4567);
1010 		break;
1011 	case IRQ_MODE_IRL3210_MASK:
1012 		/* enable IRL0-3 and mask using cpu intc controller */
1013 		__raw_writel(0x80000000, INTC_INTMSKCLR1);
1014 		register_intc_controller(&intc_desc_irl0123);
1015 		break;
1016 	default:
1017 		BUG();
1018 	}
1019 }
1020 
1021 void __init plat_mem_setup(void)
1022 {
1023 }
1024 
1025 static int __init sh7786_devices_setup(void)
1026 {
1027 	int ret, irq;
1028 
1029 	sh7786_usb_setup();
1030 
1031 	/*
1032 	 * De-mux SCIF1 IRQs if possible
1033 	 */
1034 	irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1);
1035 	if (irq > 0) {
1036 		scif1_platform_data.irqs[SCIx_TXI_IRQ] = irq;
1037 		scif1_platform_data.irqs[SCIx_ERI_IRQ] =
1038 			intc_irq_lookup(sh7786_intc_desc.name, ERI1);
1039 		scif1_platform_data.irqs[SCIx_BRI_IRQ] =
1040 			intc_irq_lookup(sh7786_intc_desc.name, BRI1);
1041 		scif1_platform_data.irqs[SCIx_RXI_IRQ] =
1042 			intc_irq_lookup(sh7786_intc_desc.name, RXI1);
1043 	}
1044 
1045 	ret = platform_add_devices(sh7786_early_devices,
1046 				   ARRAY_SIZE(sh7786_early_devices));
1047 	if (unlikely(ret != 0))
1048 		return ret;
1049 
1050 	return platform_add_devices(sh7786_devices,
1051 				    ARRAY_SIZE(sh7786_devices));
1052 }
1053 arch_initcall(sh7786_devices_setup);
1054 
1055 void __init plat_early_device_setup(void)
1056 {
1057 	early_platform_add_devices(sh7786_early_devices,
1058 				   ARRAY_SIZE(sh7786_early_devices));
1059 }
1060