1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * SH7785 Setup
4  *
5  *  Copyright (C) 2007  Paul Mundt
6  */
7 #include <linux/platform_device.h>
8 #include <linux/init.h>
9 #include <linux/serial.h>
10 #include <linux/serial_sci.h>
11 #include <linux/io.h>
12 #include <linux/mm.h>
13 #include <linux/sh_dma.h>
14 #include <linux/sh_timer.h>
15 #include <linux/sh_intc.h>
16 #include <asm/mmzone.h>
17 #include <asm/platform_early.h>
18 #include <cpu/dma-register.h>
19 
20 static struct plat_sci_port scif0_platform_data = {
21 	.scscr		= SCSCR_REIE | SCSCR_CKE1,
22 	.type		= PORT_SCIF,
23 	.regtype	= SCIx_SH4_SCIF_FIFODATA_REGTYPE,
24 };
25 
26 static struct resource scif0_resources[] = {
27 	DEFINE_RES_MEM(0xffea0000, 0x100),
28 	DEFINE_RES_IRQ(evt2irq(0x700)),
29 };
30 
31 static struct platform_device scif0_device = {
32 	.name		= "sh-sci",
33 	.id		= 0,
34 	.resource	= scif0_resources,
35 	.num_resources	= ARRAY_SIZE(scif0_resources),
36 	.dev		= {
37 		.platform_data	= &scif0_platform_data,
38 	},
39 };
40 
41 static struct plat_sci_port scif1_platform_data = {
42 	.scscr		= SCSCR_REIE | SCSCR_CKE1,
43 	.type		= PORT_SCIF,
44 	.regtype	= SCIx_SH4_SCIF_FIFODATA_REGTYPE,
45 };
46 
47 static struct resource scif1_resources[] = {
48 	DEFINE_RES_MEM(0xffeb0000, 0x100),
49 	DEFINE_RES_IRQ(evt2irq(0x780)),
50 };
51 
52 static struct platform_device scif1_device = {
53 	.name		= "sh-sci",
54 	.id		= 1,
55 	.resource	= scif1_resources,
56 	.num_resources	= ARRAY_SIZE(scif1_resources),
57 	.dev		= {
58 		.platform_data	= &scif1_platform_data,
59 	},
60 };
61 
62 static struct plat_sci_port scif2_platform_data = {
63 	.scscr		= SCSCR_REIE | SCSCR_CKE1,
64 	.type		= PORT_SCIF,
65 	.regtype	= SCIx_SH4_SCIF_FIFODATA_REGTYPE,
66 };
67 
68 static struct resource scif2_resources[] = {
69 	DEFINE_RES_MEM(0xffec0000, 0x100),
70 	DEFINE_RES_IRQ(evt2irq(0x980)),
71 };
72 
73 static struct platform_device scif2_device = {
74 	.name		= "sh-sci",
75 	.id		= 2,
76 	.resource	= scif2_resources,
77 	.num_resources	= ARRAY_SIZE(scif2_resources),
78 	.dev		= {
79 		.platform_data	= &scif2_platform_data,
80 	},
81 };
82 
83 static struct plat_sci_port scif3_platform_data = {
84 	.scscr		= SCSCR_REIE | SCSCR_CKE1,
85 	.type		= PORT_SCIF,
86 	.regtype	= SCIx_SH4_SCIF_FIFODATA_REGTYPE,
87 };
88 
89 static struct resource scif3_resources[] = {
90 	DEFINE_RES_MEM(0xffed0000, 0x100),
91 	DEFINE_RES_IRQ(evt2irq(0x9a0)),
92 };
93 
94 static struct platform_device scif3_device = {
95 	.name		= "sh-sci",
96 	.id		= 3,
97 	.resource	= scif3_resources,
98 	.num_resources	= ARRAY_SIZE(scif3_resources),
99 	.dev		= {
100 		.platform_data	= &scif3_platform_data,
101 	},
102 };
103 
104 static struct plat_sci_port scif4_platform_data = {
105 	.scscr		= SCSCR_REIE | SCSCR_CKE1,
106 	.type		= PORT_SCIF,
107 	.regtype	= SCIx_SH4_SCIF_FIFODATA_REGTYPE,
108 };
109 
110 static struct resource scif4_resources[] = {
111 	DEFINE_RES_MEM(0xffee0000, 0x100),
112 	DEFINE_RES_IRQ(evt2irq(0x9c0)),
113 };
114 
115 static struct platform_device scif4_device = {
116 	.name		= "sh-sci",
117 	.id		= 4,
118 	.resource	= scif4_resources,
119 	.num_resources	= ARRAY_SIZE(scif4_resources),
120 	.dev		= {
121 		.platform_data	= &scif4_platform_data,
122 	},
123 };
124 
125 static struct plat_sci_port scif5_platform_data = {
126 	.scscr		= SCSCR_REIE | SCSCR_CKE1,
127 	.type		= PORT_SCIF,
128 	.regtype	= SCIx_SH4_SCIF_FIFODATA_REGTYPE,
129 };
130 
131 static struct resource scif5_resources[] = {
132 	DEFINE_RES_MEM(0xffef0000, 0x100),
133 	DEFINE_RES_IRQ(evt2irq(0x9e0)),
134 };
135 
136 static struct platform_device scif5_device = {
137 	.name		= "sh-sci",
138 	.id		= 5,
139 	.resource	= scif5_resources,
140 	.num_resources	= ARRAY_SIZE(scif5_resources),
141 	.dev		= {
142 		.platform_data	= &scif5_platform_data,
143 	},
144 };
145 
146 static struct sh_timer_config tmu0_platform_data = {
147 	.channels_mask = 7,
148 };
149 
150 static struct resource tmu0_resources[] = {
151 	DEFINE_RES_MEM(0xffd80000, 0x30),
152 	DEFINE_RES_IRQ(evt2irq(0x580)),
153 	DEFINE_RES_IRQ(evt2irq(0x5a0)),
154 	DEFINE_RES_IRQ(evt2irq(0x5c0)),
155 };
156 
157 static struct platform_device tmu0_device = {
158 	.name		= "sh-tmu",
159 	.id		= 0,
160 	.dev = {
161 		.platform_data	= &tmu0_platform_data,
162 	},
163 	.resource	= tmu0_resources,
164 	.num_resources	= ARRAY_SIZE(tmu0_resources),
165 };
166 
167 static struct sh_timer_config tmu1_platform_data = {
168 	.channels_mask = 7,
169 };
170 
171 static struct resource tmu1_resources[] = {
172 	DEFINE_RES_MEM(0xffdc0000, 0x2c),
173 	DEFINE_RES_IRQ(evt2irq(0xe00)),
174 	DEFINE_RES_IRQ(evt2irq(0xe20)),
175 	DEFINE_RES_IRQ(evt2irq(0xe40)),
176 };
177 
178 static struct platform_device tmu1_device = {
179 	.name		= "sh-tmu",
180 	.id		= 1,
181 	.dev = {
182 		.platform_data	= &tmu1_platform_data,
183 	},
184 	.resource	= tmu1_resources,
185 	.num_resources	= ARRAY_SIZE(tmu1_resources),
186 };
187 
188 /* DMA */
189 static const struct sh_dmae_channel sh7785_dmae0_channels[] = {
190 	{
191 		.offset = 0,
192 		.dmars = 0,
193 		.dmars_bit = 0,
194 	}, {
195 		.offset = 0x10,
196 		.dmars = 0,
197 		.dmars_bit = 8,
198 	}, {
199 		.offset = 0x20,
200 		.dmars = 4,
201 		.dmars_bit = 0,
202 	}, {
203 		.offset = 0x30,
204 		.dmars = 4,
205 		.dmars_bit = 8,
206 	}, {
207 		.offset = 0x50,
208 		.dmars = 8,
209 		.dmars_bit = 0,
210 	}, {
211 		.offset = 0x60,
212 		.dmars = 8,
213 		.dmars_bit = 8,
214 	}
215 };
216 
217 static const struct sh_dmae_channel sh7785_dmae1_channels[] = {
218 	{
219 		.offset = 0,
220 	}, {
221 		.offset = 0x10,
222 	}, {
223 		.offset = 0x20,
224 	}, {
225 		.offset = 0x30,
226 	}, {
227 		.offset = 0x50,
228 	}, {
229 		.offset = 0x60,
230 	}
231 };
232 
233 static const unsigned int ts_shift[] = TS_SHIFT;
234 
235 static struct sh_dmae_pdata dma0_platform_data = {
236 	.channel	= sh7785_dmae0_channels,
237 	.channel_num	= ARRAY_SIZE(sh7785_dmae0_channels),
238 	.ts_low_shift	= CHCR_TS_LOW_SHIFT,
239 	.ts_low_mask	= CHCR_TS_LOW_MASK,
240 	.ts_high_shift	= CHCR_TS_HIGH_SHIFT,
241 	.ts_high_mask	= CHCR_TS_HIGH_MASK,
242 	.ts_shift	= ts_shift,
243 	.ts_shift_num	= ARRAY_SIZE(ts_shift),
244 	.dmaor_init	= DMAOR_INIT,
245 };
246 
247 static struct sh_dmae_pdata dma1_platform_data = {
248 	.channel	= sh7785_dmae1_channels,
249 	.channel_num	= ARRAY_SIZE(sh7785_dmae1_channels),
250 	.ts_low_shift	= CHCR_TS_LOW_SHIFT,
251 	.ts_low_mask	= CHCR_TS_LOW_MASK,
252 	.ts_high_shift	= CHCR_TS_HIGH_SHIFT,
253 	.ts_high_mask	= CHCR_TS_HIGH_MASK,
254 	.ts_shift	= ts_shift,
255 	.ts_shift_num	= ARRAY_SIZE(ts_shift),
256 	.dmaor_init	= DMAOR_INIT,
257 };
258 
259 static struct resource sh7785_dmae0_resources[] = {
260 	[0] = {
261 		/* Channel registers and DMAOR */
262 		.start	= 0xfc808020,
263 		.end	= 0xfc80808f,
264 		.flags	= IORESOURCE_MEM,
265 	},
266 	[1] = {
267 		/* DMARSx */
268 		.start	= 0xfc809000,
269 		.end	= 0xfc80900b,
270 		.flags	= IORESOURCE_MEM,
271 	},
272 	{
273 		/*
274 		 * Real DMA error vector is 0x6e0, and channel
275 		 * vectors are 0x620-0x6c0
276 		 */
277 		.name	= "error_irq",
278 		.start	= evt2irq(0x620),
279 		.end	= evt2irq(0x620),
280 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
281 	},
282 };
283 
284 static struct resource sh7785_dmae1_resources[] = {
285 	[0] = {
286 		/* Channel registers and DMAOR */
287 		.start	= 0xfcc08020,
288 		.end	= 0xfcc0808f,
289 		.flags	= IORESOURCE_MEM,
290 	},
291 	/* DMAC1 has no DMARS */
292 	{
293 		/*
294 		 * Real DMA error vector is 0x940, and channel
295 		 * vectors are 0x880-0x920
296 		 */
297 		.name	= "error_irq",
298 		.start	= evt2irq(0x880),
299 		.end	= evt2irq(0x880),
300 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
301 	},
302 };
303 
304 static struct platform_device dma0_device = {
305 	.name           = "sh-dma-engine",
306 	.id             = 0,
307 	.resource	= sh7785_dmae0_resources,
308 	.num_resources	= ARRAY_SIZE(sh7785_dmae0_resources),
309 	.dev            = {
310 		.platform_data	= &dma0_platform_data,
311 	},
312 };
313 
314 static struct platform_device dma1_device = {
315 	.name		= "sh-dma-engine",
316 	.id		= 1,
317 	.resource	= sh7785_dmae1_resources,
318 	.num_resources	= ARRAY_SIZE(sh7785_dmae1_resources),
319 	.dev		= {
320 		.platform_data	= &dma1_platform_data,
321 	},
322 };
323 
324 static struct platform_device *sh7785_devices[] __initdata = {
325 	&scif0_device,
326 	&scif1_device,
327 	&scif2_device,
328 	&scif3_device,
329 	&scif4_device,
330 	&scif5_device,
331 	&tmu0_device,
332 	&tmu1_device,
333 	&dma0_device,
334 	&dma1_device,
335 };
336 
337 static int __init sh7785_devices_setup(void)
338 {
339 	return platform_add_devices(sh7785_devices,
340 				    ARRAY_SIZE(sh7785_devices));
341 }
342 arch_initcall(sh7785_devices_setup);
343 
344 static struct platform_device *sh7785_early_devices[] __initdata = {
345 	&scif0_device,
346 	&scif1_device,
347 	&scif2_device,
348 	&scif3_device,
349 	&scif4_device,
350 	&scif5_device,
351 	&tmu0_device,
352 	&tmu1_device,
353 };
354 
355 void __init plat_early_device_setup(void)
356 {
357 	sh_early_platform_add_devices(sh7785_early_devices,
358 				   ARRAY_SIZE(sh7785_early_devices));
359 }
360 
361 enum {
362 	UNUSED = 0,
363 
364 	/* interrupt sources */
365 
366 	IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
367 	IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
368 	IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
369 	IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
370 
371 	IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
372 	IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
373 	IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
374 	IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
375 
376 	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
377 	WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
378 	HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
379 	SCIF2, SCIF3, SCIF4, SCIF5,
380 	PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
381 	SIOF, MMCIF, DU, GDTA,
382 	TMU3, TMU4, TMU5,
383 	SSI0, SSI1,
384 	HAC0, HAC1,
385 	FLCTL, GPIO,
386 
387 	/* interrupt groups */
388 
389 	TMU012,	TMU345
390 };
391 
392 static struct intc_vect vectors[] __initdata = {
393 	INTC_VECT(WDT, 0x560),
394 	INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
395 	INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
396 	INTC_VECT(HUDI, 0x600),
397 	INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
398 	INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
399 	INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
400 	INTC_VECT(DMAC0, 0x6e0),
401 	INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
402 	INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
403 	INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
404 	INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
405 	INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
406 	INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
407 	INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
408 	INTC_VECT(DMAC1, 0x940),
409 	INTC_VECT(HSPI, 0x960),
410 	INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
411 	INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
412 	INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
413 	INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
414 	INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
415 	INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
416 	INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
417 	INTC_VECT(SIOF, 0xc00),
418 	INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
419 	INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
420 	INTC_VECT(DU, 0xd80),
421 	INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
422 	INTC_VECT(GDTA, 0xde0),
423 	INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
424 	INTC_VECT(TMU5, 0xe40),
425 	INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
426 	INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
427 	INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
428 	INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
429 	INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
430 	INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
431 };
432 
433 static struct intc_group groups[] __initdata = {
434 	INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
435 	INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
436 };
437 
438 static struct intc_mask_reg mask_registers[] __initdata = {
439 	{ 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
440 	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
441 
442 	{ 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
443 	  { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
444 	    IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
445 	    IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
446 	    IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
447 	    IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
448 	    IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
449 	    IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
450 	    IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
451 
452 	{ 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
453 	  { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
454 	    FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
455 	    PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
456 	    SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
457 };
458 
459 static struct intc_prio_reg prio_registers[] __initdata = {
460 	{ 0xffd00010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
461 						 IRQ4, IRQ5, IRQ6, IRQ7 } },
462 	{ 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
463 						 TMU2, TMU2_TICPI } },
464 	{ 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
465 	{ 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
466 						 SCIF2, SCIF3 } },
467 	{ 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
468 	{ 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
469 	{ 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
470 						 PCISERR, PCIINTA } },
471 	{ 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
472 						 PCIINTD, PCIC5 } },
473 	{ 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
474 	{ 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
475 	{ 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
476 };
477 
478 static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
479 			 mask_registers, prio_registers, NULL);
480 
481 /* Support for external interrupt pins in IRQ mode */
482 
483 static struct intc_vect vectors_irq0123[] __initdata = {
484 	INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
485 	INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
486 };
487 
488 static struct intc_vect vectors_irq4567[] __initdata = {
489 	INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
490 	INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
491 };
492 
493 static struct intc_sense_reg sense_registers[] __initdata = {
494 	{ 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
495 					    IRQ4, IRQ5, IRQ6, IRQ7 } },
496 };
497 
498 static struct intc_mask_reg ack_registers[] __initdata = {
499 	{ 0xffd00024, 0, 32, /* INTREQ */
500 	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
501 };
502 
503 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
504 			     vectors_irq0123, NULL, mask_registers,
505 			     prio_registers, sense_registers, ack_registers);
506 
507 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
508 			     vectors_irq4567, NULL, mask_registers,
509 			     prio_registers, sense_registers, ack_registers);
510 
511 /* External interrupt pins in IRL mode */
512 
513 static struct intc_vect vectors_irl0123[] __initdata = {
514 	INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
515 	INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
516 	INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
517 	INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
518 	INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
519 	INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
520 	INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
521 	INTC_VECT(IRL0_HHHL, 0x3c0),
522 };
523 
524 static struct intc_vect vectors_irl4567[] __initdata = {
525 	INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
526 	INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
527 	INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
528 	INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
529 	INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
530 	INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
531 	INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
532 	INTC_VECT(IRL4_HHHL, 0xcc0),
533 };
534 
535 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
536 			 NULL, mask_registers, NULL, NULL);
537 
538 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
539 			 NULL, mask_registers, NULL, NULL);
540 
541 #define INTC_ICR0	0xffd00000
542 #define INTC_INTMSK0	0xffd00044
543 #define INTC_INTMSK1	0xffd00048
544 #define INTC_INTMSK2	0xffd40080
545 #define INTC_INTMSKCLR1	0xffd00068
546 #define INTC_INTMSKCLR2	0xffd40084
547 
548 void __init plat_irq_setup(void)
549 {
550 	/* disable IRQ3-0 + IRQ7-4 */
551 	__raw_writel(0xff000000, INTC_INTMSK0);
552 
553 	/* disable IRL3-0 + IRL7-4 */
554 	__raw_writel(0xc0000000, INTC_INTMSK1);
555 	__raw_writel(0xfffefffe, INTC_INTMSK2);
556 
557 	/* select IRL mode for IRL3-0 + IRL7-4 */
558 	__raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
559 
560 	/* disable holding function, ie enable "SH-4 Mode" */
561 	__raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
562 
563 	register_intc_controller(&intc_desc);
564 }
565 
566 void __init plat_irq_setup_pins(int mode)
567 {
568 	switch (mode) {
569 	case IRQ_MODE_IRQ7654:
570 		/* select IRQ mode for IRL7-4 */
571 		__raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
572 		register_intc_controller(&intc_desc_irq4567);
573 		break;
574 	case IRQ_MODE_IRQ3210:
575 		/* select IRQ mode for IRL3-0 */
576 		__raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
577 		register_intc_controller(&intc_desc_irq0123);
578 		break;
579 	case IRQ_MODE_IRL7654:
580 		/* enable IRL7-4 but don't provide any masking */
581 		__raw_writel(0x40000000, INTC_INTMSKCLR1);
582 		__raw_writel(0x0000fffe, INTC_INTMSKCLR2);
583 		break;
584 	case IRQ_MODE_IRL3210:
585 		/* enable IRL0-3 but don't provide any masking */
586 		__raw_writel(0x80000000, INTC_INTMSKCLR1);
587 		__raw_writel(0xfffe0000, INTC_INTMSKCLR2);
588 		break;
589 	case IRQ_MODE_IRL7654_MASK:
590 		/* enable IRL7-4 and mask using cpu intc controller */
591 		__raw_writel(0x40000000, INTC_INTMSKCLR1);
592 		register_intc_controller(&intc_desc_irl4567);
593 		break;
594 	case IRQ_MODE_IRL3210_MASK:
595 		/* enable IRL0-3 and mask using cpu intc controller */
596 		__raw_writel(0x80000000, INTC_INTMSKCLR1);
597 		register_intc_controller(&intc_desc_irl0123);
598 		break;
599 	default:
600 		BUG();
601 	}
602 }
603 
604 void __init plat_mem_setup(void)
605 {
606 	/* Register the URAM space as Node 1 */
607 	setup_bootmem_node(1, 0xe55f0000, 0xe5610000);
608 }
609