1 /* 2 * SH7785 Setup 3 * 4 * Copyright (C) 2007 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/serial_sci.h> 14 #include <linux/io.h> 15 #include <linux/mm.h> 16 #include <linux/sh_dma.h> 17 #include <linux/sh_timer.h> 18 #include <asm/mmzone.h> 19 #include <cpu/dma-register.h> 20 21 static struct plat_sci_port scif0_platform_data = { 22 .mapbase = 0xffea0000, 23 .flags = UPF_BOOT_AUTOCONF, 24 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 25 .scbrr_algo_id = SCBRR_ALGO_1, 26 .type = PORT_SCIF, 27 .irqs = { 40, 40, 40, 40 }, 28 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 29 }; 30 31 static struct platform_device scif0_device = { 32 .name = "sh-sci", 33 .id = 0, 34 .dev = { 35 .platform_data = &scif0_platform_data, 36 }, 37 }; 38 39 static struct plat_sci_port scif1_platform_data = { 40 .mapbase = 0xffeb0000, 41 .flags = UPF_BOOT_AUTOCONF, 42 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 43 .scbrr_algo_id = SCBRR_ALGO_1, 44 .type = PORT_SCIF, 45 .irqs = { 44, 44, 44, 44 }, 46 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 47 }; 48 49 static struct platform_device scif1_device = { 50 .name = "sh-sci", 51 .id = 1, 52 .dev = { 53 .platform_data = &scif1_platform_data, 54 }, 55 }; 56 57 static struct plat_sci_port scif2_platform_data = { 58 .mapbase = 0xffec0000, 59 .flags = UPF_BOOT_AUTOCONF, 60 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 61 .scbrr_algo_id = SCBRR_ALGO_1, 62 .type = PORT_SCIF, 63 .irqs = { 60, 60, 60, 60 }, 64 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 65 }; 66 67 static struct platform_device scif2_device = { 68 .name = "sh-sci", 69 .id = 2, 70 .dev = { 71 .platform_data = &scif2_platform_data, 72 }, 73 }; 74 75 static struct plat_sci_port scif3_platform_data = { 76 .mapbase = 0xffed0000, 77 .flags = UPF_BOOT_AUTOCONF, 78 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 79 .scbrr_algo_id = SCBRR_ALGO_1, 80 .type = PORT_SCIF, 81 .irqs = { 61, 61, 61, 61 }, 82 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 83 }; 84 85 static struct platform_device scif3_device = { 86 .name = "sh-sci", 87 .id = 3, 88 .dev = { 89 .platform_data = &scif3_platform_data, 90 }, 91 }; 92 93 static struct plat_sci_port scif4_platform_data = { 94 .mapbase = 0xffee0000, 95 .flags = UPF_BOOT_AUTOCONF, 96 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 97 .scbrr_algo_id = SCBRR_ALGO_1, 98 .type = PORT_SCIF, 99 .irqs = { 62, 62, 62, 62 }, 100 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 101 }; 102 103 static struct platform_device scif4_device = { 104 .name = "sh-sci", 105 .id = 4, 106 .dev = { 107 .platform_data = &scif4_platform_data, 108 }, 109 }; 110 111 static struct plat_sci_port scif5_platform_data = { 112 .mapbase = 0xffef0000, 113 .flags = UPF_BOOT_AUTOCONF, 114 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 115 .scbrr_algo_id = SCBRR_ALGO_1, 116 .type = PORT_SCIF, 117 .irqs = { 63, 63, 63, 63 }, 118 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 119 }; 120 121 static struct platform_device scif5_device = { 122 .name = "sh-sci", 123 .id = 5, 124 .dev = { 125 .platform_data = &scif5_platform_data, 126 }, 127 }; 128 129 static struct sh_timer_config tmu0_platform_data = { 130 .channel_offset = 0x04, 131 .timer_bit = 0, 132 .clockevent_rating = 200, 133 }; 134 135 static struct resource tmu0_resources[] = { 136 [0] = { 137 .start = 0xffd80008, 138 .end = 0xffd80013, 139 .flags = IORESOURCE_MEM, 140 }, 141 [1] = { 142 .start = 28, 143 .flags = IORESOURCE_IRQ, 144 }, 145 }; 146 147 static struct platform_device tmu0_device = { 148 .name = "sh_tmu", 149 .id = 0, 150 .dev = { 151 .platform_data = &tmu0_platform_data, 152 }, 153 .resource = tmu0_resources, 154 .num_resources = ARRAY_SIZE(tmu0_resources), 155 }; 156 157 static struct sh_timer_config tmu1_platform_data = { 158 .channel_offset = 0x10, 159 .timer_bit = 1, 160 .clocksource_rating = 200, 161 }; 162 163 static struct resource tmu1_resources[] = { 164 [0] = { 165 .start = 0xffd80014, 166 .end = 0xffd8001f, 167 .flags = IORESOURCE_MEM, 168 }, 169 [1] = { 170 .start = 29, 171 .flags = IORESOURCE_IRQ, 172 }, 173 }; 174 175 static struct platform_device tmu1_device = { 176 .name = "sh_tmu", 177 .id = 1, 178 .dev = { 179 .platform_data = &tmu1_platform_data, 180 }, 181 .resource = tmu1_resources, 182 .num_resources = ARRAY_SIZE(tmu1_resources), 183 }; 184 185 static struct sh_timer_config tmu2_platform_data = { 186 .channel_offset = 0x1c, 187 .timer_bit = 2, 188 }; 189 190 static struct resource tmu2_resources[] = { 191 [0] = { 192 .start = 0xffd80020, 193 .end = 0xffd8002f, 194 .flags = IORESOURCE_MEM, 195 }, 196 [1] = { 197 .start = 30, 198 .flags = IORESOURCE_IRQ, 199 }, 200 }; 201 202 static struct platform_device tmu2_device = { 203 .name = "sh_tmu", 204 .id = 2, 205 .dev = { 206 .platform_data = &tmu2_platform_data, 207 }, 208 .resource = tmu2_resources, 209 .num_resources = ARRAY_SIZE(tmu2_resources), 210 }; 211 212 static struct sh_timer_config tmu3_platform_data = { 213 .channel_offset = 0x04, 214 .timer_bit = 0, 215 }; 216 217 static struct resource tmu3_resources[] = { 218 [0] = { 219 .start = 0xffdc0008, 220 .end = 0xffdc0013, 221 .flags = IORESOURCE_MEM, 222 }, 223 [1] = { 224 .start = 96, 225 .flags = IORESOURCE_IRQ, 226 }, 227 }; 228 229 static struct platform_device tmu3_device = { 230 .name = "sh_tmu", 231 .id = 3, 232 .dev = { 233 .platform_data = &tmu3_platform_data, 234 }, 235 .resource = tmu3_resources, 236 .num_resources = ARRAY_SIZE(tmu3_resources), 237 }; 238 239 static struct sh_timer_config tmu4_platform_data = { 240 .channel_offset = 0x10, 241 .timer_bit = 1, 242 }; 243 244 static struct resource tmu4_resources[] = { 245 [0] = { 246 .start = 0xffdc0014, 247 .end = 0xffdc001f, 248 .flags = IORESOURCE_MEM, 249 }, 250 [1] = { 251 .start = 97, 252 .flags = IORESOURCE_IRQ, 253 }, 254 }; 255 256 static struct platform_device tmu4_device = { 257 .name = "sh_tmu", 258 .id = 4, 259 .dev = { 260 .platform_data = &tmu4_platform_data, 261 }, 262 .resource = tmu4_resources, 263 .num_resources = ARRAY_SIZE(tmu4_resources), 264 }; 265 266 static struct sh_timer_config tmu5_platform_data = { 267 .channel_offset = 0x1c, 268 .timer_bit = 2, 269 }; 270 271 static struct resource tmu5_resources[] = { 272 [0] = { 273 .start = 0xffdc0020, 274 .end = 0xffdc002b, 275 .flags = IORESOURCE_MEM, 276 }, 277 [1] = { 278 .start = 98, 279 .flags = IORESOURCE_IRQ, 280 }, 281 }; 282 283 static struct platform_device tmu5_device = { 284 .name = "sh_tmu", 285 .id = 5, 286 .dev = { 287 .platform_data = &tmu5_platform_data, 288 }, 289 .resource = tmu5_resources, 290 .num_resources = ARRAY_SIZE(tmu5_resources), 291 }; 292 293 /* DMA */ 294 static const struct sh_dmae_channel sh7785_dmae0_channels[] = { 295 { 296 .offset = 0, 297 .dmars = 0, 298 .dmars_bit = 0, 299 }, { 300 .offset = 0x10, 301 .dmars = 0, 302 .dmars_bit = 8, 303 }, { 304 .offset = 0x20, 305 .dmars = 4, 306 .dmars_bit = 0, 307 }, { 308 .offset = 0x30, 309 .dmars = 4, 310 .dmars_bit = 8, 311 }, { 312 .offset = 0x50, 313 .dmars = 8, 314 .dmars_bit = 0, 315 }, { 316 .offset = 0x60, 317 .dmars = 8, 318 .dmars_bit = 8, 319 } 320 }; 321 322 static const struct sh_dmae_channel sh7785_dmae1_channels[] = { 323 { 324 .offset = 0, 325 }, { 326 .offset = 0x10, 327 }, { 328 .offset = 0x20, 329 }, { 330 .offset = 0x30, 331 }, { 332 .offset = 0x50, 333 }, { 334 .offset = 0x60, 335 } 336 }; 337 338 static const unsigned int ts_shift[] = TS_SHIFT; 339 340 static struct sh_dmae_pdata dma0_platform_data = { 341 .channel = sh7785_dmae0_channels, 342 .channel_num = ARRAY_SIZE(sh7785_dmae0_channels), 343 .ts_low_shift = CHCR_TS_LOW_SHIFT, 344 .ts_low_mask = CHCR_TS_LOW_MASK, 345 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 346 .ts_high_mask = CHCR_TS_HIGH_MASK, 347 .ts_shift = ts_shift, 348 .ts_shift_num = ARRAY_SIZE(ts_shift), 349 .dmaor_init = DMAOR_INIT, 350 }; 351 352 static struct sh_dmae_pdata dma1_platform_data = { 353 .channel = sh7785_dmae1_channels, 354 .channel_num = ARRAY_SIZE(sh7785_dmae1_channels), 355 .ts_low_shift = CHCR_TS_LOW_SHIFT, 356 .ts_low_mask = CHCR_TS_LOW_MASK, 357 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 358 .ts_high_mask = CHCR_TS_HIGH_MASK, 359 .ts_shift = ts_shift, 360 .ts_shift_num = ARRAY_SIZE(ts_shift), 361 .dmaor_init = DMAOR_INIT, 362 }; 363 364 static struct resource sh7785_dmae0_resources[] = { 365 [0] = { 366 /* Channel registers and DMAOR */ 367 .start = 0xfc808020, 368 .end = 0xfc80808f, 369 .flags = IORESOURCE_MEM, 370 }, 371 [1] = { 372 /* DMARSx */ 373 .start = 0xfc809000, 374 .end = 0xfc80900b, 375 .flags = IORESOURCE_MEM, 376 }, 377 { 378 /* Real DMA error IRQ is 39, and channel IRQs are 33-38 */ 379 .start = 33, 380 .end = 33, 381 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 382 }, 383 }; 384 385 static struct resource sh7785_dmae1_resources[] = { 386 [0] = { 387 /* Channel registers and DMAOR */ 388 .start = 0xfcc08020, 389 .end = 0xfcc0808f, 390 .flags = IORESOURCE_MEM, 391 }, 392 /* DMAC1 has no DMARS */ 393 { 394 /* Real DMA error IRQ is 58, and channel IRQs are 52-57 */ 395 .start = 52, 396 .end = 52, 397 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 398 }, 399 }; 400 401 static struct platform_device dma0_device = { 402 .name = "sh-dma-engine", 403 .id = 0, 404 .resource = sh7785_dmae0_resources, 405 .num_resources = ARRAY_SIZE(sh7785_dmae0_resources), 406 .dev = { 407 .platform_data = &dma0_platform_data, 408 }, 409 }; 410 411 static struct platform_device dma1_device = { 412 .name = "sh-dma-engine", 413 .id = 1, 414 .resource = sh7785_dmae1_resources, 415 .num_resources = ARRAY_SIZE(sh7785_dmae1_resources), 416 .dev = { 417 .platform_data = &dma1_platform_data, 418 }, 419 }; 420 421 static struct platform_device *sh7785_devices[] __initdata = { 422 &scif0_device, 423 &scif1_device, 424 &scif2_device, 425 &scif3_device, 426 &scif4_device, 427 &scif5_device, 428 &tmu0_device, 429 &tmu1_device, 430 &tmu2_device, 431 &tmu3_device, 432 &tmu4_device, 433 &tmu5_device, 434 &dma0_device, 435 &dma1_device, 436 }; 437 438 static int __init sh7785_devices_setup(void) 439 { 440 return platform_add_devices(sh7785_devices, 441 ARRAY_SIZE(sh7785_devices)); 442 } 443 arch_initcall(sh7785_devices_setup); 444 445 static struct platform_device *sh7785_early_devices[] __initdata = { 446 &scif0_device, 447 &scif1_device, 448 &scif2_device, 449 &scif3_device, 450 &scif4_device, 451 &scif5_device, 452 &tmu0_device, 453 &tmu1_device, 454 &tmu2_device, 455 &tmu3_device, 456 &tmu4_device, 457 &tmu5_device, 458 }; 459 460 void __init plat_early_device_setup(void) 461 { 462 early_platform_add_devices(sh7785_early_devices, 463 ARRAY_SIZE(sh7785_early_devices)); 464 } 465 466 enum { 467 UNUSED = 0, 468 469 /* interrupt sources */ 470 471 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, 472 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, 473 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, 474 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 475 476 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH, 477 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH, 478 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH, 479 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 480 481 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 482 WDT, TMU0, TMU1, TMU2, TMU2_TICPI, 483 HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI, 484 SCIF2, SCIF3, SCIF4, SCIF5, 485 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5, 486 SIOF, MMCIF, DU, GDTA, 487 TMU3, TMU4, TMU5, 488 SSI0, SSI1, 489 HAC0, HAC1, 490 FLCTL, GPIO, 491 492 /* interrupt groups */ 493 494 TMU012, TMU345 495 }; 496 497 static struct intc_vect vectors[] __initdata = { 498 INTC_VECT(WDT, 0x560), 499 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), 500 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), 501 INTC_VECT(HUDI, 0x600), 502 INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640), 503 INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680), 504 INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0), 505 INTC_VECT(DMAC0, 0x6e0), 506 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720), 507 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760), 508 INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0), 509 INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0), 510 INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0), 511 INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0), 512 INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920), 513 INTC_VECT(DMAC1, 0x940), 514 INTC_VECT(HSPI, 0x960), 515 INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0), 516 INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0), 517 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20), 518 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60), 519 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0), 520 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0), 521 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20), 522 INTC_VECT(SIOF, 0xc00), 523 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20), 524 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60), 525 INTC_VECT(DU, 0xd80), 526 INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0), 527 INTC_VECT(GDTA, 0xde0), 528 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 529 INTC_VECT(TMU5, 0xe40), 530 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0), 531 INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0), 532 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20), 533 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60), 534 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0), 535 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0), 536 }; 537 538 static struct intc_group groups[] __initdata = { 539 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), 540 INTC_GROUP(TMU345, TMU3, TMU4, TMU5), 541 }; 542 543 static struct intc_mask_reg mask_registers[] __initdata = { 544 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ 545 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 546 547 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ 548 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, 549 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, 550 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, 551 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0, 552 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH, 553 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH, 554 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH, 555 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } }, 556 557 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ 558 { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO, 559 FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB, 560 PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT, 561 SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } }, 562 }; 563 564 static struct intc_prio_reg prio_registers[] __initdata = { 565 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, 566 IRQ4, IRQ5, IRQ6, IRQ7 } }, 567 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, 568 TMU2, TMU2_TICPI } }, 569 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } }, 570 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, 571 SCIF2, SCIF3 } }, 572 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } }, 573 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } }, 574 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1, 575 PCISERR, PCIINTA } }, 576 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC, 577 PCIINTD, PCIC5 } }, 578 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } }, 579 { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } }, 580 { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } }, 581 }; 582 583 static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups, 584 mask_registers, prio_registers, NULL); 585 586 /* Support for external interrupt pins in IRQ mode */ 587 588 static struct intc_vect vectors_irq0123[] __initdata = { 589 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), 590 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), 591 }; 592 593 static struct intc_vect vectors_irq4567[] __initdata = { 594 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380), 595 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200), 596 }; 597 598 static struct intc_sense_reg sense_registers[] __initdata = { 599 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, 600 IRQ4, IRQ5, IRQ6, IRQ7 } }, 601 }; 602 603 static struct intc_mask_reg ack_registers[] __initdata = { 604 { 0xffd00024, 0, 32, /* INTREQ */ 605 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 606 }; 607 608 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123", 609 vectors_irq0123, NULL, mask_registers, 610 prio_registers, sense_registers, ack_registers); 611 612 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567", 613 vectors_irq4567, NULL, mask_registers, 614 prio_registers, sense_registers, ack_registers); 615 616 /* External interrupt pins in IRL mode */ 617 618 static struct intc_vect vectors_irl0123[] __initdata = { 619 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220), 620 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260), 621 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0), 622 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0), 623 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320), 624 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360), 625 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0), 626 INTC_VECT(IRL0_HHHL, 0x3c0), 627 }; 628 629 static struct intc_vect vectors_irl4567[] __initdata = { 630 INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20), 631 INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60), 632 INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0), 633 INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0), 634 INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20), 635 INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60), 636 INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0), 637 INTC_VECT(IRL4_HHHL, 0xcc0), 638 }; 639 640 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123, 641 NULL, mask_registers, NULL, NULL); 642 643 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567, 644 NULL, mask_registers, NULL, NULL); 645 646 #define INTC_ICR0 0xffd00000 647 #define INTC_INTMSK0 0xffd00044 648 #define INTC_INTMSK1 0xffd00048 649 #define INTC_INTMSK2 0xffd40080 650 #define INTC_INTMSKCLR1 0xffd00068 651 #define INTC_INTMSKCLR2 0xffd40084 652 653 void __init plat_irq_setup(void) 654 { 655 /* disable IRQ3-0 + IRQ7-4 */ 656 __raw_writel(0xff000000, INTC_INTMSK0); 657 658 /* disable IRL3-0 + IRL7-4 */ 659 __raw_writel(0xc0000000, INTC_INTMSK1); 660 __raw_writel(0xfffefffe, INTC_INTMSK2); 661 662 /* select IRL mode for IRL3-0 + IRL7-4 */ 663 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 664 665 /* disable holding function, ie enable "SH-4 Mode" */ 666 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); 667 668 register_intc_controller(&intc_desc); 669 } 670 671 void __init plat_irq_setup_pins(int mode) 672 { 673 switch (mode) { 674 case IRQ_MODE_IRQ7654: 675 /* select IRQ mode for IRL7-4 */ 676 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0); 677 register_intc_controller(&intc_desc_irq4567); 678 break; 679 case IRQ_MODE_IRQ3210: 680 /* select IRQ mode for IRL3-0 */ 681 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); 682 register_intc_controller(&intc_desc_irq0123); 683 break; 684 case IRQ_MODE_IRL7654: 685 /* enable IRL7-4 but don't provide any masking */ 686 __raw_writel(0x40000000, INTC_INTMSKCLR1); 687 __raw_writel(0x0000fffe, INTC_INTMSKCLR2); 688 break; 689 case IRQ_MODE_IRL3210: 690 /* enable IRL0-3 but don't provide any masking */ 691 __raw_writel(0x80000000, INTC_INTMSKCLR1); 692 __raw_writel(0xfffe0000, INTC_INTMSKCLR2); 693 break; 694 case IRQ_MODE_IRL7654_MASK: 695 /* enable IRL7-4 and mask using cpu intc controller */ 696 __raw_writel(0x40000000, INTC_INTMSKCLR1); 697 register_intc_controller(&intc_desc_irl4567); 698 break; 699 case IRQ_MODE_IRL3210_MASK: 700 /* enable IRL0-3 and mask using cpu intc controller */ 701 __raw_writel(0x80000000, INTC_INTMSKCLR1); 702 register_intc_controller(&intc_desc_irl0123); 703 break; 704 default: 705 BUG(); 706 } 707 } 708 709 void __init plat_mem_setup(void) 710 { 711 /* Register the URAM space as Node 1 */ 712 setup_bootmem_node(1, 0xe55f0000, 0xe5610000); 713 } 714