1 /* 2 * SH7780 Setup 3 * 4 * Copyright (C) 2006 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/io.h> 14 #include <linux/serial_sci.h> 15 #include <linux/sh_timer.h> 16 #include <asm/dma-sh.h> 17 18 static struct plat_sci_port scif0_platform_data = { 19 .mapbase = 0xffe00000, 20 .flags = UPF_BOOT_AUTOCONF, 21 .type = PORT_SCIF, 22 .irqs = { 40, 40, 40, 40 }, 23 }; 24 25 static struct platform_device scif0_device = { 26 .name = "sh-sci", 27 .id = 0, 28 .dev = { 29 .platform_data = &scif0_platform_data, 30 }, 31 }; 32 33 static struct plat_sci_port scif1_platform_data = { 34 .mapbase = 0xffe10000, 35 .flags = UPF_BOOT_AUTOCONF, 36 .type = PORT_SCIF, 37 .irqs = { 76, 76, 76, 76 }, 38 }; 39 40 static struct platform_device scif1_device = { 41 .name = "sh-sci", 42 .id = 1, 43 .dev = { 44 .platform_data = &scif1_platform_data, 45 }, 46 }; 47 48 static struct sh_timer_config tmu0_platform_data = { 49 .name = "TMU0", 50 .channel_offset = 0x04, 51 .timer_bit = 0, 52 .clk = "peripheral_clk", 53 .clockevent_rating = 200, 54 }; 55 56 static struct resource tmu0_resources[] = { 57 [0] = { 58 .name = "TMU0", 59 .start = 0xffd80008, 60 .end = 0xffd80013, 61 .flags = IORESOURCE_MEM, 62 }, 63 [1] = { 64 .start = 28, 65 .flags = IORESOURCE_IRQ, 66 }, 67 }; 68 69 static struct platform_device tmu0_device = { 70 .name = "sh_tmu", 71 .id = 0, 72 .dev = { 73 .platform_data = &tmu0_platform_data, 74 }, 75 .resource = tmu0_resources, 76 .num_resources = ARRAY_SIZE(tmu0_resources), 77 }; 78 79 static struct sh_timer_config tmu1_platform_data = { 80 .name = "TMU1", 81 .channel_offset = 0x10, 82 .timer_bit = 1, 83 .clk = "peripheral_clk", 84 .clocksource_rating = 200, 85 }; 86 87 static struct resource tmu1_resources[] = { 88 [0] = { 89 .name = "TMU1", 90 .start = 0xffd80014, 91 .end = 0xffd8001f, 92 .flags = IORESOURCE_MEM, 93 }, 94 [1] = { 95 .start = 29, 96 .flags = IORESOURCE_IRQ, 97 }, 98 }; 99 100 static struct platform_device tmu1_device = { 101 .name = "sh_tmu", 102 .id = 1, 103 .dev = { 104 .platform_data = &tmu1_platform_data, 105 }, 106 .resource = tmu1_resources, 107 .num_resources = ARRAY_SIZE(tmu1_resources), 108 }; 109 110 static struct sh_timer_config tmu2_platform_data = { 111 .name = "TMU2", 112 .channel_offset = 0x1c, 113 .timer_bit = 2, 114 .clk = "peripheral_clk", 115 }; 116 117 static struct resource tmu2_resources[] = { 118 [0] = { 119 .name = "TMU2", 120 .start = 0xffd80020, 121 .end = 0xffd8002f, 122 .flags = IORESOURCE_MEM, 123 }, 124 [1] = { 125 .start = 30, 126 .flags = IORESOURCE_IRQ, 127 }, 128 }; 129 130 static struct platform_device tmu2_device = { 131 .name = "sh_tmu", 132 .id = 2, 133 .dev = { 134 .platform_data = &tmu2_platform_data, 135 }, 136 .resource = tmu2_resources, 137 .num_resources = ARRAY_SIZE(tmu2_resources), 138 }; 139 140 static struct sh_timer_config tmu3_platform_data = { 141 .name = "TMU3", 142 .channel_offset = 0x04, 143 .timer_bit = 0, 144 .clk = "peripheral_clk", 145 }; 146 147 static struct resource tmu3_resources[] = { 148 [0] = { 149 .name = "TMU3", 150 .start = 0xffdc0008, 151 .end = 0xffdc0013, 152 .flags = IORESOURCE_MEM, 153 }, 154 [1] = { 155 .start = 96, 156 .flags = IORESOURCE_IRQ, 157 }, 158 }; 159 160 static struct platform_device tmu3_device = { 161 .name = "sh_tmu", 162 .id = 3, 163 .dev = { 164 .platform_data = &tmu3_platform_data, 165 }, 166 .resource = tmu3_resources, 167 .num_resources = ARRAY_SIZE(tmu3_resources), 168 }; 169 170 static struct sh_timer_config tmu4_platform_data = { 171 .name = "TMU4", 172 .channel_offset = 0x10, 173 .timer_bit = 1, 174 .clk = "peripheral_clk", 175 }; 176 177 static struct resource tmu4_resources[] = { 178 [0] = { 179 .name = "TMU4", 180 .start = 0xffdc0014, 181 .end = 0xffdc001f, 182 .flags = IORESOURCE_MEM, 183 }, 184 [1] = { 185 .start = 97, 186 .flags = IORESOURCE_IRQ, 187 }, 188 }; 189 190 static struct platform_device tmu4_device = { 191 .name = "sh_tmu", 192 .id = 4, 193 .dev = { 194 .platform_data = &tmu4_platform_data, 195 }, 196 .resource = tmu4_resources, 197 .num_resources = ARRAY_SIZE(tmu4_resources), 198 }; 199 200 static struct sh_timer_config tmu5_platform_data = { 201 .name = "TMU5", 202 .channel_offset = 0x1c, 203 .timer_bit = 2, 204 .clk = "peripheral_clk", 205 }; 206 207 static struct resource tmu5_resources[] = { 208 [0] = { 209 .name = "TMU5", 210 .start = 0xffdc0020, 211 .end = 0xffdc002b, 212 .flags = IORESOURCE_MEM, 213 }, 214 [1] = { 215 .start = 98, 216 .flags = IORESOURCE_IRQ, 217 }, 218 }; 219 220 static struct platform_device tmu5_device = { 221 .name = "sh_tmu", 222 .id = 5, 223 .dev = { 224 .platform_data = &tmu5_platform_data, 225 }, 226 .resource = tmu5_resources, 227 .num_resources = ARRAY_SIZE(tmu5_resources), 228 }; 229 230 static struct resource rtc_resources[] = { 231 [0] = { 232 .start = 0xffe80000, 233 .end = 0xffe80000 + 0x58 - 1, 234 .flags = IORESOURCE_IO, 235 }, 236 [1] = { 237 /* Shared Period/Carry/Alarm IRQ */ 238 .start = 20, 239 .flags = IORESOURCE_IRQ, 240 }, 241 }; 242 243 static struct platform_device rtc_device = { 244 .name = "sh-rtc", 245 .id = -1, 246 .num_resources = ARRAY_SIZE(rtc_resources), 247 .resource = rtc_resources, 248 }; 249 250 static struct sh_dmae_pdata dma_platform_data = { 251 .mode = (SHDMA_MIX_IRQ | SHDMA_DMAOR1), 252 }; 253 254 static struct platform_device dma_device = { 255 .name = "sh-dma-engine", 256 .id = -1, 257 .dev = { 258 .platform_data = &dma_platform_data, 259 }, 260 }; 261 262 static struct platform_device *sh7780_devices[] __initdata = { 263 &scif0_device, 264 &scif1_device, 265 &tmu0_device, 266 &tmu1_device, 267 &tmu2_device, 268 &tmu3_device, 269 &tmu4_device, 270 &tmu5_device, 271 &rtc_device, 272 &dma_device, 273 }; 274 275 static int __init sh7780_devices_setup(void) 276 { 277 return platform_add_devices(sh7780_devices, 278 ARRAY_SIZE(sh7780_devices)); 279 } 280 arch_initcall(sh7780_devices_setup); 281 static struct platform_device *sh7780_early_devices[] __initdata = { 282 &scif0_device, 283 &scif1_device, 284 &tmu0_device, 285 &tmu1_device, 286 &tmu2_device, 287 &tmu3_device, 288 &tmu4_device, 289 &tmu5_device, 290 }; 291 292 void __init plat_early_device_setup(void) 293 { 294 early_platform_add_devices(sh7780_early_devices, 295 ARRAY_SIZE(sh7780_early_devices)); 296 } 297 298 enum { 299 UNUSED = 0, 300 301 /* interrupt sources */ 302 303 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 304 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 305 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 306 IRL_HHLL, IRL_HHLH, IRL_HHHL, 307 308 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 309 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI, 310 HUDI, DMAC0, SCIF0, DMAC1, CMT, HAC, 311 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5, 312 SCIF1, SIOF, HSPI, MMCIF, TMU3, TMU4, TMU5, SSI, FLCTL, GPIO, 313 314 /* interrupt groups */ 315 316 TMU012, TMU345, 317 }; 318 319 static struct intc_vect vectors[] __initdata = { 320 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 321 INTC_VECT(RTC, 0x4c0), 322 INTC_VECT(WDT, 0x560), 323 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), 324 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), 325 INTC_VECT(HUDI, 0x600), 326 INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660), 327 INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0), 328 INTC_VECT(DMAC0, 0x6c0), 329 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720), 330 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760), 331 INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0), 332 INTC_VECT(DMAC1, 0x7c0), INTC_VECT(DMAC1, 0x7e0), 333 INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980), 334 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20), 335 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60), 336 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0), 337 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0), 338 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20), 339 INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0), 340 INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0), 341 INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80), 342 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20), 343 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60), 344 INTC_VECT(DMAC1, 0xd80), INTC_VECT(DMAC1, 0xda0), 345 INTC_VECT(DMAC1, 0xdc0), INTC_VECT(DMAC1, 0xde0), 346 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 347 INTC_VECT(TMU5, 0xe40), 348 INTC_VECT(SSI, 0xe80), 349 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20), 350 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60), 351 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0), 352 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0), 353 }; 354 355 static struct intc_group groups[] __initdata = { 356 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), 357 INTC_GROUP(TMU345, TMU3, TMU4, TMU5), 358 }; 359 360 static struct intc_mask_reg mask_registers[] __initdata = { 361 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ 362 { 0, 0, 0, 0, 0, 0, GPIO, FLCTL, 363 SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB, 364 PCIINTA, PCISERR, HAC, CMT, 0, 0, DMAC1, DMAC0, 365 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } }, 366 }; 367 368 static struct intc_prio_reg prio_registers[] __initdata = { 369 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, 370 TMU2, TMU2_TICPI } }, 371 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } }, 372 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } }, 373 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } }, 374 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC, 375 PCISERR, PCIINTA, } }, 376 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC, 377 PCIINTD, PCIC5 } }, 378 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } }, 379 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } }, 380 }; 381 382 static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups, 383 mask_registers, prio_registers, NULL); 384 385 /* Support for external interrupt pins in IRQ mode */ 386 387 static struct intc_vect irq_vectors[] __initdata = { 388 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), 389 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), 390 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380), 391 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200), 392 }; 393 394 static struct intc_mask_reg irq_mask_registers[] __initdata = { 395 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ 396 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 397 }; 398 399 static struct intc_prio_reg irq_prio_registers[] __initdata = { 400 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, 401 IRQ4, IRQ5, IRQ6, IRQ7 } }, 402 }; 403 404 static struct intc_sense_reg irq_sense_registers[] __initdata = { 405 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, 406 IRQ4, IRQ5, IRQ6, IRQ7 } }, 407 }; 408 409 static struct intc_mask_reg irq_ack_registers[] __initdata = { 410 { 0xffd00024, 0, 32, /* INTREQ */ 411 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 412 }; 413 414 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7780-irq", irq_vectors, 415 NULL, irq_mask_registers, irq_prio_registers, 416 irq_sense_registers, irq_ack_registers); 417 418 /* External interrupt pins in IRL mode */ 419 420 static struct intc_vect irl_vectors[] __initdata = { 421 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220), 422 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260), 423 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0), 424 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0), 425 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320), 426 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360), 427 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0), 428 INTC_VECT(IRL_HHHL, 0x3c0), 429 }; 430 431 static struct intc_mask_reg irl3210_mask_registers[] __initdata = { 432 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ 433 { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 434 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 435 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 436 IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, 437 }; 438 439 static struct intc_mask_reg irl7654_mask_registers[] __initdata = { 440 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ 441 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 442 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 443 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 444 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 445 IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, 446 }; 447 448 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors, 449 NULL, irl7654_mask_registers, NULL, NULL); 450 451 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors, 452 NULL, irl3210_mask_registers, NULL, NULL); 453 454 #define INTC_ICR0 0xffd00000 455 #define INTC_INTMSK0 0xffd00044 456 #define INTC_INTMSK1 0xffd00048 457 #define INTC_INTMSK2 0xffd40080 458 #define INTC_INTMSKCLR1 0xffd00068 459 #define INTC_INTMSKCLR2 0xffd40084 460 461 void __init plat_irq_setup(void) 462 { 463 /* disable IRQ7-0 */ 464 ctrl_outl(0xff000000, INTC_INTMSK0); 465 466 /* disable IRL3-0 + IRL7-4 */ 467 ctrl_outl(0xc0000000, INTC_INTMSK1); 468 ctrl_outl(0xfffefffe, INTC_INTMSK2); 469 470 /* select IRL mode for IRL3-0 + IRL7-4 */ 471 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 472 473 /* disable holding function, ie enable "SH-4 Mode" */ 474 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0); 475 476 register_intc_controller(&intc_desc); 477 } 478 479 void __init plat_irq_setup_pins(int mode) 480 { 481 switch (mode) { 482 case IRQ_MODE_IRQ: 483 /* select IRQ mode for IRL3-0 + IRL7-4 */ 484 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0); 485 register_intc_controller(&intc_irq_desc); 486 break; 487 case IRQ_MODE_IRL7654: 488 /* enable IRL7-4 but don't provide any masking */ 489 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 490 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); 491 break; 492 case IRQ_MODE_IRL3210: 493 /* enable IRL0-3 but don't provide any masking */ 494 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 495 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); 496 break; 497 case IRQ_MODE_IRL7654_MASK: 498 /* enable IRL7-4 and mask using cpu intc controller */ 499 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 500 register_intc_controller(&intc_irl7654_desc); 501 break; 502 case IRQ_MODE_IRL3210_MASK: 503 /* enable IRL0-3 and mask using cpu intc controller */ 504 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 505 register_intc_controller(&intc_irl3210_desc); 506 break; 507 default: 508 BUG(); 509 } 510 } 511