1 /* 2 * SH7780 Setup 3 * 4 * Copyright (C) 2006 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/io.h> 14 #include <linux/serial_sci.h> 15 #include <linux/sh_dma.h> 16 #include <linux/sh_timer.h> 17 #include <linux/sh_intc.h> 18 #include <cpu/dma-register.h> 19 20 static struct plat_sci_port scif0_platform_data = { 21 .mapbase = 0xffe00000, 22 .flags = UPF_BOOT_AUTOCONF, 23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 24 .scbrr_algo_id = SCBRR_ALGO_1, 25 .type = PORT_SCIF, 26 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), 27 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 28 }; 29 30 static struct platform_device scif0_device = { 31 .name = "sh-sci", 32 .id = 0, 33 .dev = { 34 .platform_data = &scif0_platform_data, 35 }, 36 }; 37 38 static struct plat_sci_port scif1_platform_data = { 39 .mapbase = 0xffe10000, 40 .flags = UPF_BOOT_AUTOCONF, 41 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 42 .scbrr_algo_id = SCBRR_ALGO_1, 43 .type = PORT_SCIF, 44 .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)), 45 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 46 }; 47 48 static struct platform_device scif1_device = { 49 .name = "sh-sci", 50 .id = 1, 51 .dev = { 52 .platform_data = &scif1_platform_data, 53 }, 54 }; 55 56 static struct sh_timer_config tmu0_platform_data = { 57 .channel_offset = 0x04, 58 .timer_bit = 0, 59 .clockevent_rating = 200, 60 }; 61 62 static struct resource tmu0_resources[] = { 63 [0] = { 64 .start = 0xffd80008, 65 .end = 0xffd80013, 66 .flags = IORESOURCE_MEM, 67 }, 68 [1] = { 69 .start = evt2irq(0x580), 70 .flags = IORESOURCE_IRQ, 71 }, 72 }; 73 74 static struct platform_device tmu0_device = { 75 .name = "sh_tmu", 76 .id = 0, 77 .dev = { 78 .platform_data = &tmu0_platform_data, 79 }, 80 .resource = tmu0_resources, 81 .num_resources = ARRAY_SIZE(tmu0_resources), 82 }; 83 84 static struct sh_timer_config tmu1_platform_data = { 85 .channel_offset = 0x10, 86 .timer_bit = 1, 87 .clocksource_rating = 200, 88 }; 89 90 static struct resource tmu1_resources[] = { 91 [0] = { 92 .start = 0xffd80014, 93 .end = 0xffd8001f, 94 .flags = IORESOURCE_MEM, 95 }, 96 [1] = { 97 .start = evt2irq(0x5a0), 98 .flags = IORESOURCE_IRQ, 99 }, 100 }; 101 102 static struct platform_device tmu1_device = { 103 .name = "sh_tmu", 104 .id = 1, 105 .dev = { 106 .platform_data = &tmu1_platform_data, 107 }, 108 .resource = tmu1_resources, 109 .num_resources = ARRAY_SIZE(tmu1_resources), 110 }; 111 112 static struct sh_timer_config tmu2_platform_data = { 113 .channel_offset = 0x1c, 114 .timer_bit = 2, 115 }; 116 117 static struct resource tmu2_resources[] = { 118 [0] = { 119 .start = 0xffd80020, 120 .end = 0xffd8002f, 121 .flags = IORESOURCE_MEM, 122 }, 123 [1] = { 124 .start = evt2irq(0x5c0), 125 .flags = IORESOURCE_IRQ, 126 }, 127 }; 128 129 static struct platform_device tmu2_device = { 130 .name = "sh_tmu", 131 .id = 2, 132 .dev = { 133 .platform_data = &tmu2_platform_data, 134 }, 135 .resource = tmu2_resources, 136 .num_resources = ARRAY_SIZE(tmu2_resources), 137 }; 138 139 static struct sh_timer_config tmu3_platform_data = { 140 .channel_offset = 0x04, 141 .timer_bit = 0, 142 }; 143 144 static struct resource tmu3_resources[] = { 145 [0] = { 146 .start = 0xffdc0008, 147 .end = 0xffdc0013, 148 .flags = IORESOURCE_MEM, 149 }, 150 [1] = { 151 .start = evt2irq(0xe00), 152 .flags = IORESOURCE_IRQ, 153 }, 154 }; 155 156 static struct platform_device tmu3_device = { 157 .name = "sh_tmu", 158 .id = 3, 159 .dev = { 160 .platform_data = &tmu3_platform_data, 161 }, 162 .resource = tmu3_resources, 163 .num_resources = ARRAY_SIZE(tmu3_resources), 164 }; 165 166 static struct sh_timer_config tmu4_platform_data = { 167 .channel_offset = 0x10, 168 .timer_bit = 1, 169 }; 170 171 static struct resource tmu4_resources[] = { 172 [0] = { 173 .start = 0xffdc0014, 174 .end = 0xffdc001f, 175 .flags = IORESOURCE_MEM, 176 }, 177 [1] = { 178 .start = evt2irq(0xe20), 179 .flags = IORESOURCE_IRQ, 180 }, 181 }; 182 183 static struct platform_device tmu4_device = { 184 .name = "sh_tmu", 185 .id = 4, 186 .dev = { 187 .platform_data = &tmu4_platform_data, 188 }, 189 .resource = tmu4_resources, 190 .num_resources = ARRAY_SIZE(tmu4_resources), 191 }; 192 193 static struct sh_timer_config tmu5_platform_data = { 194 .channel_offset = 0x1c, 195 .timer_bit = 2, 196 }; 197 198 static struct resource tmu5_resources[] = { 199 [0] = { 200 .start = 0xffdc0020, 201 .end = 0xffdc002b, 202 .flags = IORESOURCE_MEM, 203 }, 204 [1] = { 205 .start = evt2irq(0xe40), 206 .flags = IORESOURCE_IRQ, 207 }, 208 }; 209 210 static struct platform_device tmu5_device = { 211 .name = "sh_tmu", 212 .id = 5, 213 .dev = { 214 .platform_data = &tmu5_platform_data, 215 }, 216 .resource = tmu5_resources, 217 .num_resources = ARRAY_SIZE(tmu5_resources), 218 }; 219 220 static struct resource rtc_resources[] = { 221 [0] = { 222 .start = 0xffe80000, 223 .end = 0xffe80000 + 0x58 - 1, 224 .flags = IORESOURCE_IO, 225 }, 226 [1] = { 227 /* Shared Period/Carry/Alarm IRQ */ 228 .start = evt2irq(0x480), 229 .flags = IORESOURCE_IRQ, 230 }, 231 }; 232 233 static struct platform_device rtc_device = { 234 .name = "sh-rtc", 235 .id = -1, 236 .num_resources = ARRAY_SIZE(rtc_resources), 237 .resource = rtc_resources, 238 }; 239 240 /* DMA */ 241 static const struct sh_dmae_channel sh7780_dmae0_channels[] = { 242 { 243 .offset = 0, 244 .dmars = 0, 245 .dmars_bit = 0, 246 }, { 247 .offset = 0x10, 248 .dmars = 0, 249 .dmars_bit = 8, 250 }, { 251 .offset = 0x20, 252 .dmars = 4, 253 .dmars_bit = 0, 254 }, { 255 .offset = 0x30, 256 .dmars = 4, 257 .dmars_bit = 8, 258 }, { 259 .offset = 0x50, 260 .dmars = 8, 261 .dmars_bit = 0, 262 }, { 263 .offset = 0x60, 264 .dmars = 8, 265 .dmars_bit = 8, 266 } 267 }; 268 269 static const struct sh_dmae_channel sh7780_dmae1_channels[] = { 270 { 271 .offset = 0, 272 }, { 273 .offset = 0x10, 274 }, { 275 .offset = 0x20, 276 }, { 277 .offset = 0x30, 278 }, { 279 .offset = 0x50, 280 }, { 281 .offset = 0x60, 282 } 283 }; 284 285 static const unsigned int ts_shift[] = TS_SHIFT; 286 287 static struct sh_dmae_pdata dma0_platform_data = { 288 .channel = sh7780_dmae0_channels, 289 .channel_num = ARRAY_SIZE(sh7780_dmae0_channels), 290 .ts_low_shift = CHCR_TS_LOW_SHIFT, 291 .ts_low_mask = CHCR_TS_LOW_MASK, 292 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 293 .ts_high_mask = CHCR_TS_HIGH_MASK, 294 .ts_shift = ts_shift, 295 .ts_shift_num = ARRAY_SIZE(ts_shift), 296 .dmaor_init = DMAOR_INIT, 297 }; 298 299 static struct sh_dmae_pdata dma1_platform_data = { 300 .channel = sh7780_dmae1_channels, 301 .channel_num = ARRAY_SIZE(sh7780_dmae1_channels), 302 .ts_low_shift = CHCR_TS_LOW_SHIFT, 303 .ts_low_mask = CHCR_TS_LOW_MASK, 304 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 305 .ts_high_mask = CHCR_TS_HIGH_MASK, 306 .ts_shift = ts_shift, 307 .ts_shift_num = ARRAY_SIZE(ts_shift), 308 .dmaor_init = DMAOR_INIT, 309 }; 310 311 static struct resource sh7780_dmae0_resources[] = { 312 [0] = { 313 /* Channel registers and DMAOR */ 314 .start = 0xfc808020, 315 .end = 0xfc80808f, 316 .flags = IORESOURCE_MEM, 317 }, 318 [1] = { 319 /* DMARSx */ 320 .start = 0xfc809000, 321 .end = 0xfc80900b, 322 .flags = IORESOURCE_MEM, 323 }, 324 { 325 /* 326 * Real DMA error vector is 0x6c0, and channel 327 * vectors are 0x640-0x6a0, 0x780-0x7a0 328 */ 329 .name = "error_irq", 330 .start = evt2irq(0x640), 331 .end = evt2irq(0x640), 332 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 333 }, 334 }; 335 336 static struct resource sh7780_dmae1_resources[] = { 337 [0] = { 338 /* Channel registers and DMAOR */ 339 .start = 0xfc818020, 340 .end = 0xfc81808f, 341 .flags = IORESOURCE_MEM, 342 }, 343 /* DMAC1 has no DMARS */ 344 { 345 /* 346 * Real DMA error vector is 0x6c0, and channel 347 * vectors are 0x7c0-0x7e0, 0xd80-0xde0 348 */ 349 .name = "error_irq", 350 .start = evt2irq(0x7c0), 351 .end = evt2irq(0x7c0), 352 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 353 }, 354 }; 355 356 static struct platform_device dma0_device = { 357 .name = "sh-dma-engine", 358 .id = 0, 359 .resource = sh7780_dmae0_resources, 360 .num_resources = ARRAY_SIZE(sh7780_dmae0_resources), 361 .dev = { 362 .platform_data = &dma0_platform_data, 363 }, 364 }; 365 366 static struct platform_device dma1_device = { 367 .name = "sh-dma-engine", 368 .id = 1, 369 .resource = sh7780_dmae1_resources, 370 .num_resources = ARRAY_SIZE(sh7780_dmae1_resources), 371 .dev = { 372 .platform_data = &dma1_platform_data, 373 }, 374 }; 375 376 static struct platform_device *sh7780_devices[] __initdata = { 377 &scif0_device, 378 &scif1_device, 379 &tmu0_device, 380 &tmu1_device, 381 &tmu2_device, 382 &tmu3_device, 383 &tmu4_device, 384 &tmu5_device, 385 &rtc_device, 386 &dma0_device, 387 &dma1_device, 388 }; 389 390 static int __init sh7780_devices_setup(void) 391 { 392 return platform_add_devices(sh7780_devices, 393 ARRAY_SIZE(sh7780_devices)); 394 } 395 arch_initcall(sh7780_devices_setup); 396 397 static struct platform_device *sh7780_early_devices[] __initdata = { 398 &scif0_device, 399 &scif1_device, 400 &tmu0_device, 401 &tmu1_device, 402 &tmu2_device, 403 &tmu3_device, 404 &tmu4_device, 405 &tmu5_device, 406 }; 407 408 void __init plat_early_device_setup(void) 409 { 410 if (mach_is_sh2007()) { 411 scif0_platform_data.scscr &= ~SCSCR_CKE1; 412 scif0_platform_data.scbrr_algo_id = SCBRR_ALGO_2; 413 scif1_platform_data.scscr &= ~SCSCR_CKE1; 414 scif1_platform_data.scbrr_algo_id = SCBRR_ALGO_2; 415 } 416 417 early_platform_add_devices(sh7780_early_devices, 418 ARRAY_SIZE(sh7780_early_devices)); 419 } 420 421 enum { 422 UNUSED = 0, 423 424 /* interrupt sources */ 425 426 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 427 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 428 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 429 IRL_HHLL, IRL_HHLH, IRL_HHHL, 430 431 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 432 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI, 433 HUDI, DMAC0, SCIF0, DMAC1, CMT, HAC, 434 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5, 435 SCIF1, SIOF, HSPI, MMCIF, TMU3, TMU4, TMU5, SSI, FLCTL, GPIO, 436 437 /* interrupt groups */ 438 439 TMU012, TMU345, 440 }; 441 442 static struct intc_vect vectors[] __initdata = { 443 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 444 INTC_VECT(RTC, 0x4c0), 445 INTC_VECT(WDT, 0x560), 446 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), 447 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), 448 INTC_VECT(HUDI, 0x600), 449 INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660), 450 INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0), 451 INTC_VECT(DMAC0, 0x6c0), 452 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720), 453 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760), 454 INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0), 455 INTC_VECT(DMAC1, 0x7c0), INTC_VECT(DMAC1, 0x7e0), 456 INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980), 457 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20), 458 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60), 459 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0), 460 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0), 461 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20), 462 INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0), 463 INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0), 464 INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80), 465 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20), 466 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60), 467 INTC_VECT(DMAC1, 0xd80), INTC_VECT(DMAC1, 0xda0), 468 INTC_VECT(DMAC1, 0xdc0), INTC_VECT(DMAC1, 0xde0), 469 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 470 INTC_VECT(TMU5, 0xe40), 471 INTC_VECT(SSI, 0xe80), 472 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20), 473 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60), 474 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0), 475 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0), 476 }; 477 478 static struct intc_group groups[] __initdata = { 479 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), 480 INTC_GROUP(TMU345, TMU3, TMU4, TMU5), 481 }; 482 483 static struct intc_mask_reg mask_registers[] __initdata = { 484 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ 485 { 0, 0, 0, 0, 0, 0, GPIO, FLCTL, 486 SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB, 487 PCIINTA, PCISERR, HAC, CMT, 0, 0, DMAC1, DMAC0, 488 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } }, 489 }; 490 491 static struct intc_prio_reg prio_registers[] __initdata = { 492 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, 493 TMU2, TMU2_TICPI } }, 494 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } }, 495 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } }, 496 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } }, 497 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC, 498 PCISERR, PCIINTA, } }, 499 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC, 500 PCIINTD, PCIC5 } }, 501 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } }, 502 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } }, 503 }; 504 505 static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups, 506 mask_registers, prio_registers, NULL); 507 508 /* Support for external interrupt pins in IRQ mode */ 509 510 static struct intc_vect irq_vectors[] __initdata = { 511 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), 512 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), 513 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380), 514 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200), 515 }; 516 517 static struct intc_mask_reg irq_mask_registers[] __initdata = { 518 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ 519 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 520 }; 521 522 static struct intc_prio_reg irq_prio_registers[] __initdata = { 523 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, 524 IRQ4, IRQ5, IRQ6, IRQ7 } }, 525 }; 526 527 static struct intc_sense_reg irq_sense_registers[] __initdata = { 528 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, 529 IRQ4, IRQ5, IRQ6, IRQ7 } }, 530 }; 531 532 static struct intc_mask_reg irq_ack_registers[] __initdata = { 533 { 0xffd00024, 0, 32, /* INTREQ */ 534 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 535 }; 536 537 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7780-irq", irq_vectors, 538 NULL, irq_mask_registers, irq_prio_registers, 539 irq_sense_registers, irq_ack_registers); 540 541 /* External interrupt pins in IRL mode */ 542 543 static struct intc_vect irl_vectors[] __initdata = { 544 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220), 545 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260), 546 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0), 547 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0), 548 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320), 549 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360), 550 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0), 551 INTC_VECT(IRL_HHHL, 0x3c0), 552 }; 553 554 static struct intc_mask_reg irl3210_mask_registers[] __initdata = { 555 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ 556 { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 557 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 558 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 559 IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, 560 }; 561 562 static struct intc_mask_reg irl7654_mask_registers[] __initdata = { 563 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ 564 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 565 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 566 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 567 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 568 IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, 569 }; 570 571 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors, 572 NULL, irl7654_mask_registers, NULL, NULL); 573 574 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors, 575 NULL, irl3210_mask_registers, NULL, NULL); 576 577 #define INTC_ICR0 0xffd00000 578 #define INTC_INTMSK0 0xffd00044 579 #define INTC_INTMSK1 0xffd00048 580 #define INTC_INTMSK2 0xffd40080 581 #define INTC_INTMSKCLR1 0xffd00068 582 #define INTC_INTMSKCLR2 0xffd40084 583 584 void __init plat_irq_setup(void) 585 { 586 /* disable IRQ7-0 */ 587 __raw_writel(0xff000000, INTC_INTMSK0); 588 589 /* disable IRL3-0 + IRL7-4 */ 590 __raw_writel(0xc0000000, INTC_INTMSK1); 591 __raw_writel(0xfffefffe, INTC_INTMSK2); 592 593 /* select IRL mode for IRL3-0 + IRL7-4 */ 594 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 595 596 /* disable holding function, ie enable "SH-4 Mode" */ 597 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); 598 599 register_intc_controller(&intc_desc); 600 } 601 602 void __init plat_irq_setup_pins(int mode) 603 { 604 switch (mode) { 605 case IRQ_MODE_IRQ: 606 /* select IRQ mode for IRL3-0 + IRL7-4 */ 607 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0); 608 register_intc_controller(&intc_irq_desc); 609 break; 610 case IRQ_MODE_IRL7654: 611 /* enable IRL7-4 but don't provide any masking */ 612 __raw_writel(0x40000000, INTC_INTMSKCLR1); 613 __raw_writel(0x0000fffe, INTC_INTMSKCLR2); 614 break; 615 case IRQ_MODE_IRL3210: 616 /* enable IRL0-3 but don't provide any masking */ 617 __raw_writel(0x80000000, INTC_INTMSKCLR1); 618 __raw_writel(0xfffe0000, INTC_INTMSKCLR2); 619 break; 620 case IRQ_MODE_IRL7654_MASK: 621 /* enable IRL7-4 and mask using cpu intc controller */ 622 __raw_writel(0x40000000, INTC_INTMSKCLR1); 623 register_intc_controller(&intc_irl7654_desc); 624 break; 625 case IRQ_MODE_IRL3210_MASK: 626 /* enable IRL0-3 and mask using cpu intc controller */ 627 __raw_writel(0x80000000, INTC_INTMSKCLR1); 628 register_intc_controller(&intc_irl3210_desc); 629 break; 630 default: 631 BUG(); 632 } 633 } 634