1 /* 2 * SH7763 Setup 3 * 4 * Copyright (C) 2006 Paul Mundt 5 * Copyright (C) 2007 Yoshihiro Shimoda 6 * Copyright (C) 2008, 2009 Nobuhiro Iwamatsu 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 #include <linux/platform_device.h> 13 #include <linux/init.h> 14 #include <linux/serial.h> 15 #include <linux/sh_timer.h> 16 #include <linux/sh_intc.h> 17 #include <linux/io.h> 18 #include <linux/serial_sci.h> 19 #include <linux/usb/ohci_pdriver.h> 20 21 static struct plat_sci_port scif0_platform_data = { 22 .flags = UPF_BOOT_AUTOCONF, 23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 24 .type = PORT_SCIF, 25 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 26 }; 27 28 static struct resource scif0_resources[] = { 29 DEFINE_RES_MEM(0xffe00000, 0x100), 30 DEFINE_RES_IRQ(evt2irq(0x700)), 31 }; 32 33 static struct platform_device scif0_device = { 34 .name = "sh-sci", 35 .id = 0, 36 .resource = scif0_resources, 37 .num_resources = ARRAY_SIZE(scif0_resources), 38 .dev = { 39 .platform_data = &scif0_platform_data, 40 }, 41 }; 42 43 static struct plat_sci_port scif1_platform_data = { 44 .flags = UPF_BOOT_AUTOCONF, 45 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 46 .type = PORT_SCIF, 47 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 48 }; 49 50 static struct resource scif1_resources[] = { 51 DEFINE_RES_MEM(0xffe08000, 0x100), 52 DEFINE_RES_IRQ(evt2irq(0xb80)), 53 }; 54 55 static struct platform_device scif1_device = { 56 .name = "sh-sci", 57 .id = 1, 58 .resource = scif1_resources, 59 .num_resources = ARRAY_SIZE(scif1_resources), 60 .dev = { 61 .platform_data = &scif1_platform_data, 62 }, 63 }; 64 65 static struct plat_sci_port scif2_platform_data = { 66 .flags = UPF_BOOT_AUTOCONF, 67 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 68 .type = PORT_SCIF, 69 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 70 }; 71 72 static struct resource scif2_resources[] = { 73 DEFINE_RES_MEM(0xffe10000, 0x100), 74 DEFINE_RES_IRQ(evt2irq(0xf00)), 75 }; 76 77 static struct platform_device scif2_device = { 78 .name = "sh-sci", 79 .id = 2, 80 .resource = scif2_resources, 81 .num_resources = ARRAY_SIZE(scif2_resources), 82 .dev = { 83 .platform_data = &scif2_platform_data, 84 }, 85 }; 86 87 static struct resource rtc_resources[] = { 88 [0] = { 89 .start = 0xffe80000, 90 .end = 0xffe80000 + 0x58 - 1, 91 .flags = IORESOURCE_IO, 92 }, 93 [1] = { 94 /* Shared Period/Carry/Alarm IRQ */ 95 .start = evt2irq(0x480), 96 .flags = IORESOURCE_IRQ, 97 }, 98 }; 99 100 static struct platform_device rtc_device = { 101 .name = "sh-rtc", 102 .id = -1, 103 .num_resources = ARRAY_SIZE(rtc_resources), 104 .resource = rtc_resources, 105 }; 106 107 static struct resource usb_ohci_resources[] = { 108 [0] = { 109 .start = 0xffec8000, 110 .end = 0xffec80ff, 111 .flags = IORESOURCE_MEM, 112 }, 113 [1] = { 114 .start = evt2irq(0xc60), 115 .end = evt2irq(0xc60), 116 .flags = IORESOURCE_IRQ, 117 }, 118 }; 119 120 static u64 usb_ohci_dma_mask = 0xffffffffUL; 121 122 static struct usb_ohci_pdata usb_ohci_pdata; 123 124 static struct platform_device usb_ohci_device = { 125 .name = "ohci-platform", 126 .id = -1, 127 .dev = { 128 .dma_mask = &usb_ohci_dma_mask, 129 .coherent_dma_mask = 0xffffffff, 130 .platform_data = &usb_ohci_pdata, 131 }, 132 .num_resources = ARRAY_SIZE(usb_ohci_resources), 133 .resource = usb_ohci_resources, 134 }; 135 136 static struct resource usbf_resources[] = { 137 [0] = { 138 .start = 0xffec0000, 139 .end = 0xffec00ff, 140 .flags = IORESOURCE_MEM, 141 }, 142 [1] = { 143 .start = evt2irq(0xc80), 144 .end = evt2irq(0xc80), 145 .flags = IORESOURCE_IRQ, 146 }, 147 }; 148 149 static struct platform_device usbf_device = { 150 .name = "sh_udc", 151 .id = -1, 152 .dev = { 153 .dma_mask = NULL, 154 .coherent_dma_mask = 0xffffffff, 155 }, 156 .num_resources = ARRAY_SIZE(usbf_resources), 157 .resource = usbf_resources, 158 }; 159 160 static struct sh_timer_config tmu0_platform_data = { 161 .channel_offset = 0x04, 162 .timer_bit = 0, 163 .clockevent_rating = 200, 164 }; 165 166 static struct resource tmu0_resources[] = { 167 [0] = { 168 .start = 0xffd80008, 169 .end = 0xffd80013, 170 .flags = IORESOURCE_MEM, 171 }, 172 [1] = { 173 .start = evt2irq(0x580), 174 .flags = IORESOURCE_IRQ, 175 }, 176 }; 177 178 static struct platform_device tmu0_device = { 179 .name = "sh_tmu", 180 .id = 0, 181 .dev = { 182 .platform_data = &tmu0_platform_data, 183 }, 184 .resource = tmu0_resources, 185 .num_resources = ARRAY_SIZE(tmu0_resources), 186 }; 187 188 static struct sh_timer_config tmu1_platform_data = { 189 .channel_offset = 0x10, 190 .timer_bit = 1, 191 .clocksource_rating = 200, 192 }; 193 194 static struct resource tmu1_resources[] = { 195 [0] = { 196 .start = 0xffd80014, 197 .end = 0xffd8001f, 198 .flags = IORESOURCE_MEM, 199 }, 200 [1] = { 201 .start = evt2irq(0x5a0), 202 .flags = IORESOURCE_IRQ, 203 }, 204 }; 205 206 static struct platform_device tmu1_device = { 207 .name = "sh_tmu", 208 .id = 1, 209 .dev = { 210 .platform_data = &tmu1_platform_data, 211 }, 212 .resource = tmu1_resources, 213 .num_resources = ARRAY_SIZE(tmu1_resources), 214 }; 215 216 static struct sh_timer_config tmu2_platform_data = { 217 .channel_offset = 0x1c, 218 .timer_bit = 2, 219 }; 220 221 static struct resource tmu2_resources[] = { 222 [0] = { 223 .start = 0xffd80020, 224 .end = 0xffd8002f, 225 .flags = IORESOURCE_MEM, 226 }, 227 [1] = { 228 .start = evt2irq(0x5c0), 229 .flags = IORESOURCE_IRQ, 230 }, 231 }; 232 233 static struct platform_device tmu2_device = { 234 .name = "sh_tmu", 235 .id = 2, 236 .dev = { 237 .platform_data = &tmu2_platform_data, 238 }, 239 .resource = tmu2_resources, 240 .num_resources = ARRAY_SIZE(tmu2_resources), 241 }; 242 243 static struct sh_timer_config tmu3_platform_data = { 244 .channel_offset = 0x04, 245 .timer_bit = 0, 246 }; 247 248 static struct resource tmu3_resources[] = { 249 [0] = { 250 .start = 0xffd88008, 251 .end = 0xffd88013, 252 .flags = IORESOURCE_MEM, 253 }, 254 [1] = { 255 .start = evt2irq(0xe00), 256 .flags = IORESOURCE_IRQ, 257 }, 258 }; 259 260 static struct platform_device tmu3_device = { 261 .name = "sh_tmu", 262 .id = 3, 263 .dev = { 264 .platform_data = &tmu3_platform_data, 265 }, 266 .resource = tmu3_resources, 267 .num_resources = ARRAY_SIZE(tmu3_resources), 268 }; 269 270 static struct sh_timer_config tmu4_platform_data = { 271 .channel_offset = 0x10, 272 .timer_bit = 1, 273 }; 274 275 static struct resource tmu4_resources[] = { 276 [0] = { 277 .start = 0xffd88014, 278 .end = 0xffd8801f, 279 .flags = IORESOURCE_MEM, 280 }, 281 [1] = { 282 .start = evt2irq(0xe20), 283 .flags = IORESOURCE_IRQ, 284 }, 285 }; 286 287 static struct platform_device tmu4_device = { 288 .name = "sh_tmu", 289 .id = 4, 290 .dev = { 291 .platform_data = &tmu4_platform_data, 292 }, 293 .resource = tmu4_resources, 294 .num_resources = ARRAY_SIZE(tmu4_resources), 295 }; 296 297 static struct sh_timer_config tmu5_platform_data = { 298 .channel_offset = 0x1c, 299 .timer_bit = 2, 300 }; 301 302 static struct resource tmu5_resources[] = { 303 [0] = { 304 .start = 0xffd88020, 305 .end = 0xffd8802b, 306 .flags = IORESOURCE_MEM, 307 }, 308 [1] = { 309 .start = evt2irq(0xe40), 310 .flags = IORESOURCE_IRQ, 311 }, 312 }; 313 314 static struct platform_device tmu5_device = { 315 .name = "sh_tmu", 316 .id = 5, 317 .dev = { 318 .platform_data = &tmu5_platform_data, 319 }, 320 .resource = tmu5_resources, 321 .num_resources = ARRAY_SIZE(tmu5_resources), 322 }; 323 324 static struct platform_device *sh7763_devices[] __initdata = { 325 &scif0_device, 326 &scif1_device, 327 &scif2_device, 328 &tmu0_device, 329 &tmu1_device, 330 &tmu2_device, 331 &tmu3_device, 332 &tmu4_device, 333 &tmu5_device, 334 &rtc_device, 335 &usb_ohci_device, 336 &usbf_device, 337 }; 338 339 static int __init sh7763_devices_setup(void) 340 { 341 return platform_add_devices(sh7763_devices, 342 ARRAY_SIZE(sh7763_devices)); 343 } 344 arch_initcall(sh7763_devices_setup); 345 346 static struct platform_device *sh7763_early_devices[] __initdata = { 347 &scif0_device, 348 &scif1_device, 349 &scif2_device, 350 &tmu0_device, 351 &tmu1_device, 352 &tmu2_device, 353 &tmu3_device, 354 &tmu4_device, 355 &tmu5_device, 356 }; 357 358 void __init plat_early_device_setup(void) 359 { 360 early_platform_add_devices(sh7763_early_devices, 361 ARRAY_SIZE(sh7763_early_devices)); 362 } 363 364 enum { 365 UNUSED = 0, 366 367 /* interrupt sources */ 368 369 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 370 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 371 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 372 IRL_HHLL, IRL_HHLH, IRL_HHHL, 373 374 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 375 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI, 376 HUDI, LCDC, DMAC, SCIF0, IIC0, IIC1, CMT, GETHER, HAC, 377 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5, 378 STIF0, STIF1, SCIF1, SIOF0, SIOF1, SIOF2, 379 USBH, USBF, TPU, PCC, MMCIF, SIM, 380 TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3, 381 SCIF2, GPIO, 382 383 /* interrupt groups */ 384 385 TMU012, TMU345, 386 }; 387 388 static struct intc_vect vectors[] __initdata = { 389 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 390 INTC_VECT(RTC, 0x4c0), 391 INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580), 392 INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0), 393 INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600), 394 INTC_VECT(LCDC, 0x620), 395 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660), 396 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0), 397 INTC_VECT(DMAC, 0x6c0), 398 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720), 399 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760), 400 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0), 401 INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0), 402 INTC_VECT(CMT, 0x900), INTC_VECT(GETHER, 0x920), 403 INTC_VECT(GETHER, 0x940), INTC_VECT(GETHER, 0x960), 404 INTC_VECT(HAC, 0x980), 405 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20), 406 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60), 407 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0), 408 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0), 409 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20), 410 INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60), 411 INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0), 412 INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0), 413 INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20), 414 INTC_VECT(USBH, 0xc60), INTC_VECT(USBF, 0xc80), 415 INTC_VECT(USBF, 0xca0), 416 INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0), 417 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20), 418 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60), 419 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0), 420 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0), 421 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 422 INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60), 423 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0), 424 INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0), 425 INTC_VECT(SCIF2, 0xf00), INTC_VECT(SCIF2, 0xf20), 426 INTC_VECT(SCIF2, 0xf40), INTC_VECT(SCIF2, 0xf60), 427 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0), 428 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0), 429 }; 430 431 static struct intc_group groups[] __initdata = { 432 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), 433 INTC_GROUP(TMU345, TMU3, TMU4, TMU5), 434 }; 435 436 static struct intc_mask_reg mask_registers[] __initdata = { 437 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ 438 { 0, 0, 0, 0, 0, 0, GPIO, 0, 439 SSI0, MMCIF, 0, SIOF0, PCIC5, PCIINTD, PCIINTC, PCIINTB, 440 PCIINTA, PCISERR, HAC, CMT, 0, 0, 0, DMAC, 441 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } }, 442 { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */ 443 { 0, 0, 0, 0, 0, 0, SCIF2, USBF, 444 0, 0, STIF1, STIF0, 0, 0, USBH, GETHER, 445 PCC, 0, 0, ADC, TPU, SIM, SIOF2, SIOF1, 446 LCDC, 0, IIC1, IIC0, SSI3, SSI2, SSI1, 0 } }, 447 }; 448 449 static struct intc_prio_reg prio_registers[] __initdata = { 450 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, 451 TMU2, TMU2_TICPI } }, 452 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } }, 453 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } }, 454 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC, ADC } }, 455 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC, 456 PCISERR, PCIINTA } }, 457 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC, 458 PCIINTD, PCIC5 } }, 459 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF0, USBF, MMCIF, SSI0 } }, 460 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SCIF2, GPIO } }, 461 { 0xffd400a0, 0, 32, 8, /* INT2PRI8 */ { SSI3, SSI2, SSI1, 0 } }, 462 { 0xffd400a4, 0, 32, 8, /* INT2PRI9 */ { LCDC, 0, IIC1, IIC0 } }, 463 { 0xffd400a8, 0, 32, 8, /* INT2PRI10 */ { TPU, SIM, SIOF2, SIOF1 } }, 464 { 0xffd400ac, 0, 32, 8, /* INT2PRI11 */ { PCC } }, 465 { 0xffd400b0, 0, 32, 8, /* INT2PRI12 */ { 0, 0, USBH, GETHER } }, 466 { 0xffd400b4, 0, 32, 8, /* INT2PRI13 */ { 0, 0, STIF1, STIF0 } }, 467 }; 468 469 static DECLARE_INTC_DESC(intc_desc, "sh7763", vectors, groups, 470 mask_registers, prio_registers, NULL); 471 472 /* Support for external interrupt pins in IRQ mode */ 473 static struct intc_vect irq_vectors[] __initdata = { 474 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), 475 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), 476 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380), 477 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200), 478 }; 479 480 static struct intc_mask_reg irq_mask_registers[] __initdata = { 481 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ 482 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 483 }; 484 485 static struct intc_prio_reg irq_prio_registers[] __initdata = { 486 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, 487 IRQ4, IRQ5, IRQ6, IRQ7 } }, 488 }; 489 490 static struct intc_sense_reg irq_sense_registers[] __initdata = { 491 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, 492 IRQ4, IRQ5, IRQ6, IRQ7 } }, 493 }; 494 495 static struct intc_mask_reg irq_ack_registers[] __initdata = { 496 { 0xffd00024, 0, 32, /* INTREQ */ 497 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 498 }; 499 500 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7763-irq", irq_vectors, 501 NULL, irq_mask_registers, irq_prio_registers, 502 irq_sense_registers, irq_ack_registers); 503 504 505 /* External interrupt pins in IRL mode */ 506 static struct intc_vect irl_vectors[] __initdata = { 507 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220), 508 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260), 509 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0), 510 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0), 511 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320), 512 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360), 513 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0), 514 INTC_VECT(IRL_HHHL, 0x3c0), 515 }; 516 517 static struct intc_mask_reg irl3210_mask_registers[] __initdata = { 518 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ 519 { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 520 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 521 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 522 IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, 523 }; 524 525 static struct intc_mask_reg irl7654_mask_registers[] __initdata = { 526 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ 527 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 528 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 529 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 530 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 531 IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, 532 }; 533 534 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7763-irl7654", irl_vectors, 535 NULL, irl7654_mask_registers, NULL, NULL); 536 537 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors, 538 NULL, irl3210_mask_registers, NULL, NULL); 539 540 #define INTC_ICR0 0xffd00000 541 #define INTC_INTMSK0 0xffd00044 542 #define INTC_INTMSK1 0xffd00048 543 #define INTC_INTMSK2 0xffd40080 544 #define INTC_INTMSKCLR1 0xffd00068 545 #define INTC_INTMSKCLR2 0xffd40084 546 547 void __init plat_irq_setup(void) 548 { 549 /* disable IRQ7-0 */ 550 __raw_writel(0xff000000, INTC_INTMSK0); 551 552 /* disable IRL3-0 + IRL7-4 */ 553 __raw_writel(0xc0000000, INTC_INTMSK1); 554 __raw_writel(0xfffefffe, INTC_INTMSK2); 555 556 register_intc_controller(&intc_desc); 557 } 558 559 void __init plat_irq_setup_pins(int mode) 560 { 561 switch (mode) { 562 case IRQ_MODE_IRQ: 563 /* select IRQ mode for IRL3-0 + IRL7-4 */ 564 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0); 565 register_intc_controller(&intc_irq_desc); 566 break; 567 case IRQ_MODE_IRL7654: 568 /* enable IRL7-4 but don't provide any masking */ 569 __raw_writel(0x40000000, INTC_INTMSKCLR1); 570 __raw_writel(0x0000fffe, INTC_INTMSKCLR2); 571 break; 572 case IRQ_MODE_IRL3210: 573 /* enable IRL0-3 but don't provide any masking */ 574 __raw_writel(0x80000000, INTC_INTMSKCLR1); 575 __raw_writel(0xfffe0000, INTC_INTMSKCLR2); 576 break; 577 case IRQ_MODE_IRL7654_MASK: 578 /* enable IRL7-4 and mask using cpu intc controller */ 579 __raw_writel(0x40000000, INTC_INTMSKCLR1); 580 register_intc_controller(&intc_irl7654_desc); 581 break; 582 case IRQ_MODE_IRL3210_MASK: 583 /* enable IRL0-3 and mask using cpu intc controller */ 584 __raw_writel(0x80000000, INTC_INTMSKCLR1); 585 register_intc_controller(&intc_irl3210_desc); 586 break; 587 default: 588 BUG(); 589 } 590 } 591