1 /* 2 * SH7763 Setup 3 * 4 * Copyright (C) 2006 Paul Mundt 5 * Copyright (C) 2007 Yoshihiro Shimoda 6 * Copyright (C) 2008, 2009 Nobuhiro Iwamatsu 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 #include <linux/platform_device.h> 13 #include <linux/init.h> 14 #include <linux/serial.h> 15 #include <linux/sh_timer.h> 16 #include <linux/sh_intc.h> 17 #include <linux/io.h> 18 #include <linux/serial_sci.h> 19 20 static struct plat_sci_port scif0_platform_data = { 21 .mapbase = 0xffe00000, 22 .flags = UPF_BOOT_AUTOCONF, 23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 24 .scbrr_algo_id = SCBRR_ALGO_2, 25 .type = PORT_SCIF, 26 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), 27 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 28 }; 29 30 static struct platform_device scif0_device = { 31 .name = "sh-sci", 32 .id = 0, 33 .dev = { 34 .platform_data = &scif0_platform_data, 35 }, 36 }; 37 38 static struct plat_sci_port scif1_platform_data = { 39 .mapbase = 0xffe08000, 40 .flags = UPF_BOOT_AUTOCONF, 41 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 42 .scbrr_algo_id = SCBRR_ALGO_2, 43 .type = PORT_SCIF, 44 .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)), 45 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 46 }; 47 48 static struct platform_device scif1_device = { 49 .name = "sh-sci", 50 .id = 1, 51 .dev = { 52 .platform_data = &scif1_platform_data, 53 }, 54 }; 55 56 static struct plat_sci_port scif2_platform_data = { 57 .mapbase = 0xffe10000, 58 .flags = UPF_BOOT_AUTOCONF, 59 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 60 .scbrr_algo_id = SCBRR_ALGO_2, 61 .type = PORT_SCIF, 62 .irqs = SCIx_IRQ_MUXED(evt2irq(0xf00)), 63 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 64 }; 65 66 static struct platform_device scif2_device = { 67 .name = "sh-sci", 68 .id = 2, 69 .dev = { 70 .platform_data = &scif2_platform_data, 71 }, 72 }; 73 74 static struct resource rtc_resources[] = { 75 [0] = { 76 .start = 0xffe80000, 77 .end = 0xffe80000 + 0x58 - 1, 78 .flags = IORESOURCE_IO, 79 }, 80 [1] = { 81 /* Shared Period/Carry/Alarm IRQ */ 82 .start = evt2irq(0x480), 83 .flags = IORESOURCE_IRQ, 84 }, 85 }; 86 87 static struct platform_device rtc_device = { 88 .name = "sh-rtc", 89 .id = -1, 90 .num_resources = ARRAY_SIZE(rtc_resources), 91 .resource = rtc_resources, 92 }; 93 94 static struct resource usb_ohci_resources[] = { 95 [0] = { 96 .start = 0xffec8000, 97 .end = 0xffec80ff, 98 .flags = IORESOURCE_MEM, 99 }, 100 [1] = { 101 .start = evt2irq(0xc60), 102 .end = evt2irq(0xc60), 103 .flags = IORESOURCE_IRQ, 104 }, 105 }; 106 107 static u64 usb_ohci_dma_mask = 0xffffffffUL; 108 109 static struct platform_device usb_ohci_device = { 110 .name = "sh_ohci", 111 .id = -1, 112 .dev = { 113 .dma_mask = &usb_ohci_dma_mask, 114 .coherent_dma_mask = 0xffffffff, 115 }, 116 .num_resources = ARRAY_SIZE(usb_ohci_resources), 117 .resource = usb_ohci_resources, 118 }; 119 120 static struct resource usbf_resources[] = { 121 [0] = { 122 .start = 0xffec0000, 123 .end = 0xffec00ff, 124 .flags = IORESOURCE_MEM, 125 }, 126 [1] = { 127 .start = evt2irq(0xc80), 128 .end = evt2irq(0xc80), 129 .flags = IORESOURCE_IRQ, 130 }, 131 }; 132 133 static struct platform_device usbf_device = { 134 .name = "sh_udc", 135 .id = -1, 136 .dev = { 137 .dma_mask = NULL, 138 .coherent_dma_mask = 0xffffffff, 139 }, 140 .num_resources = ARRAY_SIZE(usbf_resources), 141 .resource = usbf_resources, 142 }; 143 144 static struct sh_timer_config tmu0_platform_data = { 145 .channel_offset = 0x04, 146 .timer_bit = 0, 147 .clockevent_rating = 200, 148 }; 149 150 static struct resource tmu0_resources[] = { 151 [0] = { 152 .start = 0xffd80008, 153 .end = 0xffd80013, 154 .flags = IORESOURCE_MEM, 155 }, 156 [1] = { 157 .start = evt2irq(0x580), 158 .flags = IORESOURCE_IRQ, 159 }, 160 }; 161 162 static struct platform_device tmu0_device = { 163 .name = "sh_tmu", 164 .id = 0, 165 .dev = { 166 .platform_data = &tmu0_platform_data, 167 }, 168 .resource = tmu0_resources, 169 .num_resources = ARRAY_SIZE(tmu0_resources), 170 }; 171 172 static struct sh_timer_config tmu1_platform_data = { 173 .channel_offset = 0x10, 174 .timer_bit = 1, 175 .clocksource_rating = 200, 176 }; 177 178 static struct resource tmu1_resources[] = { 179 [0] = { 180 .start = 0xffd80014, 181 .end = 0xffd8001f, 182 .flags = IORESOURCE_MEM, 183 }, 184 [1] = { 185 .start = evt2irq(0x5a0), 186 .flags = IORESOURCE_IRQ, 187 }, 188 }; 189 190 static struct platform_device tmu1_device = { 191 .name = "sh_tmu", 192 .id = 1, 193 .dev = { 194 .platform_data = &tmu1_platform_data, 195 }, 196 .resource = tmu1_resources, 197 .num_resources = ARRAY_SIZE(tmu1_resources), 198 }; 199 200 static struct sh_timer_config tmu2_platform_data = { 201 .channel_offset = 0x1c, 202 .timer_bit = 2, 203 }; 204 205 static struct resource tmu2_resources[] = { 206 [0] = { 207 .start = 0xffd80020, 208 .end = 0xffd8002f, 209 .flags = IORESOURCE_MEM, 210 }, 211 [1] = { 212 .start = evt2irq(0x5c0), 213 .flags = IORESOURCE_IRQ, 214 }, 215 }; 216 217 static struct platform_device tmu2_device = { 218 .name = "sh_tmu", 219 .id = 2, 220 .dev = { 221 .platform_data = &tmu2_platform_data, 222 }, 223 .resource = tmu2_resources, 224 .num_resources = ARRAY_SIZE(tmu2_resources), 225 }; 226 227 static struct sh_timer_config tmu3_platform_data = { 228 .channel_offset = 0x04, 229 .timer_bit = 0, 230 }; 231 232 static struct resource tmu3_resources[] = { 233 [0] = { 234 .start = 0xffd88008, 235 .end = 0xffd88013, 236 .flags = IORESOURCE_MEM, 237 }, 238 [1] = { 239 .start = evt2irq(0xe00), 240 .flags = IORESOURCE_IRQ, 241 }, 242 }; 243 244 static struct platform_device tmu3_device = { 245 .name = "sh_tmu", 246 .id = 3, 247 .dev = { 248 .platform_data = &tmu3_platform_data, 249 }, 250 .resource = tmu3_resources, 251 .num_resources = ARRAY_SIZE(tmu3_resources), 252 }; 253 254 static struct sh_timer_config tmu4_platform_data = { 255 .channel_offset = 0x10, 256 .timer_bit = 1, 257 }; 258 259 static struct resource tmu4_resources[] = { 260 [0] = { 261 .start = 0xffd88014, 262 .end = 0xffd8801f, 263 .flags = IORESOURCE_MEM, 264 }, 265 [1] = { 266 .start = evt2irq(0xe20), 267 .flags = IORESOURCE_IRQ, 268 }, 269 }; 270 271 static struct platform_device tmu4_device = { 272 .name = "sh_tmu", 273 .id = 4, 274 .dev = { 275 .platform_data = &tmu4_platform_data, 276 }, 277 .resource = tmu4_resources, 278 .num_resources = ARRAY_SIZE(tmu4_resources), 279 }; 280 281 static struct sh_timer_config tmu5_platform_data = { 282 .channel_offset = 0x1c, 283 .timer_bit = 2, 284 }; 285 286 static struct resource tmu5_resources[] = { 287 [0] = { 288 .start = 0xffd88020, 289 .end = 0xffd8802b, 290 .flags = IORESOURCE_MEM, 291 }, 292 [1] = { 293 .start = evt2irq(0xe40), 294 .flags = IORESOURCE_IRQ, 295 }, 296 }; 297 298 static struct platform_device tmu5_device = { 299 .name = "sh_tmu", 300 .id = 5, 301 .dev = { 302 .platform_data = &tmu5_platform_data, 303 }, 304 .resource = tmu5_resources, 305 .num_resources = ARRAY_SIZE(tmu5_resources), 306 }; 307 308 static struct platform_device *sh7763_devices[] __initdata = { 309 &scif0_device, 310 &scif1_device, 311 &scif2_device, 312 &tmu0_device, 313 &tmu1_device, 314 &tmu2_device, 315 &tmu3_device, 316 &tmu4_device, 317 &tmu5_device, 318 &rtc_device, 319 &usb_ohci_device, 320 &usbf_device, 321 }; 322 323 static int __init sh7763_devices_setup(void) 324 { 325 return platform_add_devices(sh7763_devices, 326 ARRAY_SIZE(sh7763_devices)); 327 } 328 arch_initcall(sh7763_devices_setup); 329 330 static struct platform_device *sh7763_early_devices[] __initdata = { 331 &scif0_device, 332 &scif1_device, 333 &scif2_device, 334 &tmu0_device, 335 &tmu1_device, 336 &tmu2_device, 337 &tmu3_device, 338 &tmu4_device, 339 &tmu5_device, 340 }; 341 342 void __init plat_early_device_setup(void) 343 { 344 early_platform_add_devices(sh7763_early_devices, 345 ARRAY_SIZE(sh7763_early_devices)); 346 } 347 348 enum { 349 UNUSED = 0, 350 351 /* interrupt sources */ 352 353 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 354 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 355 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 356 IRL_HHLL, IRL_HHLH, IRL_HHHL, 357 358 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 359 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI, 360 HUDI, LCDC, DMAC, SCIF0, IIC0, IIC1, CMT, GETHER, HAC, 361 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5, 362 STIF0, STIF1, SCIF1, SIOF0, SIOF1, SIOF2, 363 USBH, USBF, TPU, PCC, MMCIF, SIM, 364 TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3, 365 SCIF2, GPIO, 366 367 /* interrupt groups */ 368 369 TMU012, TMU345, 370 }; 371 372 static struct intc_vect vectors[] __initdata = { 373 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 374 INTC_VECT(RTC, 0x4c0), 375 INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580), 376 INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0), 377 INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600), 378 INTC_VECT(LCDC, 0x620), 379 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660), 380 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0), 381 INTC_VECT(DMAC, 0x6c0), 382 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720), 383 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760), 384 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0), 385 INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0), 386 INTC_VECT(CMT, 0x900), INTC_VECT(GETHER, 0x920), 387 INTC_VECT(GETHER, 0x940), INTC_VECT(GETHER, 0x960), 388 INTC_VECT(HAC, 0x980), 389 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20), 390 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60), 391 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0), 392 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0), 393 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20), 394 INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60), 395 INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0), 396 INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0), 397 INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20), 398 INTC_VECT(USBH, 0xc60), INTC_VECT(USBF, 0xc80), 399 INTC_VECT(USBF, 0xca0), 400 INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0), 401 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20), 402 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60), 403 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0), 404 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0), 405 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 406 INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60), 407 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0), 408 INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0), 409 INTC_VECT(SCIF2, 0xf00), INTC_VECT(SCIF2, 0xf20), 410 INTC_VECT(SCIF2, 0xf40), INTC_VECT(SCIF2, 0xf60), 411 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0), 412 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0), 413 }; 414 415 static struct intc_group groups[] __initdata = { 416 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), 417 INTC_GROUP(TMU345, TMU3, TMU4, TMU5), 418 }; 419 420 static struct intc_mask_reg mask_registers[] __initdata = { 421 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ 422 { 0, 0, 0, 0, 0, 0, GPIO, 0, 423 SSI0, MMCIF, 0, SIOF0, PCIC5, PCIINTD, PCIINTC, PCIINTB, 424 PCIINTA, PCISERR, HAC, CMT, 0, 0, 0, DMAC, 425 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } }, 426 { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */ 427 { 0, 0, 0, 0, 0, 0, SCIF2, USBF, 428 0, 0, STIF1, STIF0, 0, 0, USBH, GETHER, 429 PCC, 0, 0, ADC, TPU, SIM, SIOF2, SIOF1, 430 LCDC, 0, IIC1, IIC0, SSI3, SSI2, SSI1, 0 } }, 431 }; 432 433 static struct intc_prio_reg prio_registers[] __initdata = { 434 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, 435 TMU2, TMU2_TICPI } }, 436 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } }, 437 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } }, 438 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC, ADC } }, 439 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC, 440 PCISERR, PCIINTA } }, 441 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC, 442 PCIINTD, PCIC5 } }, 443 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF0, USBF, MMCIF, SSI0 } }, 444 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SCIF2, GPIO } }, 445 { 0xffd400a0, 0, 32, 8, /* INT2PRI8 */ { SSI3, SSI2, SSI1, 0 } }, 446 { 0xffd400a4, 0, 32, 8, /* INT2PRI9 */ { LCDC, 0, IIC1, IIC0 } }, 447 { 0xffd400a8, 0, 32, 8, /* INT2PRI10 */ { TPU, SIM, SIOF2, SIOF1 } }, 448 { 0xffd400ac, 0, 32, 8, /* INT2PRI11 */ { PCC } }, 449 { 0xffd400b0, 0, 32, 8, /* INT2PRI12 */ { 0, 0, USBH, GETHER } }, 450 { 0xffd400b4, 0, 32, 8, /* INT2PRI13 */ { 0, 0, STIF1, STIF0 } }, 451 }; 452 453 static DECLARE_INTC_DESC(intc_desc, "sh7763", vectors, groups, 454 mask_registers, prio_registers, NULL); 455 456 /* Support for external interrupt pins in IRQ mode */ 457 static struct intc_vect irq_vectors[] __initdata = { 458 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), 459 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), 460 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380), 461 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200), 462 }; 463 464 static struct intc_mask_reg irq_mask_registers[] __initdata = { 465 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ 466 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 467 }; 468 469 static struct intc_prio_reg irq_prio_registers[] __initdata = { 470 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, 471 IRQ4, IRQ5, IRQ6, IRQ7 } }, 472 }; 473 474 static struct intc_sense_reg irq_sense_registers[] __initdata = { 475 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, 476 IRQ4, IRQ5, IRQ6, IRQ7 } }, 477 }; 478 479 static struct intc_mask_reg irq_ack_registers[] __initdata = { 480 { 0xffd00024, 0, 32, /* INTREQ */ 481 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 482 }; 483 484 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7763-irq", irq_vectors, 485 NULL, irq_mask_registers, irq_prio_registers, 486 irq_sense_registers, irq_ack_registers); 487 488 489 /* External interrupt pins in IRL mode */ 490 static struct intc_vect irl_vectors[] __initdata = { 491 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220), 492 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260), 493 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0), 494 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0), 495 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320), 496 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360), 497 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0), 498 INTC_VECT(IRL_HHHL, 0x3c0), 499 }; 500 501 static struct intc_mask_reg irl3210_mask_registers[] __initdata = { 502 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ 503 { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 504 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 505 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 506 IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, 507 }; 508 509 static struct intc_mask_reg irl7654_mask_registers[] __initdata = { 510 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ 511 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 512 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 513 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 514 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 515 IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, 516 }; 517 518 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7763-irl7654", irl_vectors, 519 NULL, irl7654_mask_registers, NULL, NULL); 520 521 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors, 522 NULL, irl3210_mask_registers, NULL, NULL); 523 524 #define INTC_ICR0 0xffd00000 525 #define INTC_INTMSK0 0xffd00044 526 #define INTC_INTMSK1 0xffd00048 527 #define INTC_INTMSK2 0xffd40080 528 #define INTC_INTMSKCLR1 0xffd00068 529 #define INTC_INTMSKCLR2 0xffd40084 530 531 void __init plat_irq_setup(void) 532 { 533 /* disable IRQ7-0 */ 534 __raw_writel(0xff000000, INTC_INTMSK0); 535 536 /* disable IRL3-0 + IRL7-4 */ 537 __raw_writel(0xc0000000, INTC_INTMSK1); 538 __raw_writel(0xfffefffe, INTC_INTMSK2); 539 540 register_intc_controller(&intc_desc); 541 } 542 543 void __init plat_irq_setup_pins(int mode) 544 { 545 switch (mode) { 546 case IRQ_MODE_IRQ: 547 /* select IRQ mode for IRL3-0 + IRL7-4 */ 548 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0); 549 register_intc_controller(&intc_irq_desc); 550 break; 551 case IRQ_MODE_IRL7654: 552 /* enable IRL7-4 but don't provide any masking */ 553 __raw_writel(0x40000000, INTC_INTMSKCLR1); 554 __raw_writel(0x0000fffe, INTC_INTMSKCLR2); 555 break; 556 case IRQ_MODE_IRL3210: 557 /* enable IRL0-3 but don't provide any masking */ 558 __raw_writel(0x80000000, INTC_INTMSKCLR1); 559 __raw_writel(0xfffe0000, INTC_INTMSKCLR2); 560 break; 561 case IRQ_MODE_IRL7654_MASK: 562 /* enable IRL7-4 and mask using cpu intc controller */ 563 __raw_writel(0x40000000, INTC_INTMSKCLR1); 564 register_intc_controller(&intc_irl7654_desc); 565 break; 566 case IRQ_MODE_IRL3210_MASK: 567 /* enable IRL0-3 and mask using cpu intc controller */ 568 __raw_writel(0x80000000, INTC_INTMSKCLR1); 569 register_intc_controller(&intc_irl3210_desc); 570 break; 571 default: 572 BUG(); 573 } 574 } 575