1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SH7757 Setup 4 * 5 * Copyright (C) 2009, 2011 Renesas Solutions Corp. 6 * 7 * based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt 8 */ 9 #include <linux/platform_device.h> 10 #include <linux/init.h> 11 #include <linux/serial.h> 12 #include <linux/serial_sci.h> 13 #include <linux/io.h> 14 #include <linux/mm.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/sh_timer.h> 17 #include <linux/sh_dma.h> 18 #include <linux/sh_intc.h> 19 #include <linux/usb/ohci_pdriver.h> 20 #include <cpu/dma-register.h> 21 #include <cpu/sh7757.h> 22 23 static struct plat_sci_port scif2_platform_data = { 24 .scscr = SCSCR_REIE, 25 .type = PORT_SCIF, 26 }; 27 28 static struct resource scif2_resources[] = { 29 DEFINE_RES_MEM(0xfe4b0000, 0x100), /* SCIF2 */ 30 DEFINE_RES_IRQ(evt2irq(0x700)), 31 }; 32 33 static struct platform_device scif2_device = { 34 .name = "sh-sci", 35 .id = 0, 36 .resource = scif2_resources, 37 .num_resources = ARRAY_SIZE(scif2_resources), 38 .dev = { 39 .platform_data = &scif2_platform_data, 40 }, 41 }; 42 43 static struct plat_sci_port scif3_platform_data = { 44 .scscr = SCSCR_REIE, 45 .type = PORT_SCIF, 46 }; 47 48 static struct resource scif3_resources[] = { 49 DEFINE_RES_MEM(0xfe4c0000, 0x100), /* SCIF3 */ 50 DEFINE_RES_IRQ(evt2irq(0xb80)), 51 }; 52 53 static struct platform_device scif3_device = { 54 .name = "sh-sci", 55 .id = 1, 56 .resource = scif3_resources, 57 .num_resources = ARRAY_SIZE(scif3_resources), 58 .dev = { 59 .platform_data = &scif3_platform_data, 60 }, 61 }; 62 63 static struct plat_sci_port scif4_platform_data = { 64 .scscr = SCSCR_REIE, 65 .type = PORT_SCIF, 66 }; 67 68 static struct resource scif4_resources[] = { 69 DEFINE_RES_MEM(0xfe4d0000, 0x100), /* SCIF4 */ 70 DEFINE_RES_IRQ(evt2irq(0xf00)), 71 }; 72 73 static struct platform_device scif4_device = { 74 .name = "sh-sci", 75 .id = 2, 76 .resource = scif4_resources, 77 .num_resources = ARRAY_SIZE(scif4_resources), 78 .dev = { 79 .platform_data = &scif4_platform_data, 80 }, 81 }; 82 83 static struct sh_timer_config tmu0_platform_data = { 84 .channels_mask = 3, 85 }; 86 87 static struct resource tmu0_resources[] = { 88 DEFINE_RES_MEM(0xfe430000, 0x20), 89 DEFINE_RES_IRQ(evt2irq(0x580)), 90 DEFINE_RES_IRQ(evt2irq(0x5a0)), 91 }; 92 93 static struct platform_device tmu0_device = { 94 .name = "sh-tmu", 95 .id = 0, 96 .dev = { 97 .platform_data = &tmu0_platform_data, 98 }, 99 .resource = tmu0_resources, 100 .num_resources = ARRAY_SIZE(tmu0_resources), 101 }; 102 103 static struct resource spi0_resources[] = { 104 [0] = { 105 .start = 0xfe002000, 106 .end = 0xfe0020ff, 107 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, 108 }, 109 [1] = { 110 .start = evt2irq(0xcc0), 111 .flags = IORESOURCE_IRQ, 112 }, 113 }; 114 115 /* DMA */ 116 static const struct sh_dmae_slave_config sh7757_dmae0_slaves[] = { 117 { 118 .slave_id = SHDMA_SLAVE_SDHI_TX, 119 .addr = 0x1fe50030, 120 .chcr = SM_INC | RS_ERS | 0x40000000 | 121 TS_INDEX2VAL(XMIT_SZ_16BIT), 122 .mid_rid = 0xc5, 123 }, 124 { 125 .slave_id = SHDMA_SLAVE_SDHI_RX, 126 .addr = 0x1fe50030, 127 .chcr = DM_INC | RS_ERS | 0x40000000 | 128 TS_INDEX2VAL(XMIT_SZ_16BIT), 129 .mid_rid = 0xc6, 130 }, 131 { 132 .slave_id = SHDMA_SLAVE_MMCIF_TX, 133 .addr = 0x1fcb0034, 134 .chcr = SM_INC | RS_ERS | 0x40000000 | 135 TS_INDEX2VAL(XMIT_SZ_32BIT), 136 .mid_rid = 0xd3, 137 }, 138 { 139 .slave_id = SHDMA_SLAVE_MMCIF_RX, 140 .addr = 0x1fcb0034, 141 .chcr = DM_INC | RS_ERS | 0x40000000 | 142 TS_INDEX2VAL(XMIT_SZ_32BIT), 143 .mid_rid = 0xd7, 144 }, 145 }; 146 147 static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = { 148 { 149 .slave_id = SHDMA_SLAVE_SCIF2_TX, 150 .addr = 0x1f4b000c, 151 .chcr = SM_INC | RS_ERS | 0x40000000 | 152 TS_INDEX2VAL(XMIT_SZ_8BIT), 153 .mid_rid = 0x21, 154 }, 155 { 156 .slave_id = SHDMA_SLAVE_SCIF2_RX, 157 .addr = 0x1f4b0014, 158 .chcr = DM_INC | RS_ERS | 0x40000000 | 159 TS_INDEX2VAL(XMIT_SZ_8BIT), 160 .mid_rid = 0x22, 161 }, 162 { 163 .slave_id = SHDMA_SLAVE_SCIF3_TX, 164 .addr = 0x1f4c000c, 165 .chcr = SM_INC | RS_ERS | 0x40000000 | 166 TS_INDEX2VAL(XMIT_SZ_8BIT), 167 .mid_rid = 0x29, 168 }, 169 { 170 .slave_id = SHDMA_SLAVE_SCIF3_RX, 171 .addr = 0x1f4c0014, 172 .chcr = DM_INC | RS_ERS | 0x40000000 | 173 TS_INDEX2VAL(XMIT_SZ_8BIT), 174 .mid_rid = 0x2a, 175 }, 176 { 177 .slave_id = SHDMA_SLAVE_SCIF4_TX, 178 .addr = 0x1f4d000c, 179 .chcr = SM_INC | RS_ERS | 0x40000000 | 180 TS_INDEX2VAL(XMIT_SZ_8BIT), 181 .mid_rid = 0x41, 182 }, 183 { 184 .slave_id = SHDMA_SLAVE_SCIF4_RX, 185 .addr = 0x1f4d0014, 186 .chcr = DM_INC | RS_ERS | 0x40000000 | 187 TS_INDEX2VAL(XMIT_SZ_8BIT), 188 .mid_rid = 0x42, 189 }, 190 { 191 .slave_id = SHDMA_SLAVE_RSPI_TX, 192 .addr = 0xfe480004, 193 .chcr = SM_INC | RS_ERS | 0x40000000 | 194 TS_INDEX2VAL(XMIT_SZ_16BIT), 195 .mid_rid = 0xc1, 196 }, 197 { 198 .slave_id = SHDMA_SLAVE_RSPI_RX, 199 .addr = 0xfe480004, 200 .chcr = DM_INC | RS_ERS | 0x40000000 | 201 TS_INDEX2VAL(XMIT_SZ_16BIT), 202 .mid_rid = 0xc2, 203 }, 204 }; 205 206 static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = { 207 { 208 .slave_id = SHDMA_SLAVE_RIIC0_TX, 209 .addr = 0x1e500012, 210 .chcr = SM_INC | RS_ERS | 0x40000000 | 211 TS_INDEX2VAL(XMIT_SZ_8BIT), 212 .mid_rid = 0x21, 213 }, 214 { 215 .slave_id = SHDMA_SLAVE_RIIC0_RX, 216 .addr = 0x1e500013, 217 .chcr = DM_INC | RS_ERS | 0x40000000 | 218 TS_INDEX2VAL(XMIT_SZ_8BIT), 219 .mid_rid = 0x22, 220 }, 221 { 222 .slave_id = SHDMA_SLAVE_RIIC1_TX, 223 .addr = 0x1e510012, 224 .chcr = SM_INC | RS_ERS | 0x40000000 | 225 TS_INDEX2VAL(XMIT_SZ_8BIT), 226 .mid_rid = 0x29, 227 }, 228 { 229 .slave_id = SHDMA_SLAVE_RIIC1_RX, 230 .addr = 0x1e510013, 231 .chcr = DM_INC | RS_ERS | 0x40000000 | 232 TS_INDEX2VAL(XMIT_SZ_8BIT), 233 .mid_rid = 0x2a, 234 }, 235 { 236 .slave_id = SHDMA_SLAVE_RIIC2_TX, 237 .addr = 0x1e520012, 238 .chcr = SM_INC | RS_ERS | 0x40000000 | 239 TS_INDEX2VAL(XMIT_SZ_8BIT), 240 .mid_rid = 0xa1, 241 }, 242 { 243 .slave_id = SHDMA_SLAVE_RIIC2_RX, 244 .addr = 0x1e520013, 245 .chcr = DM_INC | RS_ERS | 0x40000000 | 246 TS_INDEX2VAL(XMIT_SZ_8BIT), 247 .mid_rid = 0xa2, 248 }, 249 { 250 .slave_id = SHDMA_SLAVE_RIIC3_TX, 251 .addr = 0x1e530012, 252 .chcr = SM_INC | RS_ERS | 0x40000000 | 253 TS_INDEX2VAL(XMIT_SZ_8BIT), 254 .mid_rid = 0xa9, 255 }, 256 { 257 .slave_id = SHDMA_SLAVE_RIIC3_RX, 258 .addr = 0x1e530013, 259 .chcr = DM_INC | RS_ERS | 0x40000000 | 260 TS_INDEX2VAL(XMIT_SZ_8BIT), 261 .mid_rid = 0xaf, 262 }, 263 { 264 .slave_id = SHDMA_SLAVE_RIIC4_TX, 265 .addr = 0x1e540012, 266 .chcr = SM_INC | RS_ERS | 0x40000000 | 267 TS_INDEX2VAL(XMIT_SZ_8BIT), 268 .mid_rid = 0xc5, 269 }, 270 { 271 .slave_id = SHDMA_SLAVE_RIIC4_RX, 272 .addr = 0x1e540013, 273 .chcr = DM_INC | RS_ERS | 0x40000000 | 274 TS_INDEX2VAL(XMIT_SZ_8BIT), 275 .mid_rid = 0xc6, 276 }, 277 }; 278 279 static const struct sh_dmae_slave_config sh7757_dmae3_slaves[] = { 280 { 281 .slave_id = SHDMA_SLAVE_RIIC5_TX, 282 .addr = 0x1e550012, 283 .chcr = SM_INC | RS_ERS | 0x40000000 | 284 TS_INDEX2VAL(XMIT_SZ_8BIT), 285 .mid_rid = 0x21, 286 }, 287 { 288 .slave_id = SHDMA_SLAVE_RIIC5_RX, 289 .addr = 0x1e550013, 290 .chcr = DM_INC | RS_ERS | 0x40000000 | 291 TS_INDEX2VAL(XMIT_SZ_8BIT), 292 .mid_rid = 0x22, 293 }, 294 { 295 .slave_id = SHDMA_SLAVE_RIIC6_TX, 296 .addr = 0x1e560012, 297 .chcr = SM_INC | RS_ERS | 0x40000000 | 298 TS_INDEX2VAL(XMIT_SZ_8BIT), 299 .mid_rid = 0x29, 300 }, 301 { 302 .slave_id = SHDMA_SLAVE_RIIC6_RX, 303 .addr = 0x1e560013, 304 .chcr = DM_INC | RS_ERS | 0x40000000 | 305 TS_INDEX2VAL(XMIT_SZ_8BIT), 306 .mid_rid = 0x2a, 307 }, 308 { 309 .slave_id = SHDMA_SLAVE_RIIC7_TX, 310 .addr = 0x1e570012, 311 .chcr = SM_INC | RS_ERS | 0x40000000 | 312 TS_INDEX2VAL(XMIT_SZ_8BIT), 313 .mid_rid = 0x41, 314 }, 315 { 316 .slave_id = SHDMA_SLAVE_RIIC7_RX, 317 .addr = 0x1e570013, 318 .chcr = DM_INC | RS_ERS | 0x40000000 | 319 TS_INDEX2VAL(XMIT_SZ_8BIT), 320 .mid_rid = 0x42, 321 }, 322 { 323 .slave_id = SHDMA_SLAVE_RIIC8_TX, 324 .addr = 0x1e580012, 325 .chcr = SM_INC | RS_ERS | 0x40000000 | 326 TS_INDEX2VAL(XMIT_SZ_8BIT), 327 .mid_rid = 0x45, 328 }, 329 { 330 .slave_id = SHDMA_SLAVE_RIIC8_RX, 331 .addr = 0x1e580013, 332 .chcr = DM_INC | RS_ERS | 0x40000000 | 333 TS_INDEX2VAL(XMIT_SZ_8BIT), 334 .mid_rid = 0x46, 335 }, 336 { 337 .slave_id = SHDMA_SLAVE_RIIC9_TX, 338 .addr = 0x1e590012, 339 .chcr = SM_INC | RS_ERS | 0x40000000 | 340 TS_INDEX2VAL(XMIT_SZ_8BIT), 341 .mid_rid = 0x51, 342 }, 343 { 344 .slave_id = SHDMA_SLAVE_RIIC9_RX, 345 .addr = 0x1e590013, 346 .chcr = DM_INC | RS_ERS | 0x40000000 | 347 TS_INDEX2VAL(XMIT_SZ_8BIT), 348 .mid_rid = 0x52, 349 }, 350 }; 351 352 static const struct sh_dmae_channel sh7757_dmae_channels[] = { 353 { 354 .offset = 0, 355 .dmars = 0, 356 .dmars_bit = 0, 357 }, { 358 .offset = 0x10, 359 .dmars = 0, 360 .dmars_bit = 8, 361 }, { 362 .offset = 0x20, 363 .dmars = 4, 364 .dmars_bit = 0, 365 }, { 366 .offset = 0x30, 367 .dmars = 4, 368 .dmars_bit = 8, 369 }, { 370 .offset = 0x50, 371 .dmars = 8, 372 .dmars_bit = 0, 373 }, { 374 .offset = 0x60, 375 .dmars = 8, 376 .dmars_bit = 8, 377 } 378 }; 379 380 static const unsigned int ts_shift[] = TS_SHIFT; 381 382 static struct sh_dmae_pdata dma0_platform_data = { 383 .slave = sh7757_dmae0_slaves, 384 .slave_num = ARRAY_SIZE(sh7757_dmae0_slaves), 385 .channel = sh7757_dmae_channels, 386 .channel_num = ARRAY_SIZE(sh7757_dmae_channels), 387 .ts_low_shift = CHCR_TS_LOW_SHIFT, 388 .ts_low_mask = CHCR_TS_LOW_MASK, 389 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 390 .ts_high_mask = CHCR_TS_HIGH_MASK, 391 .ts_shift = ts_shift, 392 .ts_shift_num = ARRAY_SIZE(ts_shift), 393 .dmaor_init = DMAOR_INIT, 394 }; 395 396 static struct sh_dmae_pdata dma1_platform_data = { 397 .slave = sh7757_dmae1_slaves, 398 .slave_num = ARRAY_SIZE(sh7757_dmae1_slaves), 399 .channel = sh7757_dmae_channels, 400 .channel_num = ARRAY_SIZE(sh7757_dmae_channels), 401 .ts_low_shift = CHCR_TS_LOW_SHIFT, 402 .ts_low_mask = CHCR_TS_LOW_MASK, 403 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 404 .ts_high_mask = CHCR_TS_HIGH_MASK, 405 .ts_shift = ts_shift, 406 .ts_shift_num = ARRAY_SIZE(ts_shift), 407 .dmaor_init = DMAOR_INIT, 408 }; 409 410 static struct sh_dmae_pdata dma2_platform_data = { 411 .slave = sh7757_dmae2_slaves, 412 .slave_num = ARRAY_SIZE(sh7757_dmae2_slaves), 413 .channel = sh7757_dmae_channels, 414 .channel_num = ARRAY_SIZE(sh7757_dmae_channels), 415 .ts_low_shift = CHCR_TS_LOW_SHIFT, 416 .ts_low_mask = CHCR_TS_LOW_MASK, 417 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 418 .ts_high_mask = CHCR_TS_HIGH_MASK, 419 .ts_shift = ts_shift, 420 .ts_shift_num = ARRAY_SIZE(ts_shift), 421 .dmaor_init = DMAOR_INIT, 422 }; 423 424 static struct sh_dmae_pdata dma3_platform_data = { 425 .slave = sh7757_dmae3_slaves, 426 .slave_num = ARRAY_SIZE(sh7757_dmae3_slaves), 427 .channel = sh7757_dmae_channels, 428 .channel_num = ARRAY_SIZE(sh7757_dmae_channels), 429 .ts_low_shift = CHCR_TS_LOW_SHIFT, 430 .ts_low_mask = CHCR_TS_LOW_MASK, 431 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 432 .ts_high_mask = CHCR_TS_HIGH_MASK, 433 .ts_shift = ts_shift, 434 .ts_shift_num = ARRAY_SIZE(ts_shift), 435 .dmaor_init = DMAOR_INIT, 436 }; 437 438 /* channel 0 to 5 */ 439 static struct resource sh7757_dmae0_resources[] = { 440 [0] = { 441 /* Channel registers and DMAOR */ 442 .start = 0xff608020, 443 .end = 0xff60808f, 444 .flags = IORESOURCE_MEM, 445 }, 446 [1] = { 447 /* DMARSx */ 448 .start = 0xff609000, 449 .end = 0xff60900b, 450 .flags = IORESOURCE_MEM, 451 }, 452 { 453 .name = "error_irq", 454 .start = evt2irq(0x640), 455 .end = evt2irq(0x640), 456 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 457 }, 458 }; 459 460 /* channel 6 to 11 */ 461 static struct resource sh7757_dmae1_resources[] = { 462 [0] = { 463 /* Channel registers and DMAOR */ 464 .start = 0xff618020, 465 .end = 0xff61808f, 466 .flags = IORESOURCE_MEM, 467 }, 468 [1] = { 469 /* DMARSx */ 470 .start = 0xff619000, 471 .end = 0xff61900b, 472 .flags = IORESOURCE_MEM, 473 }, 474 { 475 .name = "error_irq", 476 .start = evt2irq(0x640), 477 .end = evt2irq(0x640), 478 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 479 }, 480 { 481 /* IRQ for channels 4 */ 482 .start = evt2irq(0x7c0), 483 .end = evt2irq(0x7c0), 484 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 485 }, 486 { 487 /* IRQ for channels 5 */ 488 .start = evt2irq(0x7c0), 489 .end = evt2irq(0x7c0), 490 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 491 }, 492 { 493 /* IRQ for channels 6 */ 494 .start = evt2irq(0xd00), 495 .end = evt2irq(0xd00), 496 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 497 }, 498 { 499 /* IRQ for channels 7 */ 500 .start = evt2irq(0xd00), 501 .end = evt2irq(0xd00), 502 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 503 }, 504 { 505 /* IRQ for channels 8 */ 506 .start = evt2irq(0xd00), 507 .end = evt2irq(0xd00), 508 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 509 }, 510 { 511 /* IRQ for channels 9 */ 512 .start = evt2irq(0xd00), 513 .end = evt2irq(0xd00), 514 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 515 }, 516 { 517 /* IRQ for channels 10 */ 518 .start = evt2irq(0xd00), 519 .end = evt2irq(0xd00), 520 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 521 }, 522 { 523 /* IRQ for channels 11 */ 524 .start = evt2irq(0xd00), 525 .end = evt2irq(0xd00), 526 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 527 }, 528 }; 529 530 /* channel 12 to 17 */ 531 static struct resource sh7757_dmae2_resources[] = { 532 [0] = { 533 /* Channel registers and DMAOR */ 534 .start = 0xff708020, 535 .end = 0xff70808f, 536 .flags = IORESOURCE_MEM, 537 }, 538 [1] = { 539 /* DMARSx */ 540 .start = 0xff709000, 541 .end = 0xff70900b, 542 .flags = IORESOURCE_MEM, 543 }, 544 { 545 .name = "error_irq", 546 .start = evt2irq(0x2a60), 547 .end = evt2irq(0x2a60), 548 .flags = IORESOURCE_IRQ, 549 }, 550 { 551 /* IRQ for channels 12 to 16 */ 552 .start = evt2irq(0x2400), 553 .end = evt2irq(0x2480), 554 .flags = IORESOURCE_IRQ, 555 }, 556 { 557 /* IRQ for channel 17 */ 558 .start = evt2irq(0x24e0), 559 .end = evt2irq(0x24e0), 560 .flags = IORESOURCE_IRQ, 561 }, 562 }; 563 564 /* channel 18 to 23 */ 565 static struct resource sh7757_dmae3_resources[] = { 566 [0] = { 567 /* Channel registers and DMAOR */ 568 .start = 0xff718020, 569 .end = 0xff71808f, 570 .flags = IORESOURCE_MEM, 571 }, 572 [1] = { 573 /* DMARSx */ 574 .start = 0xff719000, 575 .end = 0xff71900b, 576 .flags = IORESOURCE_MEM, 577 }, 578 { 579 .name = "error_irq", 580 .start = evt2irq(0x2a80), 581 .end = evt2irq(0x2a80), 582 .flags = IORESOURCE_IRQ, 583 }, 584 { 585 /* IRQ for channels 18 to 22 */ 586 .start = evt2irq(0x2500), 587 .end = evt2irq(0x2580), 588 .flags = IORESOURCE_IRQ, 589 }, 590 { 591 /* IRQ for channel 23 */ 592 .start = evt2irq(0x2600), 593 .end = evt2irq(0x2600), 594 .flags = IORESOURCE_IRQ, 595 }, 596 }; 597 598 static struct platform_device dma0_device = { 599 .name = "sh-dma-engine", 600 .id = 0, 601 .resource = sh7757_dmae0_resources, 602 .num_resources = ARRAY_SIZE(sh7757_dmae0_resources), 603 .dev = { 604 .platform_data = &dma0_platform_data, 605 }, 606 }; 607 608 static struct platform_device dma1_device = { 609 .name = "sh-dma-engine", 610 .id = 1, 611 .resource = sh7757_dmae1_resources, 612 .num_resources = ARRAY_SIZE(sh7757_dmae1_resources), 613 .dev = { 614 .platform_data = &dma1_platform_data, 615 }, 616 }; 617 618 static struct platform_device dma2_device = { 619 .name = "sh-dma-engine", 620 .id = 2, 621 .resource = sh7757_dmae2_resources, 622 .num_resources = ARRAY_SIZE(sh7757_dmae2_resources), 623 .dev = { 624 .platform_data = &dma2_platform_data, 625 }, 626 }; 627 628 static struct platform_device dma3_device = { 629 .name = "sh-dma-engine", 630 .id = 3, 631 .resource = sh7757_dmae3_resources, 632 .num_resources = ARRAY_SIZE(sh7757_dmae3_resources), 633 .dev = { 634 .platform_data = &dma3_platform_data, 635 }, 636 }; 637 638 static struct platform_device spi0_device = { 639 .name = "sh_spi", 640 .id = 0, 641 .dev = { 642 .dma_mask = NULL, 643 .coherent_dma_mask = 0xffffffff, 644 }, 645 .num_resources = ARRAY_SIZE(spi0_resources), 646 .resource = spi0_resources, 647 }; 648 649 static struct resource spi1_resources[] = { 650 { 651 .start = 0xffd8ee70, 652 .end = 0xffd8eeff, 653 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, 654 }, 655 { 656 .start = evt2irq(0x8c0), 657 .flags = IORESOURCE_IRQ, 658 }, 659 }; 660 661 static struct platform_device spi1_device = { 662 .name = "sh_spi", 663 .id = 1, 664 .num_resources = ARRAY_SIZE(spi1_resources), 665 .resource = spi1_resources, 666 }; 667 668 static struct resource rspi_resources[] = { 669 { 670 .start = 0xfe480000, 671 .end = 0xfe4800ff, 672 .flags = IORESOURCE_MEM, 673 }, 674 { 675 .start = evt2irq(0x1d80), 676 .flags = IORESOURCE_IRQ, 677 }, 678 }; 679 680 static struct platform_device rspi_device = { 681 .name = "rspi", 682 .id = 2, 683 .num_resources = ARRAY_SIZE(rspi_resources), 684 .resource = rspi_resources, 685 }; 686 687 static struct resource usb_ehci_resources[] = { 688 [0] = { 689 .start = 0xfe4f1000, 690 .end = 0xfe4f10ff, 691 .flags = IORESOURCE_MEM, 692 }, 693 [1] = { 694 .start = evt2irq(0x920), 695 .end = evt2irq(0x920), 696 .flags = IORESOURCE_IRQ, 697 }, 698 }; 699 700 static struct platform_device usb_ehci_device = { 701 .name = "sh_ehci", 702 .id = -1, 703 .dev = { 704 .dma_mask = &usb_ehci_device.dev.coherent_dma_mask, 705 .coherent_dma_mask = DMA_BIT_MASK(32), 706 }, 707 .num_resources = ARRAY_SIZE(usb_ehci_resources), 708 .resource = usb_ehci_resources, 709 }; 710 711 static struct resource usb_ohci_resources[] = { 712 [0] = { 713 .start = 0xfe4f1800, 714 .end = 0xfe4f18ff, 715 .flags = IORESOURCE_MEM, 716 }, 717 [1] = { 718 .start = evt2irq(0x920), 719 .end = evt2irq(0x920), 720 .flags = IORESOURCE_IRQ, 721 }, 722 }; 723 724 static struct usb_ohci_pdata usb_ohci_pdata; 725 726 static struct platform_device usb_ohci_device = { 727 .name = "ohci-platform", 728 .id = -1, 729 .dev = { 730 .dma_mask = &usb_ohci_device.dev.coherent_dma_mask, 731 .coherent_dma_mask = DMA_BIT_MASK(32), 732 .platform_data = &usb_ohci_pdata, 733 }, 734 .num_resources = ARRAY_SIZE(usb_ohci_resources), 735 .resource = usb_ohci_resources, 736 }; 737 738 static struct platform_device *sh7757_devices[] __initdata = { 739 &scif2_device, 740 &scif3_device, 741 &scif4_device, 742 &tmu0_device, 743 &dma0_device, 744 &dma1_device, 745 &dma2_device, 746 &dma3_device, 747 &spi0_device, 748 &spi1_device, 749 &rspi_device, 750 &usb_ehci_device, 751 &usb_ohci_device, 752 }; 753 754 static int __init sh7757_devices_setup(void) 755 { 756 return platform_add_devices(sh7757_devices, 757 ARRAY_SIZE(sh7757_devices)); 758 } 759 arch_initcall(sh7757_devices_setup); 760 761 static struct platform_device *sh7757_early_devices[] __initdata = { 762 &scif2_device, 763 &scif3_device, 764 &scif4_device, 765 &tmu0_device, 766 }; 767 768 void __init plat_early_device_setup(void) 769 { 770 early_platform_add_devices(sh7757_early_devices, 771 ARRAY_SIZE(sh7757_early_devices)); 772 } 773 774 enum { 775 UNUSED = 0, 776 777 /* interrupt sources */ 778 779 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, 780 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, 781 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, 782 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 783 784 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH, 785 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH, 786 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH, 787 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 788 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 789 790 SDHI, DVC, 791 IRQ8, IRQ9, IRQ11, IRQ10, IRQ12, IRQ13, IRQ14, IRQ15, 792 TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5, 793 HUDI, 794 ARC4, 795 DMAC0_5, DMAC6_7, DMAC8_11, 796 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, 797 USB0, USB1, 798 JMC, 799 SPI0, SPI1, 800 TMR01, TMR23, TMR45, 801 FRT, 802 LPC, LPC5, LPC6, LPC7, LPC8, 803 PECI0, PECI1, PECI2, PECI3, PECI4, PECI5, 804 ETHERC, 805 ADC0, ADC1, 806 SIM, 807 IIC0_0, IIC0_1, IIC0_2, IIC0_3, 808 IIC1_0, IIC1_1, IIC1_2, IIC1_3, 809 IIC2_0, IIC2_1, IIC2_2, IIC2_3, 810 IIC3_0, IIC3_1, IIC3_2, IIC3_3, 811 IIC4_0, IIC4_1, IIC4_2, IIC4_3, 812 IIC5_0, IIC5_1, IIC5_2, IIC5_3, 813 IIC6_0, IIC6_1, IIC6_2, IIC6_3, 814 IIC7_0, IIC7_1, IIC7_2, IIC7_3, 815 IIC8_0, IIC8_1, IIC8_2, IIC8_3, 816 IIC9_0, IIC9_1, IIC9_2, IIC9_3, 817 ONFICTL, 818 MMC1, MMC2, 819 ECCU, 820 PCIC, 821 G200, 822 RSPI, 823 SGPIO, 824 DMINT12, DMINT13, DMINT14, DMINT15, DMINT16, DMINT17, DMINT18, DMINT19, 825 DMINT20, DMINT21, DMINT22, DMINT23, 826 DDRECC, 827 TSIP, 828 PCIE_BRIDGE, 829 WDT0B, WDT1B, WDT2B, WDT3B, WDT4B, WDT5B, WDT6B, WDT7B, WDT8B, 830 GETHER0, GETHER1, GETHER2, 831 PBIA, PBIB, PBIC, 832 DMAE2, DMAE3, 833 SERMUX2, SERMUX3, 834 835 /* interrupt groups */ 836 837 TMU012, TMU345, 838 }; 839 840 static struct intc_vect vectors[] __initdata = { 841 INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0), 842 INTC_VECT(SDHI, 0x4c0), 843 INTC_VECT(DVC, 0x4e0), 844 INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520), 845 INTC_VECT(IRQ10, 0x540), 846 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), 847 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), 848 INTC_VECT(HUDI, 0x600), 849 INTC_VECT(ARC4, 0x620), 850 INTC_VECT(DMAC0_5, 0x640), INTC_VECT(DMAC0_5, 0x660), 851 INTC_VECT(DMAC0_5, 0x680), INTC_VECT(DMAC0_5, 0x6a0), 852 INTC_VECT(DMAC0_5, 0x6c0), 853 INTC_VECT(IRQ11, 0x6e0), 854 INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720), 855 INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760), 856 INTC_VECT(DMAC0_5, 0x780), INTC_VECT(DMAC0_5, 0x7a0), 857 INTC_VECT(DMAC6_7, 0x7c0), INTC_VECT(DMAC6_7, 0x7e0), 858 INTC_VECT(USB0, 0x840), 859 INTC_VECT(IRQ12, 0x880), 860 INTC_VECT(JMC, 0x8a0), 861 INTC_VECT(SPI1, 0x8c0), 862 INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900), 863 INTC_VECT(USB1, 0x920), 864 INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20), 865 INTC_VECT(TMR45, 0xa40), 866 INTC_VECT(FRT, 0xa80), 867 INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0), 868 INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00), 869 INTC_VECT(LPC, 0xb20), 870 INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60), 871 INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0), 872 INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0), 873 INTC_VECT(PECI0, 0xc00), INTC_VECT(PECI1, 0xc20), 874 INTC_VECT(PECI2, 0xc40), 875 INTC_VECT(IRQ15, 0xc60), 876 INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0), 877 INTC_VECT(SPI0, 0xcc0), 878 INTC_VECT(ADC1, 0xce0), 879 INTC_VECT(DMAC8_11, 0xd00), INTC_VECT(DMAC8_11, 0xd20), 880 INTC_VECT(DMAC8_11, 0xd40), INTC_VECT(DMAC8_11, 0xd60), 881 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0), 882 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0), 883 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 884 INTC_VECT(TMU5, 0xe40), 885 INTC_VECT(ADC0, 0xe60), 886 INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20), 887 INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60), 888 INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420), 889 INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460), 890 INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0), 891 INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520), 892 INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560), 893 INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600), 894 INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640), 895 INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700), 896 INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800), 897 INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840), 898 INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880), 899 INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0), 900 INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900), 901 INTC_VECT(IIC6_2, 0x1920), 902 INTC_VECT(ONFICTL, 0x1960), 903 INTC_VECT(IIC6_3, 0x1980), 904 INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00), 905 INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40), 906 INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80), 907 INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40), 908 INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80), 909 INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20), 910 INTC_VECT(MMC1, 0x1c60), INTC_VECT(MMC2, 0x1c80), 911 INTC_VECT(ECCU, 0x1cc0), 912 INTC_VECT(PCIC, 0x1ce0), 913 INTC_VECT(G200, 0x1d00), 914 INTC_VECT(RSPI, 0x1d80), INTC_VECT(RSPI, 0x1da0), 915 INTC_VECT(RSPI, 0x1dc0), INTC_VECT(RSPI, 0x1de0), 916 INTC_VECT(PECI3, 0x1ec0), INTC_VECT(PECI4, 0x1ee0), 917 INTC_VECT(PECI5, 0x1f00), 918 INTC_VECT(SGPIO, 0x1f80), INTC_VECT(SGPIO, 0x1fa0), 919 INTC_VECT(SGPIO, 0x1fc0), 920 INTC_VECT(DMINT12, 0x2400), INTC_VECT(DMINT13, 0x2420), 921 INTC_VECT(DMINT14, 0x2440), INTC_VECT(DMINT15, 0x2460), 922 INTC_VECT(DMINT16, 0x2480), INTC_VECT(DMINT17, 0x24e0), 923 INTC_VECT(DMINT18, 0x2500), INTC_VECT(DMINT19, 0x2520), 924 INTC_VECT(DMINT20, 0x2540), INTC_VECT(DMINT21, 0x2560), 925 INTC_VECT(DMINT22, 0x2580), INTC_VECT(DMINT23, 0x2600), 926 INTC_VECT(DDRECC, 0x2620), 927 INTC_VECT(TSIP, 0x2640), 928 INTC_VECT(PCIE_BRIDGE, 0x27c0), 929 INTC_VECT(WDT0B, 0x2800), INTC_VECT(WDT1B, 0x2820), 930 INTC_VECT(WDT2B, 0x2840), INTC_VECT(WDT3B, 0x2860), 931 INTC_VECT(WDT4B, 0x2880), INTC_VECT(WDT5B, 0x28a0), 932 INTC_VECT(WDT6B, 0x28c0), INTC_VECT(WDT7B, 0x28e0), 933 INTC_VECT(WDT8B, 0x2900), 934 INTC_VECT(GETHER0, 0x2960), INTC_VECT(GETHER1, 0x2980), 935 INTC_VECT(GETHER2, 0x29a0), 936 INTC_VECT(PBIA, 0x2a00), INTC_VECT(PBIB, 0x2a20), 937 INTC_VECT(PBIC, 0x2a40), 938 INTC_VECT(DMAE2, 0x2a60), INTC_VECT(DMAE3, 0x2a80), 939 INTC_VECT(SERMUX2, 0x2aa0), INTC_VECT(SERMUX3, 0x2b40), 940 INTC_VECT(LPC5, 0x2b60), INTC_VECT(LPC6, 0x2b80), 941 INTC_VECT(LPC7, 0x2c00), INTC_VECT(LPC8, 0x2c20), 942 }; 943 944 static struct intc_group groups[] __initdata = { 945 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), 946 INTC_GROUP(TMU345, TMU3, TMU4, TMU5), 947 }; 948 949 static struct intc_mask_reg mask_registers[] __initdata = { 950 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ 951 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 952 953 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ 954 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, 955 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, 956 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, 957 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0, 958 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH, 959 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH, 960 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH, 961 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } }, 962 963 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ 964 { 0, 0, 0, 0, 0, 0, 0, 0, 965 0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45, 966 TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0_5, 967 HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012 968 } }, 969 970 { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */ 971 { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC, 972 IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1, 973 ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1, 974 ARC4, 0, SPI1, JMC, 0, 0, 0, DVC 975 } }, 976 977 { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */ 978 { IIC4_1, IIC4_2, IIC5_0, ONFICTL, 0, 0, SGPIO, 0, 979 0, G200, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3, 980 IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1, 981 IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, 0, IIC2_2 982 } }, 983 984 { 0xffd100d0, 0xffd100d4, 32, /* INT2MSKR3 / INT2MSKCR3 */ 985 { MMC1, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, PECI5, MMC2, 986 IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2, 987 PCIC, 0, IIC4_0, 0, ECCU, RSPI, 0, IIC9_3, 988 IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1 989 } }, 990 991 { 0xffd20038, 0xffd2003c, 32, /* INT2MSKR4 / INT2MSKCR4 */ 992 { WDT0B, WDT1B, WDT3B, GETHER0, 0, 0, 0, 0, 993 0, 0, 0, LPC7, SERMUX2, DMAE3, DMAE2, PBIC, 994 PBIB, PBIA, GETHER1, DMINT12, DMINT13, DMINT14, DMINT15, TSIP, 995 DMINT23, 0, DMINT21, LPC6, 0, DMINT16, 0, DMINT22 996 } }, 997 998 { 0xffd200d0, 0xffd200d4, 32, /* INT2MSKR5 / INT2MSKCR5 */ 999 { 0, WDT8B, WDT7B, WDT4B, 0, DMINT20, 0, 0, 1000 DMINT19, DMINT18, LPC5, SERMUX3, WDT2B, GETHER2, 0, 0, 1001 0, 0, PCIE_BRIDGE, 0, 0, 0, 0, LPC8, 1002 DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17 1003 } }, 1004 }; 1005 1006 #define INTPRI 0xffd00010 1007 #define INT2PRI0 0xffd40000 1008 #define INT2PRI1 0xffd40004 1009 #define INT2PRI2 0xffd40008 1010 #define INT2PRI3 0xffd4000c 1011 #define INT2PRI4 0xffd40010 1012 #define INT2PRI5 0xffd40014 1013 #define INT2PRI6 0xffd40018 1014 #define INT2PRI7 0xffd4001c 1015 #define INT2PRI8 0xffd400a0 1016 #define INT2PRI9 0xffd400a4 1017 #define INT2PRI10 0xffd400a8 1018 #define INT2PRI11 0xffd400ac 1019 #define INT2PRI12 0xffd400b0 1020 #define INT2PRI13 0xffd400b4 1021 #define INT2PRI14 0xffd400b8 1022 #define INT2PRI15 0xffd400bc 1023 #define INT2PRI16 0xffd10000 1024 #define INT2PRI17 0xffd10004 1025 #define INT2PRI18 0xffd10008 1026 #define INT2PRI19 0xffd1000c 1027 #define INT2PRI20 0xffd10010 1028 #define INT2PRI21 0xffd10014 1029 #define INT2PRI22 0xffd10018 1030 #define INT2PRI23 0xffd1001c 1031 #define INT2PRI24 0xffd100a0 1032 #define INT2PRI25 0xffd100a4 1033 #define INT2PRI26 0xffd100a8 1034 #define INT2PRI27 0xffd100ac 1035 #define INT2PRI28 0xffd100b0 1036 #define INT2PRI29 0xffd100b4 1037 #define INT2PRI30 0xffd100b8 1038 #define INT2PRI31 0xffd100bc 1039 #define INT2PRI32 0xffd20000 1040 #define INT2PRI33 0xffd20004 1041 #define INT2PRI34 0xffd20008 1042 #define INT2PRI35 0xffd2000c 1043 #define INT2PRI36 0xffd20010 1044 #define INT2PRI37 0xffd20014 1045 #define INT2PRI38 0xffd20018 1046 #define INT2PRI39 0xffd2001c 1047 #define INT2PRI40 0xffd200a0 1048 #define INT2PRI41 0xffd200a4 1049 #define INT2PRI42 0xffd200a8 1050 #define INT2PRI43 0xffd200ac 1051 #define INT2PRI44 0xffd200b0 1052 #define INT2PRI45 0xffd200b4 1053 #define INT2PRI46 0xffd200b8 1054 #define INT2PRI47 0xffd200bc 1055 1056 static struct intc_prio_reg prio_registers[] __initdata = { 1057 { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3, 1058 IRQ4, IRQ5, IRQ6, IRQ7 } }, 1059 1060 { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } }, 1061 { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } }, 1062 { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, 0, IRQ8 } }, 1063 { INT2PRI3, 0, 32, 8, { HUDI, DMAC0_5, ADC0, IRQ9 } }, 1064 { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } }, 1065 { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } }, 1066 { INT2PRI6, 0, 32, 8, { PECI0, ETHERC, DMAC8_11, 0 } }, 1067 { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } }, 1068 { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } }, 1069 { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } }, 1070 { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } }, 1071 { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC6_7, IRQ14 } }, 1072 { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } }, 1073 { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } }, 1074 1075 { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } }, 1076 { INT2PRI17, 0, 32, 8, { 0, 0, 0, IIC1_0 } }, 1077 { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } }, 1078 { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } }, 1079 { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } }, 1080 { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } }, 1081 { INT2PRI22, 0, 32, 8, { IIC9_2, MMC2, G200, 0 } }, 1082 { INT2PRI23, 0, 32, 8, { PECI5, SGPIO, IIC3_2, IIC5_1 } }, 1083 { INT2PRI24, 0, 32, 8, { PECI4, PECI3, 0, IIC1_1 } }, 1084 { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } }, 1085 { INT2PRI26, 0, 32, 8, { ECCU, RSPI, 0, IIC9_3 } }, 1086 { INT2PRI27, 0, 32, 8, { PCIC, IIC6_0, IIC4_0, IIC6_1 } }, 1087 { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, MMC1, IIC6_2 } }, 1088 { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } }, 1089 { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, ONFICTL } }, 1090 { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } }, 1091 { INT2PRI32, 0, 32, 8, { DMINT22, 0, 0, 0 } }, 1092 { INT2PRI33, 0, 32, 8, { 0, 0, 0, DMINT16 } }, 1093 { INT2PRI34, 0, 32, 8, { 0, LPC6, DMINT21, DMINT18 } }, 1094 { INT2PRI35, 0, 32, 8, { DMINT23, TSIP, 0, DMINT19 } }, 1095 { INT2PRI36, 0, 32, 8, { DMINT20, GETHER1, PBIA, PBIB } }, 1096 { INT2PRI37, 0, 32, 8, { PBIC, DMAE2, DMAE3, SERMUX2 } }, 1097 { INT2PRI38, 0, 32, 8, { LPC7, 0, 0, 0 } }, 1098 { INT2PRI39, 0, 32, 8, { 0, 0, 0, WDT4B } }, 1099 { INT2PRI40, 0, 32, 8, { 0, 0, 0, DMINT17 } }, 1100 { INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } }, 1101 { INT2PRI42, 0, 32, 8, { 0, 0, 0, LPC8 } }, 1102 { INT2PRI43, 0, 32, 8, { 0, WDT7B, PCIE_BRIDGE, WDT8B } }, 1103 { INT2PRI44, 0, 32, 8, { WDT2B, GETHER2, 0, 0 } }, 1104 { INT2PRI45, 0, 32, 8, { 0, 0, LPC5, SERMUX3 } }, 1105 { INT2PRI46, 0, 32, 8, { WDT0B, WDT1B, WDT3B, GETHER0 } }, 1106 { INT2PRI47, 0, 32, 8, { DMINT12, DMINT13, DMINT14, DMINT15 } }, 1107 }; 1108 1109 static struct intc_sense_reg sense_registers_irq8to15[] __initdata = { 1110 { 0xffd100f8, 32, 2, /* ICR2 */ { IRQ15, IRQ14, IRQ13, IRQ12, 1111 IRQ11, IRQ10, IRQ9, IRQ8 } }, 1112 }; 1113 1114 static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups, 1115 mask_registers, prio_registers, 1116 sense_registers_irq8to15); 1117 1118 /* Support for external interrupt pins in IRQ mode */ 1119 static struct intc_vect vectors_irq0123[] __initdata = { 1120 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240), 1121 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0), 1122 }; 1123 1124 static struct intc_vect vectors_irq4567[] __initdata = { 1125 INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340), 1126 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0), 1127 }; 1128 1129 static struct intc_sense_reg sense_registers[] __initdata = { 1130 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, 1131 IRQ4, IRQ5, IRQ6, IRQ7 } }, 1132 }; 1133 1134 static struct intc_mask_reg ack_registers[] __initdata = { 1135 { 0xffd00024, 0, 32, /* INTREQ */ 1136 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1137 }; 1138 1139 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123", 1140 vectors_irq0123, NULL, mask_registers, 1141 prio_registers, sense_registers, ack_registers); 1142 1143 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567", 1144 vectors_irq4567, NULL, mask_registers, 1145 prio_registers, sense_registers, ack_registers); 1146 1147 /* External interrupt pins in IRL mode */ 1148 static struct intc_vect vectors_irl0123[] __initdata = { 1149 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220), 1150 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260), 1151 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0), 1152 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0), 1153 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320), 1154 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360), 1155 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0), 1156 INTC_VECT(IRL0_HHHL, 0x3c0), 1157 }; 1158 1159 static struct intc_vect vectors_irl4567[] __initdata = { 1160 INTC_VECT(IRL4_LLLL, 0x200), INTC_VECT(IRL4_LLLH, 0x220), 1161 INTC_VECT(IRL4_LLHL, 0x240), INTC_VECT(IRL4_LLHH, 0x260), 1162 INTC_VECT(IRL4_LHLL, 0x280), INTC_VECT(IRL4_LHLH, 0x2a0), 1163 INTC_VECT(IRL4_LHHL, 0x2c0), INTC_VECT(IRL4_LHHH, 0x2e0), 1164 INTC_VECT(IRL4_HLLL, 0x300), INTC_VECT(IRL4_HLLH, 0x320), 1165 INTC_VECT(IRL4_HLHL, 0x340), INTC_VECT(IRL4_HLHH, 0x360), 1166 INTC_VECT(IRL4_HHLL, 0x380), INTC_VECT(IRL4_HHLH, 0x3a0), 1167 INTC_VECT(IRL4_HHHL, 0x3c0), 1168 }; 1169 1170 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123, 1171 NULL, mask_registers, NULL, NULL); 1172 1173 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567, 1174 NULL, mask_registers, NULL, NULL); 1175 1176 #define INTC_ICR0 0xffd00000 1177 #define INTC_INTMSK0 0xffd00044 1178 #define INTC_INTMSK1 0xffd00048 1179 #define INTC_INTMSK2 0xffd40080 1180 #define INTC_INTMSKCLR1 0xffd00068 1181 #define INTC_INTMSKCLR2 0xffd40084 1182 1183 void __init plat_irq_setup(void) 1184 { 1185 /* disable IRQ3-0 + IRQ7-4 */ 1186 __raw_writel(0xff000000, INTC_INTMSK0); 1187 1188 /* disable IRL3-0 + IRL7-4 */ 1189 __raw_writel(0xc0000000, INTC_INTMSK1); 1190 __raw_writel(0xfffefffe, INTC_INTMSK2); 1191 1192 /* select IRL mode for IRL3-0 + IRL7-4 */ 1193 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 1194 1195 /* disable holding function, ie enable "SH-4 Mode" */ 1196 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); 1197 1198 register_intc_controller(&intc_desc); 1199 } 1200 1201 void __init plat_irq_setup_pins(int mode) 1202 { 1203 switch (mode) { 1204 case IRQ_MODE_IRQ7654: 1205 /* select IRQ mode for IRL7-4 */ 1206 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0); 1207 register_intc_controller(&intc_desc_irq4567); 1208 break; 1209 case IRQ_MODE_IRQ3210: 1210 /* select IRQ mode for IRL3-0 */ 1211 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); 1212 register_intc_controller(&intc_desc_irq0123); 1213 break; 1214 case IRQ_MODE_IRL7654: 1215 /* enable IRL7-4 but don't provide any masking */ 1216 __raw_writel(0x40000000, INTC_INTMSKCLR1); 1217 __raw_writel(0x0000fffe, INTC_INTMSKCLR2); 1218 break; 1219 case IRQ_MODE_IRL3210: 1220 /* enable IRL0-3 but don't provide any masking */ 1221 __raw_writel(0x80000000, INTC_INTMSKCLR1); 1222 __raw_writel(0xfffe0000, INTC_INTMSKCLR2); 1223 break; 1224 case IRQ_MODE_IRL7654_MASK: 1225 /* enable IRL7-4 and mask using cpu intc controller */ 1226 __raw_writel(0x40000000, INTC_INTMSKCLR1); 1227 register_intc_controller(&intc_desc_irl4567); 1228 break; 1229 case IRQ_MODE_IRL3210_MASK: 1230 /* enable IRL0-3 and mask using cpu intc controller */ 1231 __raw_writel(0x80000000, INTC_INTMSKCLR1); 1232 register_intc_controller(&intc_desc_irl0123); 1233 break; 1234 default: 1235 BUG(); 1236 } 1237 } 1238 1239 void __init plat_mem_setup(void) 1240 { 1241 } 1242