1 /* 2 * SH7757 Setup 3 * 4 * Copyright (C) 2009 Renesas Solutions Corp. 5 * 6 * based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 #include <linux/platform_device.h> 13 #include <linux/init.h> 14 #include <linux/serial.h> 15 #include <linux/serial_sci.h> 16 #include <linux/io.h> 17 #include <linux/mm.h> 18 #include <linux/sh_timer.h> 19 20 static struct plat_sci_port scif2_platform_data = { 21 .mapbase = 0xfe4b0000, /* SCIF2 */ 22 .flags = UPF_BOOT_AUTOCONF, 23 .type = PORT_SCIF, 24 .irqs = { 40, 40, 40, 40 }, 25 }; 26 27 static struct platform_device scif2_device = { 28 .name = "sh-sci", 29 .id = 2, 30 .dev = { 31 .platform_data = &scif2_platform_data, 32 }, 33 }; 34 35 static struct plat_sci_port scif3_platform_data = { 36 .mapbase = 0xfe4c0000, /* SCIF3 */ 37 .flags = UPF_BOOT_AUTOCONF, 38 .type = PORT_SCIF, 39 .irqs = { 76, 76, 76, 76 }, 40 }; 41 42 static struct platform_device scif3_device = { 43 .name = "sh-sci", 44 .id = 3, 45 .dev = { 46 .platform_data = &scif3_platform_data, 47 }, 48 }; 49 50 static struct plat_sci_port scif4_platform_data = { 51 .mapbase = 0xfe4d0000, /* SCIF4 */ 52 .flags = UPF_BOOT_AUTOCONF, 53 .type = PORT_SCIF, 54 .irqs = { 104, 104, 104, 104 }, 55 }; 56 57 static struct platform_device scif4_device = { 58 .name = "sh-sci", 59 .id = 4, 60 .dev = { 61 .platform_data = &scif4_platform_data, 62 }, 63 }; 64 65 static struct sh_timer_config tmu0_platform_data = { 66 .name = "TMU0", 67 .channel_offset = 0x04, 68 .timer_bit = 0, 69 .clk = "peripheral_clk", 70 .clockevent_rating = 200, 71 }; 72 73 static struct resource tmu0_resources[] = { 74 [0] = { 75 .name = "TMU0", 76 .start = 0xfe430008, 77 .end = 0xfe430013, 78 .flags = IORESOURCE_MEM, 79 }, 80 [1] = { 81 .start = 28, 82 .flags = IORESOURCE_IRQ, 83 }, 84 }; 85 86 static struct platform_device tmu0_device = { 87 .name = "sh_tmu", 88 .id = 0, 89 .dev = { 90 .platform_data = &tmu0_platform_data, 91 }, 92 .resource = tmu0_resources, 93 .num_resources = ARRAY_SIZE(tmu0_resources), 94 }; 95 96 static struct sh_timer_config tmu1_platform_data = { 97 .name = "TMU1", 98 .channel_offset = 0x10, 99 .timer_bit = 1, 100 .clk = "peripheral_clk", 101 .clocksource_rating = 200, 102 }; 103 104 static struct resource tmu1_resources[] = { 105 [0] = { 106 .name = "TMU1", 107 .start = 0xfe430014, 108 .end = 0xfe43001f, 109 .flags = IORESOURCE_MEM, 110 }, 111 [1] = { 112 .start = 29, 113 .flags = IORESOURCE_IRQ, 114 }, 115 }; 116 117 static struct platform_device tmu1_device = { 118 .name = "sh_tmu", 119 .id = 1, 120 .dev = { 121 .platform_data = &tmu1_platform_data, 122 }, 123 .resource = tmu1_resources, 124 .num_resources = ARRAY_SIZE(tmu1_resources), 125 }; 126 127 static struct platform_device *sh7757_devices[] __initdata = { 128 &scif2_device, 129 &scif3_device, 130 &scif4_device, 131 &tmu0_device, 132 &tmu1_device, 133 }; 134 135 static int __init sh7757_devices_setup(void) 136 { 137 return platform_add_devices(sh7757_devices, 138 ARRAY_SIZE(sh7757_devices)); 139 } 140 arch_initcall(sh7757_devices_setup); 141 142 static struct platform_device *sh7757_early_devices[] __initdata = { 143 &scif2_device, 144 &scif3_device, 145 &scif4_device, 146 &tmu0_device, 147 &tmu1_device, 148 }; 149 150 void __init plat_early_device_setup(void) 151 { 152 early_platform_add_devices(sh7757_early_devices, 153 ARRAY_SIZE(sh7757_early_devices)); 154 } 155 156 enum { 157 UNUSED = 0, 158 159 /* interrupt sources */ 160 161 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, 162 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, 163 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, 164 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 165 166 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH, 167 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH, 168 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH, 169 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 170 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 171 172 SDHI, 173 DVC, 174 IRQ8, IRQ9, IRQ10, 175 WDT0, 176 TMU0, TMU1, TMU2, TMU2_TICPI, 177 HUDI, 178 179 ARC4, 180 DMAC0, 181 IRQ11, 182 SCIF2, 183 DMAC1_6, 184 USB0, 185 IRQ12, 186 JMC, 187 SPI1, 188 IRQ13, IRQ14, 189 USB1, 190 TMR01, TMR23, TMR45, 191 WDT1, 192 FRT, 193 LPC, 194 SCIF0, SCIF1, SCIF3, 195 PECI0I, PECI1I, PECI2I, 196 IRQ15, 197 ETHERC, 198 SPI0, 199 ADC1, 200 DMAC1_8, 201 SIM, 202 TMU3, TMU4, TMU5, 203 ADC0, 204 SCIF4, 205 IIC0_0, IIC0_1, IIC0_2, IIC0_3, 206 IIC1_0, IIC1_1, IIC1_2, IIC1_3, 207 IIC2_0, IIC2_1, IIC2_2, IIC2_3, 208 IIC3_0, IIC3_1, IIC3_2, IIC3_3, 209 IIC4_0, IIC4_1, IIC4_2, IIC4_3, 210 IIC5_0, IIC5_1, IIC5_2, IIC5_3, 211 IIC6_0, IIC6_1, IIC6_2, IIC6_3, 212 IIC7_0, IIC7_1, IIC7_2, IIC7_3, 213 IIC8_0, IIC8_1, IIC8_2, IIC8_3, 214 IIC9_0, IIC9_1, IIC9_2, IIC9_3, 215 PCIINTA, 216 PCIE, 217 SGPIO, 218 219 /* interrupt groups */ 220 221 TMU012, TMU345, 222 }; 223 224 static struct intc_vect vectors[] __initdata = { 225 INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0), 226 INTC_VECT(SDHI, 0x4c0), 227 INTC_VECT(DVC, 0x4e0), 228 INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520), 229 INTC_VECT(IRQ10, 0x540), 230 INTC_VECT(WDT0, 0x560), 231 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), 232 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), 233 INTC_VECT(HUDI, 0x600), 234 INTC_VECT(ARC4, 0x620), 235 INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660), 236 INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0), 237 INTC_VECT(DMAC0, 0x6c0), 238 INTC_VECT(IRQ11, 0x6e0), 239 INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720), 240 INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760), 241 INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0), 242 INTC_VECT(DMAC1_6, 0x7c0), INTC_VECT(DMAC1_6, 0x7e0), 243 INTC_VECT(USB0, 0x840), 244 INTC_VECT(IRQ12, 0x880), 245 INTC_VECT(JMC, 0x8a0), 246 INTC_VECT(SPI1, 0x8c0), 247 INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900), 248 INTC_VECT(USB1, 0x920), 249 INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20), 250 INTC_VECT(TMR45, 0xa40), 251 INTC_VECT(WDT1, 0xa60), 252 INTC_VECT(FRT, 0xa80), 253 INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0), 254 INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00), 255 INTC_VECT(LPC, 0xb20), 256 INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60), 257 INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0), 258 INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0), 259 INTC_VECT(PECI0I, 0xc00), INTC_VECT(PECI1I, 0xc20), 260 INTC_VECT(PECI2I, 0xc40), 261 INTC_VECT(IRQ15, 0xc60), 262 INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0), 263 INTC_VECT(SPI0, 0xcc0), 264 INTC_VECT(ADC1, 0xce0), 265 INTC_VECT(DMAC1_8, 0xd00), INTC_VECT(DMAC1_8, 0xd20), 266 INTC_VECT(DMAC1_8, 0xd40), INTC_VECT(DMAC1_8, 0xd60), 267 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0), 268 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0), 269 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 270 INTC_VECT(TMU5, 0xe40), 271 INTC_VECT(ADC0, 0xe60), 272 INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20), 273 INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60), 274 INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420), 275 INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460), 276 INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0), 277 INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520), 278 INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560), 279 INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600), 280 INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640), 281 INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700), 282 INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800), 283 INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840), 284 INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880), 285 INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0), 286 INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900), 287 INTC_VECT(IIC6_2, 0x1920), INTC_VECT(IIC6_3, 0x1980), 288 INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00), 289 INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40), 290 INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80), 291 INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40), 292 INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80), 293 INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20), 294 INTC_VECT(PCIINTA, 0x1ce0), 295 INTC_VECT(PCIE, 0x1e00), 296 INTC_VECT(SGPIO, 0x1f80), 297 INTC_VECT(SGPIO, 0x1fa0), 298 }; 299 300 static struct intc_group groups[] __initdata = { 301 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), 302 INTC_GROUP(TMU345, TMU3, TMU4, TMU5), 303 }; 304 305 static struct intc_mask_reg mask_registers[] __initdata = { 306 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ 307 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 308 309 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ 310 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, 311 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, 312 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, 313 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0, 314 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH, 315 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH, 316 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH, 317 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } }, 318 319 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ 320 { 0, 0, 0, 0, 0, 0, 0, 0, 321 0, DMAC1_8, 0, PECI0I, LPC, FRT, WDT1, TMR45, 322 TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0, 323 HUDI, 0, WDT0, SCIF3, SCIF2, SDHI, TMU345, TMU012 324 } }, 325 326 { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */ 327 { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC, 328 IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1, 329 ADC1, 0, DMAC1_6, ADC0, SPI0, SIM, PECI2I, PECI1I, 330 ARC4, 0, SPI1, JMC, 0, 0, 0, DVC 331 } }, 332 333 { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */ 334 { IIC4_1, IIC4_2, IIC5_0, 0, 0, 0, SGPIO, 0, 335 0, 0, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3, 336 IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1, 337 IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, PCIE, IIC2_2 338 } }, 339 340 { 0xffd100d0, 0xff1400d4, 32, /* INT2MSKR3 / INT2MSKCR4 */ 341 { 0, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, 0, 0, 342 IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2, 343 PCIINTA, 0, IIC4_0, 0, 0, 0, 0, IIC9_3, 344 IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1 345 } }, 346 }; 347 348 #define INTPRI 0xffd00010 349 #define INT2PRI0 0xffd40000 350 #define INT2PRI1 0xffd40004 351 #define INT2PRI2 0xffd40008 352 #define INT2PRI3 0xffd4000c 353 #define INT2PRI4 0xffd40010 354 #define INT2PRI5 0xffd40014 355 #define INT2PRI6 0xffd40018 356 #define INT2PRI7 0xffd4001c 357 #define INT2PRI8 0xffd400a0 358 #define INT2PRI9 0xffd400a4 359 #define INT2PRI10 0xffd400a8 360 #define INT2PRI11 0xffd400ac 361 #define INT2PRI12 0xffd400b0 362 #define INT2PRI13 0xffd400b4 363 #define INT2PRI14 0xffd400b8 364 #define INT2PRI15 0xffd400bc 365 #define INT2PRI16 0xffd10000 366 #define INT2PRI17 0xffd10004 367 #define INT2PRI18 0xffd10008 368 #define INT2PRI19 0xffd1000c 369 #define INT2PRI20 0xffd10010 370 #define INT2PRI21 0xffd10014 371 #define INT2PRI22 0xffd10018 372 #define INT2PRI23 0xffd1001c 373 #define INT2PRI24 0xffd100a0 374 #define INT2PRI25 0xffd100a4 375 #define INT2PRI26 0xffd100a8 376 #define INT2PRI27 0xffd100ac 377 #define INT2PRI28 0xffd100b0 378 #define INT2PRI29 0xffd100b4 379 #define INT2PRI30 0xffd100b8 380 #define INT2PRI31 0xffd100bc 381 382 static struct intc_prio_reg prio_registers[] __initdata = { 383 { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3, 384 IRQ4, IRQ5, IRQ6, IRQ7 } }, 385 386 { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } }, 387 { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } }, 388 { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, WDT0, IRQ8 } }, 389 { INT2PRI3, 0, 32, 8, { HUDI, DMAC0, ADC0, IRQ9 } }, 390 { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } }, 391 { INT2PRI5, 0, 32, 8, { TMR45, WDT1, FRT, LPC } }, 392 { INT2PRI6, 0, 32, 8, { PECI0I, ETHERC, DMAC1_8, 0 } }, 393 { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } }, 394 { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } }, 395 { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } }, 396 { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2I, PECI1I } }, 397 { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC1_6, IRQ14 } }, 398 { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } }, 399 { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } }, 400 401 { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } }, 402 { INT2PRI17, 0, 32, 8, { PCIE, 0, 0, IIC1_0 } }, 403 { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } }, 404 { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } }, 405 { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } }, 406 { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } }, 407 { INT2PRI22, 0, 32, 8, { IIC9_2, 0, 0, 0 } }, 408 { INT2PRI23, 0, 32, 8, { 0, SGPIO, IIC3_2, IIC5_1 } }, 409 { INT2PRI24, 0, 32, 8, { 0, 0, 0, IIC1_1 } }, 410 { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } }, 411 { INT2PRI26, 0, 32, 8, { 0, 0, 0, IIC9_3 } }, 412 { INT2PRI27, 0, 32, 8, { PCIINTA, IIC6_0, IIC4_0, IIC6_1 } }, 413 { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, 0, IIC6_2 } }, 414 { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } }, 415 { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, 0 } }, 416 { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } }, 417 }; 418 419 static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups, 420 mask_registers, prio_registers, NULL); 421 422 /* Support for external interrupt pins in IRQ mode */ 423 static struct intc_vect vectors_irq0123[] __initdata = { 424 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), 425 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), 426 }; 427 428 static struct intc_vect vectors_irq4567[] __initdata = { 429 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380), 430 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200), 431 }; 432 433 static struct intc_sense_reg sense_registers[] __initdata = { 434 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, 435 IRQ4, IRQ5, IRQ6, IRQ7 } }, 436 }; 437 438 static struct intc_mask_reg ack_registers[] __initdata = { 439 { 0xffd00024, 0, 32, /* INTREQ */ 440 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 441 }; 442 443 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123", 444 vectors_irq0123, NULL, mask_registers, 445 prio_registers, sense_registers, ack_registers); 446 447 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567", 448 vectors_irq4567, NULL, mask_registers, 449 prio_registers, sense_registers, ack_registers); 450 451 /* External interrupt pins in IRL mode */ 452 static struct intc_vect vectors_irl0123[] __initdata = { 453 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220), 454 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260), 455 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0), 456 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0), 457 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320), 458 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360), 459 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0), 460 INTC_VECT(IRL0_HHHL, 0x3c0), 461 }; 462 463 static struct intc_vect vectors_irl4567[] __initdata = { 464 INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20), 465 INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60), 466 INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0), 467 INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0), 468 INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20), 469 INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60), 470 INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0), 471 INTC_VECT(IRL4_HHHL, 0xcc0), 472 }; 473 474 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123, 475 NULL, mask_registers, NULL, NULL); 476 477 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567, 478 NULL, mask_registers, NULL, NULL); 479 480 #define INTC_ICR0 0xffd00000 481 #define INTC_INTMSK0 0xffd00044 482 #define INTC_INTMSK1 0xffd00048 483 #define INTC_INTMSK2 0xffd40080 484 #define INTC_INTMSKCLR1 0xffd00068 485 #define INTC_INTMSKCLR2 0xffd40084 486 487 void __init plat_irq_setup(void) 488 { 489 /* disable IRQ3-0 + IRQ7-4 */ 490 ctrl_outl(0xff000000, INTC_INTMSK0); 491 492 /* disable IRL3-0 + IRL7-4 */ 493 ctrl_outl(0xc0000000, INTC_INTMSK1); 494 ctrl_outl(0xfffefffe, INTC_INTMSK2); 495 496 /* select IRL mode for IRL3-0 + IRL7-4 */ 497 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 498 499 /* disable holding function, ie enable "SH-4 Mode" */ 500 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0); 501 502 register_intc_controller(&intc_desc); 503 } 504 505 void __init plat_irq_setup_pins(int mode) 506 { 507 switch (mode) { 508 case IRQ_MODE_IRQ7654: 509 /* select IRQ mode for IRL7-4 */ 510 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0); 511 register_intc_controller(&intc_desc_irq4567); 512 break; 513 case IRQ_MODE_IRQ3210: 514 /* select IRQ mode for IRL3-0 */ 515 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0); 516 register_intc_controller(&intc_desc_irq0123); 517 break; 518 case IRQ_MODE_IRL7654: 519 /* enable IRL7-4 but don't provide any masking */ 520 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 521 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); 522 break; 523 case IRQ_MODE_IRL3210: 524 /* enable IRL0-3 but don't provide any masking */ 525 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 526 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); 527 break; 528 case IRQ_MODE_IRL7654_MASK: 529 /* enable IRL7-4 and mask using cpu intc controller */ 530 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 531 register_intc_controller(&intc_desc_irl4567); 532 break; 533 case IRQ_MODE_IRL3210_MASK: 534 /* enable IRL0-3 and mask using cpu intc controller */ 535 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 536 register_intc_controller(&intc_desc_irl0123); 537 break; 538 default: 539 BUG(); 540 } 541 } 542 543 void __init plat_mem_setup(void) 544 { 545 } 546