1 /* 2 * SH7757 Setup 3 * 4 * Copyright (C) 2009 Renesas Solutions Corp. 5 * 6 * based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 #include <linux/platform_device.h> 13 #include <linux/init.h> 14 #include <linux/serial.h> 15 #include <linux/serial_sci.h> 16 #include <linux/io.h> 17 #include <linux/mm.h> 18 #include <linux/sh_timer.h> 19 20 static struct plat_sci_port scif2_platform_data = { 21 .mapbase = 0xfe4b0000, /* SCIF2 */ 22 .flags = UPF_BOOT_AUTOCONF, 23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 24 .scbrr_algo_id = SCBRR_ALGO_2, 25 .type = PORT_SCIF, 26 .irqs = { 40, 40, 40, 40 }, 27 }; 28 29 static struct platform_device scif2_device = { 30 .name = "sh-sci", 31 .id = 0, 32 .dev = { 33 .platform_data = &scif2_platform_data, 34 }, 35 }; 36 37 static struct plat_sci_port scif3_platform_data = { 38 .mapbase = 0xfe4c0000, /* SCIF3 */ 39 .flags = UPF_BOOT_AUTOCONF, 40 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 41 .scbrr_algo_id = SCBRR_ALGO_2, 42 .type = PORT_SCIF, 43 .irqs = { 76, 76, 76, 76 }, 44 }; 45 46 static struct platform_device scif3_device = { 47 .name = "sh-sci", 48 .id = 1, 49 .dev = { 50 .platform_data = &scif3_platform_data, 51 }, 52 }; 53 54 static struct plat_sci_port scif4_platform_data = { 55 .mapbase = 0xfe4d0000, /* SCIF4 */ 56 .flags = UPF_BOOT_AUTOCONF, 57 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 58 .scbrr_algo_id = SCBRR_ALGO_2, 59 .type = PORT_SCIF, 60 .irqs = { 104, 104, 104, 104 }, 61 }; 62 63 static struct platform_device scif4_device = { 64 .name = "sh-sci", 65 .id = 2, 66 .dev = { 67 .platform_data = &scif4_platform_data, 68 }, 69 }; 70 71 static struct sh_timer_config tmu0_platform_data = { 72 .channel_offset = 0x04, 73 .timer_bit = 0, 74 .clockevent_rating = 200, 75 }; 76 77 static struct resource tmu0_resources[] = { 78 [0] = { 79 .start = 0xfe430008, 80 .end = 0xfe430013, 81 .flags = IORESOURCE_MEM, 82 }, 83 [1] = { 84 .start = 28, 85 .flags = IORESOURCE_IRQ, 86 }, 87 }; 88 89 static struct platform_device tmu0_device = { 90 .name = "sh_tmu", 91 .id = 0, 92 .dev = { 93 .platform_data = &tmu0_platform_data, 94 }, 95 .resource = tmu0_resources, 96 .num_resources = ARRAY_SIZE(tmu0_resources), 97 }; 98 99 static struct sh_timer_config tmu1_platform_data = { 100 .channel_offset = 0x10, 101 .timer_bit = 1, 102 .clocksource_rating = 200, 103 }; 104 105 static struct resource tmu1_resources[] = { 106 [0] = { 107 .start = 0xfe430014, 108 .end = 0xfe43001f, 109 .flags = IORESOURCE_MEM, 110 }, 111 [1] = { 112 .start = 29, 113 .flags = IORESOURCE_IRQ, 114 }, 115 }; 116 117 static struct platform_device tmu1_device = { 118 .name = "sh_tmu", 119 .id = 1, 120 .dev = { 121 .platform_data = &tmu1_platform_data, 122 }, 123 .resource = tmu1_resources, 124 .num_resources = ARRAY_SIZE(tmu1_resources), 125 }; 126 127 static struct platform_device *sh7757_devices[] __initdata = { 128 &scif2_device, 129 &scif3_device, 130 &scif4_device, 131 &tmu0_device, 132 &tmu1_device, 133 }; 134 135 static int __init sh7757_devices_setup(void) 136 { 137 return platform_add_devices(sh7757_devices, 138 ARRAY_SIZE(sh7757_devices)); 139 } 140 arch_initcall(sh7757_devices_setup); 141 142 static struct platform_device *sh7757_early_devices[] __initdata = { 143 &scif2_device, 144 &scif3_device, 145 &scif4_device, 146 &tmu0_device, 147 &tmu1_device, 148 }; 149 150 void __init plat_early_device_setup(void) 151 { 152 early_platform_add_devices(sh7757_early_devices, 153 ARRAY_SIZE(sh7757_early_devices)); 154 } 155 156 enum { 157 UNUSED = 0, 158 159 /* interrupt sources */ 160 161 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, 162 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, 163 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, 164 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 165 166 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH, 167 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH, 168 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH, 169 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 170 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 171 172 SDHI, DVC, 173 IRQ8, IRQ9, IRQ11, IRQ10, IRQ12, IRQ13, IRQ14, IRQ15, 174 TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5, 175 HUDI, 176 ARC4, 177 DMAC0_5, DMAC6_7, DMAC8_11, 178 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, 179 USB0, USB1, 180 JMC, 181 SPI0, SPI1, 182 TMR01, TMR23, TMR45, 183 FRT, 184 LPC, LPC5, LPC6, LPC7, LPC8, 185 PECI0, PECI1, PECI2, PECI3, PECI4, PECI5, 186 ETHERC, 187 ADC0, ADC1, 188 SIM, 189 IIC0_0, IIC0_1, IIC0_2, IIC0_3, 190 IIC1_0, IIC1_1, IIC1_2, IIC1_3, 191 IIC2_0, IIC2_1, IIC2_2, IIC2_3, 192 IIC3_0, IIC3_1, IIC3_2, IIC3_3, 193 IIC4_0, IIC4_1, IIC4_2, IIC4_3, 194 IIC5_0, IIC5_1, IIC5_2, IIC5_3, 195 IIC6_0, IIC6_1, IIC6_2, IIC6_3, 196 IIC7_0, IIC7_1, IIC7_2, IIC7_3, 197 IIC8_0, IIC8_1, IIC8_2, IIC8_3, 198 IIC9_0, IIC9_1, IIC9_2, IIC9_3, 199 ONFICTL, 200 MMC1, MMC2, 201 ECCU, 202 PCIC, 203 G200, 204 RSPI, 205 SGPIO, 206 DMINT12, DMINT13, DMINT14, DMINT15, DMINT16, DMINT17, DMINT18, DMINT19, 207 DMINT20, DMINT21, DMINT22, DMINT23, 208 DDRECC, 209 TSIP, 210 PCIE_BRIDGE, 211 WDT0B, WDT1B, WDT2B, WDT3B, WDT4B, WDT5B, WDT6B, WDT7B, WDT8B, 212 GETHER0, GETHER1, GETHER2, 213 PBIA, PBIB, PBIC, 214 DMAE2, DMAE3, 215 SERMUX2, SERMUX3, 216 217 /* interrupt groups */ 218 219 TMU012, TMU345, 220 }; 221 222 static struct intc_vect vectors[] __initdata = { 223 INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0), 224 INTC_VECT(SDHI, 0x4c0), 225 INTC_VECT(DVC, 0x4e0), 226 INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520), 227 INTC_VECT(IRQ10, 0x540), 228 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), 229 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), 230 INTC_VECT(HUDI, 0x600), 231 INTC_VECT(ARC4, 0x620), 232 INTC_VECT(DMAC0_5, 0x640), INTC_VECT(DMAC0_5, 0x660), 233 INTC_VECT(DMAC0_5, 0x680), INTC_VECT(DMAC0_5, 0x6a0), 234 INTC_VECT(DMAC0_5, 0x6c0), 235 INTC_VECT(IRQ11, 0x6e0), 236 INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720), 237 INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760), 238 INTC_VECT(DMAC0_5, 0x780), INTC_VECT(DMAC0_5, 0x7a0), 239 INTC_VECT(DMAC6_7, 0x7c0), INTC_VECT(DMAC6_7, 0x7e0), 240 INTC_VECT(USB0, 0x840), 241 INTC_VECT(IRQ12, 0x880), 242 INTC_VECT(JMC, 0x8a0), 243 INTC_VECT(SPI1, 0x8c0), 244 INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900), 245 INTC_VECT(USB1, 0x920), 246 INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20), 247 INTC_VECT(TMR45, 0xa40), 248 INTC_VECT(FRT, 0xa80), 249 INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0), 250 INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00), 251 INTC_VECT(LPC, 0xb20), 252 INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60), 253 INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0), 254 INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0), 255 INTC_VECT(PECI0, 0xc00), INTC_VECT(PECI1, 0xc20), 256 INTC_VECT(PECI2, 0xc40), 257 INTC_VECT(IRQ15, 0xc60), 258 INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0), 259 INTC_VECT(SPI0, 0xcc0), 260 INTC_VECT(ADC1, 0xce0), 261 INTC_VECT(DMAC8_11, 0xd00), INTC_VECT(DMAC8_11, 0xd20), 262 INTC_VECT(DMAC8_11, 0xd40), INTC_VECT(DMAC8_11, 0xd60), 263 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0), 264 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0), 265 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 266 INTC_VECT(TMU5, 0xe40), 267 INTC_VECT(ADC0, 0xe60), 268 INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20), 269 INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60), 270 INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420), 271 INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460), 272 INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0), 273 INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520), 274 INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560), 275 INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600), 276 INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640), 277 INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700), 278 INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800), 279 INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840), 280 INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880), 281 INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0), 282 INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900), 283 INTC_VECT(IIC6_2, 0x1920), 284 INTC_VECT(ONFICTL, 0x1960), 285 INTC_VECT(IIC6_3, 0x1980), 286 INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00), 287 INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40), 288 INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80), 289 INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40), 290 INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80), 291 INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20), 292 INTC_VECT(MMC1, 0x1c60), INTC_VECT(MMC2, 0x1c80), 293 INTC_VECT(ECCU, 0x1cc0), 294 INTC_VECT(PCIC, 0x1ce0), 295 INTC_VECT(G200, 0x1d00), 296 INTC_VECT(RSPI, 0x1d80), INTC_VECT(RSPI, 0x1da0), 297 INTC_VECT(RSPI, 0x1dc0), INTC_VECT(RSPI, 0x1de0), 298 INTC_VECT(PECI3, 0x1ec0), INTC_VECT(PECI4, 0x1ee0), 299 INTC_VECT(PECI5, 0x1f00), 300 INTC_VECT(SGPIO, 0x1f80), INTC_VECT(SGPIO, 0x1fa0), 301 INTC_VECT(SGPIO, 0x1fc0), 302 INTC_VECT(DMINT12, 0x2400), INTC_VECT(DMINT13, 0x2420), 303 INTC_VECT(DMINT14, 0x2440), INTC_VECT(DMINT15, 0x2460), 304 INTC_VECT(DMINT16, 0x2480), INTC_VECT(DMINT17, 0x24e0), 305 INTC_VECT(DMINT18, 0x2500), INTC_VECT(DMINT19, 0x2520), 306 INTC_VECT(DMINT20, 0x2540), INTC_VECT(DMINT21, 0x2560), 307 INTC_VECT(DMINT22, 0x2580), INTC_VECT(DMINT23, 0x2600), 308 INTC_VECT(DDRECC, 0x2620), 309 INTC_VECT(TSIP, 0x2640), 310 INTC_VECT(PCIE_BRIDGE, 0x27c0), 311 INTC_VECT(WDT0B, 0x2800), INTC_VECT(WDT1B, 0x2820), 312 INTC_VECT(WDT2B, 0x2840), INTC_VECT(WDT3B, 0x2860), 313 INTC_VECT(WDT4B, 0x2880), INTC_VECT(WDT5B, 0x28a0), 314 INTC_VECT(WDT6B, 0x28c0), INTC_VECT(WDT7B, 0x28e0), 315 INTC_VECT(WDT8B, 0x2900), 316 INTC_VECT(GETHER0, 0x2960), INTC_VECT(GETHER1, 0x2980), 317 INTC_VECT(GETHER2, 0x29a0), 318 INTC_VECT(PBIA, 0x2a00), INTC_VECT(PBIB, 0x2a20), 319 INTC_VECT(PBIC, 0x2a40), 320 INTC_VECT(DMAE2, 0x2a60), INTC_VECT(DMAE3, 0x2a80), 321 INTC_VECT(SERMUX2, 0x2aa0), INTC_VECT(SERMUX3, 0x2b40), 322 INTC_VECT(LPC5, 0x2b60), INTC_VECT(LPC6, 0x2b80), 323 INTC_VECT(LPC7, 0x2c00), INTC_VECT(LPC8, 0x2c20), 324 }; 325 326 static struct intc_group groups[] __initdata = { 327 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), 328 INTC_GROUP(TMU345, TMU3, TMU4, TMU5), 329 }; 330 331 static struct intc_mask_reg mask_registers[] __initdata = { 332 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ 333 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 334 335 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ 336 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, 337 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, 338 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, 339 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0, 340 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH, 341 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH, 342 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH, 343 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } }, 344 345 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ 346 { 0, 0, 0, 0, 0, 0, 0, 0, 347 0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45, 348 TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0_5, 349 HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012 350 } }, 351 352 { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */ 353 { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC, 354 IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1, 355 ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1, 356 ARC4, 0, SPI1, JMC, 0, 0, 0, DVC 357 } }, 358 359 { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */ 360 { IIC4_1, IIC4_2, IIC5_0, ONFICTL, 0, 0, SGPIO, 0, 361 0, G200, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3, 362 IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1, 363 IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, 0, IIC2_2 364 } }, 365 366 { 0xffd100d0, 0xffd100d4, 32, /* INT2MSKR3 / INT2MSKCR3 */ 367 { MMC1, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, PECI5, MMC2, 368 IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2, 369 PCIC, 0, IIC4_0, 0, ECCU, RSPI, 0, IIC9_3, 370 IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1 371 } }, 372 373 { 0xffd20038, 0xffd2003c, 32, /* INT2MSKR4 / INT2MSKCR4 */ 374 { WDT0B, WDT1B, WDT3B, GETHER0, 0, 0, 0, 0, 375 0, 0, 0, LPC7, SERMUX2, DMAE3, DMAE2, PBIC, 376 PBIB, PBIA, GETHER1, DMINT12, DMINT13, DMINT14, DMINT15, TSIP, 377 DMINT23, 0, DMINT21, LPC6, 0, DMINT16, 0, DMINT22 378 } }, 379 380 { 0xffd200d0, 0xffd200d4, 32, /* INT2MSKR5 / INT2MSKCR5 */ 381 { 0, WDT8B, WDT7B, WDT4B, 0, DMINT20, 0, 0, 382 DMINT19, DMINT18, LPC5, SERMUX3, WDT2B, GETHER2, 0, 0, 383 0, 0, PCIE_BRIDGE, 0, 0, 0, 0, LPC8, 384 DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17 385 } }, 386 }; 387 388 #define INTPRI 0xffd00010 389 #define INT2PRI0 0xffd40000 390 #define INT2PRI1 0xffd40004 391 #define INT2PRI2 0xffd40008 392 #define INT2PRI3 0xffd4000c 393 #define INT2PRI4 0xffd40010 394 #define INT2PRI5 0xffd40014 395 #define INT2PRI6 0xffd40018 396 #define INT2PRI7 0xffd4001c 397 #define INT2PRI8 0xffd400a0 398 #define INT2PRI9 0xffd400a4 399 #define INT2PRI10 0xffd400a8 400 #define INT2PRI11 0xffd400ac 401 #define INT2PRI12 0xffd400b0 402 #define INT2PRI13 0xffd400b4 403 #define INT2PRI14 0xffd400b8 404 #define INT2PRI15 0xffd400bc 405 #define INT2PRI16 0xffd10000 406 #define INT2PRI17 0xffd10004 407 #define INT2PRI18 0xffd10008 408 #define INT2PRI19 0xffd1000c 409 #define INT2PRI20 0xffd10010 410 #define INT2PRI21 0xffd10014 411 #define INT2PRI22 0xffd10018 412 #define INT2PRI23 0xffd1001c 413 #define INT2PRI24 0xffd100a0 414 #define INT2PRI25 0xffd100a4 415 #define INT2PRI26 0xffd100a8 416 #define INT2PRI27 0xffd100ac 417 #define INT2PRI28 0xffd100b0 418 #define INT2PRI29 0xffd100b4 419 #define INT2PRI30 0xffd100b8 420 #define INT2PRI31 0xffd100bc 421 #define INT2PRI32 0xffd20000 422 #define INT2PRI33 0xffd20004 423 #define INT2PRI34 0xffd20008 424 #define INT2PRI35 0xffd2000c 425 #define INT2PRI36 0xffd20010 426 #define INT2PRI37 0xffd20014 427 #define INT2PRI38 0xffd20018 428 #define INT2PRI39 0xffd2001c 429 #define INT2PRI40 0xffd200a0 430 #define INT2PRI41 0xffd200a4 431 #define INT2PRI42 0xffd200a8 432 #define INT2PRI43 0xffd200ac 433 #define INT2PRI44 0xffd200b0 434 #define INT2PRI45 0xffd200b4 435 #define INT2PRI46 0xffd200b8 436 #define INT2PRI47 0xffd200bc 437 438 static struct intc_prio_reg prio_registers[] __initdata = { 439 { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3, 440 IRQ4, IRQ5, IRQ6, IRQ7 } }, 441 442 { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } }, 443 { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } }, 444 { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, 0, IRQ8 } }, 445 { INT2PRI3, 0, 32, 8, { HUDI, DMAC0_5, ADC0, IRQ9 } }, 446 { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } }, 447 { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } }, 448 { INT2PRI6, 0, 32, 8, { PECI0, ETHERC, DMAC8_11, 0 } }, 449 { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } }, 450 { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } }, 451 { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } }, 452 { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } }, 453 { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC6_7, IRQ14 } }, 454 { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } }, 455 { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } }, 456 457 { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } }, 458 { INT2PRI17, 0, 32, 8, { 0, 0, 0, IIC1_0 } }, 459 { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } }, 460 { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } }, 461 { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } }, 462 { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } }, 463 { INT2PRI22, 0, 32, 8, { IIC9_2, MMC2, G200, 0 } }, 464 { INT2PRI23, 0, 32, 8, { PECI5, SGPIO, IIC3_2, IIC5_1 } }, 465 { INT2PRI24, 0, 32, 8, { PECI4, PECI3, 0, IIC1_1 } }, 466 { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } }, 467 { INT2PRI26, 0, 32, 8, { ECCU, RSPI, 0, IIC9_3 } }, 468 { INT2PRI27, 0, 32, 8, { PCIC, IIC6_0, IIC4_0, IIC6_1 } }, 469 { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, MMC1, IIC6_2 } }, 470 { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } }, 471 { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, ONFICTL } }, 472 { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } }, 473 { INT2PRI32, 0, 32, 8, { DMINT22, 0, 0, 0 } }, 474 { INT2PRI33, 0, 32, 8, { 0, 0, 0, DMINT16 } }, 475 { INT2PRI34, 0, 32, 8, { 0, LPC6, DMINT21, DMINT18 } }, 476 { INT2PRI35, 0, 32, 8, { DMINT23, TSIP, 0, DMINT19 } }, 477 { INT2PRI36, 0, 32, 8, { DMINT20, GETHER1, PBIA, PBIB } }, 478 { INT2PRI37, 0, 32, 8, { PBIC, DMAE2, DMAE3, SERMUX2 } }, 479 { INT2PRI38, 0, 32, 8, { LPC7, 0, 0, 0 } }, 480 { INT2PRI39, 0, 32, 8, { 0, 0, 0, WDT4B } }, 481 { INT2PRI40, 0, 32, 8, { 0, 0, 0, DMINT17 } }, 482 { INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } }, 483 { INT2PRI42, 0, 32, 8, { 0, 0, 0, LPC8 } }, 484 { INT2PRI43, 0, 32, 8, { 0, WDT7B, PCIE_BRIDGE, WDT8B } }, 485 { INT2PRI44, 0, 32, 8, { WDT2B, GETHER2, 0, 0 } }, 486 { INT2PRI45, 0, 32, 8, { 0, 0, LPC5, SERMUX3 } }, 487 { INT2PRI46, 0, 32, 8, { WDT0B, WDT1B, WDT3B, GETHER0 } }, 488 { INT2PRI47, 0, 32, 8, { DMINT12, DMINT13, DMINT14, DMINT15 } }, 489 }; 490 491 static struct intc_sense_reg sense_registers_irq8to15[] __initdata = { 492 { 0xffd100f8, 32, 2, /* ICR2 */ { IRQ15, IRQ14, IRQ13, IRQ12, 493 IRQ11, IRQ10, IRQ9, IRQ8 } }, 494 }; 495 496 static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups, 497 mask_registers, prio_registers, 498 sense_registers_irq8to15); 499 500 /* Support for external interrupt pins in IRQ mode */ 501 static struct intc_vect vectors_irq0123[] __initdata = { 502 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), 503 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), 504 }; 505 506 static struct intc_vect vectors_irq4567[] __initdata = { 507 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380), 508 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200), 509 }; 510 511 static struct intc_sense_reg sense_registers[] __initdata = { 512 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, 513 IRQ4, IRQ5, IRQ6, IRQ7 } }, 514 }; 515 516 static struct intc_mask_reg ack_registers[] __initdata = { 517 { 0xffd00024, 0, 32, /* INTREQ */ 518 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 519 }; 520 521 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123", 522 vectors_irq0123, NULL, mask_registers, 523 prio_registers, sense_registers, ack_registers); 524 525 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567", 526 vectors_irq4567, NULL, mask_registers, 527 prio_registers, sense_registers, ack_registers); 528 529 /* External interrupt pins in IRL mode */ 530 static struct intc_vect vectors_irl0123[] __initdata = { 531 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220), 532 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260), 533 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0), 534 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0), 535 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320), 536 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360), 537 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0), 538 INTC_VECT(IRL0_HHHL, 0x3c0), 539 }; 540 541 static struct intc_vect vectors_irl4567[] __initdata = { 542 INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20), 543 INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60), 544 INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0), 545 INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0), 546 INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20), 547 INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60), 548 INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0), 549 INTC_VECT(IRL4_HHHL, 0xcc0), 550 }; 551 552 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123, 553 NULL, mask_registers, NULL, NULL); 554 555 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567, 556 NULL, mask_registers, NULL, NULL); 557 558 #define INTC_ICR0 0xffd00000 559 #define INTC_INTMSK0 0xffd00044 560 #define INTC_INTMSK1 0xffd00048 561 #define INTC_INTMSK2 0xffd40080 562 #define INTC_INTMSKCLR1 0xffd00068 563 #define INTC_INTMSKCLR2 0xffd40084 564 565 void __init plat_irq_setup(void) 566 { 567 /* disable IRQ3-0 + IRQ7-4 */ 568 __raw_writel(0xff000000, INTC_INTMSK0); 569 570 /* disable IRL3-0 + IRL7-4 */ 571 __raw_writel(0xc0000000, INTC_INTMSK1); 572 __raw_writel(0xfffefffe, INTC_INTMSK2); 573 574 /* select IRL mode for IRL3-0 + IRL7-4 */ 575 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 576 577 /* disable holding function, ie enable "SH-4 Mode" */ 578 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); 579 580 register_intc_controller(&intc_desc); 581 } 582 583 void __init plat_irq_setup_pins(int mode) 584 { 585 switch (mode) { 586 case IRQ_MODE_IRQ7654: 587 /* select IRQ mode for IRL7-4 */ 588 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0); 589 register_intc_controller(&intc_desc_irq4567); 590 break; 591 case IRQ_MODE_IRQ3210: 592 /* select IRQ mode for IRL3-0 */ 593 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); 594 register_intc_controller(&intc_desc_irq0123); 595 break; 596 case IRQ_MODE_IRL7654: 597 /* enable IRL7-4 but don't provide any masking */ 598 __raw_writel(0x40000000, INTC_INTMSKCLR1); 599 __raw_writel(0x0000fffe, INTC_INTMSKCLR2); 600 break; 601 case IRQ_MODE_IRL3210: 602 /* enable IRL0-3 but don't provide any masking */ 603 __raw_writel(0x80000000, INTC_INTMSKCLR1); 604 __raw_writel(0xfffe0000, INTC_INTMSKCLR2); 605 break; 606 case IRQ_MODE_IRL7654_MASK: 607 /* enable IRL7-4 and mask using cpu intc controller */ 608 __raw_writel(0x40000000, INTC_INTMSKCLR1); 609 register_intc_controller(&intc_desc_irl4567); 610 break; 611 case IRQ_MODE_IRL3210_MASK: 612 /* enable IRL0-3 and mask using cpu intc controller */ 613 __raw_writel(0x80000000, INTC_INTMSKCLR1); 614 register_intc_controller(&intc_desc_irl0123); 615 break; 616 default: 617 BUG(); 618 } 619 } 620 621 void __init plat_mem_setup(void) 622 { 623 } 624