1 /* 2 * SH7757 Setup 3 * 4 * Copyright (C) 2009, 2011 Renesas Solutions Corp. 5 * 6 * based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 #include <linux/platform_device.h> 13 #include <linux/init.h> 14 #include <linux/serial.h> 15 #include <linux/serial_sci.h> 16 #include <linux/io.h> 17 #include <linux/mm.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/sh_timer.h> 20 #include <linux/sh_dma.h> 21 #include <linux/sh_intc.h> 22 #include <cpu/dma-register.h> 23 #include <cpu/sh7757.h> 24 25 static struct plat_sci_port scif2_platform_data = { 26 .mapbase = 0xfe4b0000, /* SCIF2 */ 27 .flags = UPF_BOOT_AUTOCONF, 28 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 29 .scbrr_algo_id = SCBRR_ALGO_2, 30 .type = PORT_SCIF, 31 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), 32 }; 33 34 static struct platform_device scif2_device = { 35 .name = "sh-sci", 36 .id = 0, 37 .dev = { 38 .platform_data = &scif2_platform_data, 39 }, 40 }; 41 42 static struct plat_sci_port scif3_platform_data = { 43 .mapbase = 0xfe4c0000, /* SCIF3 */ 44 .flags = UPF_BOOT_AUTOCONF, 45 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 46 .scbrr_algo_id = SCBRR_ALGO_2, 47 .type = PORT_SCIF, 48 .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)), 49 }; 50 51 static struct platform_device scif3_device = { 52 .name = "sh-sci", 53 .id = 1, 54 .dev = { 55 .platform_data = &scif3_platform_data, 56 }, 57 }; 58 59 static struct plat_sci_port scif4_platform_data = { 60 .mapbase = 0xfe4d0000, /* SCIF4 */ 61 .flags = UPF_BOOT_AUTOCONF, 62 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 63 .scbrr_algo_id = SCBRR_ALGO_2, 64 .type = PORT_SCIF, 65 .irqs = SCIx_IRQ_MUXED(evt2irq(0xF00)), 66 }; 67 68 static struct platform_device scif4_device = { 69 .name = "sh-sci", 70 .id = 2, 71 .dev = { 72 .platform_data = &scif4_platform_data, 73 }, 74 }; 75 76 static struct sh_timer_config tmu0_platform_data = { 77 .channel_offset = 0x04, 78 .timer_bit = 0, 79 .clockevent_rating = 200, 80 }; 81 82 static struct resource tmu0_resources[] = { 83 [0] = { 84 .start = 0xfe430008, 85 .end = 0xfe430013, 86 .flags = IORESOURCE_MEM, 87 }, 88 [1] = { 89 .start = evt2irq(0x580), 90 .flags = IORESOURCE_IRQ, 91 }, 92 }; 93 94 static struct platform_device tmu0_device = { 95 .name = "sh_tmu", 96 .id = 0, 97 .dev = { 98 .platform_data = &tmu0_platform_data, 99 }, 100 .resource = tmu0_resources, 101 .num_resources = ARRAY_SIZE(tmu0_resources), 102 }; 103 104 static struct sh_timer_config tmu1_platform_data = { 105 .channel_offset = 0x10, 106 .timer_bit = 1, 107 .clocksource_rating = 200, 108 }; 109 110 static struct resource tmu1_resources[] = { 111 [0] = { 112 .start = 0xfe430014, 113 .end = 0xfe43001f, 114 .flags = IORESOURCE_MEM, 115 }, 116 [1] = { 117 .start = evt2irq(0x5a0), 118 .flags = IORESOURCE_IRQ, 119 }, 120 }; 121 122 static struct platform_device tmu1_device = { 123 .name = "sh_tmu", 124 .id = 1, 125 .dev = { 126 .platform_data = &tmu1_platform_data, 127 }, 128 .resource = tmu1_resources, 129 .num_resources = ARRAY_SIZE(tmu1_resources), 130 }; 131 132 static struct resource spi0_resources[] = { 133 [0] = { 134 .start = 0xfe002000, 135 .end = 0xfe0020ff, 136 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, 137 }, 138 [1] = { 139 .start = evt2irq(0xcc0), 140 .flags = IORESOURCE_IRQ, 141 }, 142 }; 143 144 /* DMA */ 145 static const struct sh_dmae_slave_config sh7757_dmae0_slaves[] = { 146 { 147 .slave_id = SHDMA_SLAVE_SDHI_TX, 148 .addr = 0x1fe50030, 149 .chcr = SM_INC | 0x800 | 0x40000000 | 150 TS_INDEX2VAL(XMIT_SZ_16BIT), 151 .mid_rid = 0xc5, 152 }, 153 { 154 .slave_id = SHDMA_SLAVE_SDHI_RX, 155 .addr = 0x1fe50030, 156 .chcr = DM_INC | 0x800 | 0x40000000 | 157 TS_INDEX2VAL(XMIT_SZ_16BIT), 158 .mid_rid = 0xc6, 159 }, 160 { 161 .slave_id = SHDMA_SLAVE_MMCIF_TX, 162 .addr = 0x1fcb0034, 163 .chcr = SM_INC | 0x800 | 0x40000000 | 164 TS_INDEX2VAL(XMIT_SZ_32BIT), 165 .mid_rid = 0xd3, 166 }, 167 { 168 .slave_id = SHDMA_SLAVE_MMCIF_RX, 169 .addr = 0x1fcb0034, 170 .chcr = DM_INC | 0x800 | 0x40000000 | 171 TS_INDEX2VAL(XMIT_SZ_32BIT), 172 .mid_rid = 0xd7, 173 }, 174 }; 175 176 static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = { 177 { 178 .slave_id = SHDMA_SLAVE_SCIF2_TX, 179 .addr = 0x1f4b000c, 180 .chcr = SM_INC | 0x800 | 0x40000000 | 181 TS_INDEX2VAL(XMIT_SZ_8BIT), 182 .mid_rid = 0x21, 183 }, 184 { 185 .slave_id = SHDMA_SLAVE_SCIF2_RX, 186 .addr = 0x1f4b0014, 187 .chcr = DM_INC | 0x800 | 0x40000000 | 188 TS_INDEX2VAL(XMIT_SZ_8BIT), 189 .mid_rid = 0x22, 190 }, 191 { 192 .slave_id = SHDMA_SLAVE_SCIF3_TX, 193 .addr = 0x1f4c000c, 194 .chcr = SM_INC | 0x800 | 0x40000000 | 195 TS_INDEX2VAL(XMIT_SZ_8BIT), 196 .mid_rid = 0x29, 197 }, 198 { 199 .slave_id = SHDMA_SLAVE_SCIF3_RX, 200 .addr = 0x1f4c0014, 201 .chcr = DM_INC | 0x800 | 0x40000000 | 202 TS_INDEX2VAL(XMIT_SZ_8BIT), 203 .mid_rid = 0x2a, 204 }, 205 { 206 .slave_id = SHDMA_SLAVE_SCIF4_TX, 207 .addr = 0x1f4d000c, 208 .chcr = SM_INC | 0x800 | 0x40000000 | 209 TS_INDEX2VAL(XMIT_SZ_8BIT), 210 .mid_rid = 0x41, 211 }, 212 { 213 .slave_id = SHDMA_SLAVE_SCIF4_RX, 214 .addr = 0x1f4d0014, 215 .chcr = DM_INC | 0x800 | 0x40000000 | 216 TS_INDEX2VAL(XMIT_SZ_8BIT), 217 .mid_rid = 0x42, 218 }, 219 { 220 .slave_id = SHDMA_SLAVE_RSPI_TX, 221 .addr = 0xfe480004, 222 .chcr = SM_INC | 0x800 | 0x40000000 | 223 TS_INDEX2VAL(XMIT_SZ_16BIT), 224 .mid_rid = 0xc1, 225 }, 226 { 227 .slave_id = SHDMA_SLAVE_RSPI_RX, 228 .addr = 0xfe480004, 229 .chcr = DM_INC | 0x800 | 0x40000000 | 230 TS_INDEX2VAL(XMIT_SZ_16BIT), 231 .mid_rid = 0xc2, 232 }, 233 }; 234 235 static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = { 236 { 237 .slave_id = SHDMA_SLAVE_RIIC0_TX, 238 .addr = 0x1e500012, 239 .chcr = SM_INC | 0x800 | 0x40000000 | 240 TS_INDEX2VAL(XMIT_SZ_8BIT), 241 .mid_rid = 0x21, 242 }, 243 { 244 .slave_id = SHDMA_SLAVE_RIIC0_RX, 245 .addr = 0x1e500013, 246 .chcr = DM_INC | 0x800 | 0x40000000 | 247 TS_INDEX2VAL(XMIT_SZ_8BIT), 248 .mid_rid = 0x22, 249 }, 250 { 251 .slave_id = SHDMA_SLAVE_RIIC1_TX, 252 .addr = 0x1e510012, 253 .chcr = SM_INC | 0x800 | 0x40000000 | 254 TS_INDEX2VAL(XMIT_SZ_8BIT), 255 .mid_rid = 0x29, 256 }, 257 { 258 .slave_id = SHDMA_SLAVE_RIIC1_RX, 259 .addr = 0x1e510013, 260 .chcr = DM_INC | 0x800 | 0x40000000 | 261 TS_INDEX2VAL(XMIT_SZ_8BIT), 262 .mid_rid = 0x2a, 263 }, 264 { 265 .slave_id = SHDMA_SLAVE_RIIC2_TX, 266 .addr = 0x1e520012, 267 .chcr = SM_INC | 0x800 | 0x40000000 | 268 TS_INDEX2VAL(XMIT_SZ_8BIT), 269 .mid_rid = 0xa1, 270 }, 271 { 272 .slave_id = SHDMA_SLAVE_RIIC2_RX, 273 .addr = 0x1e520013, 274 .chcr = DM_INC | 0x800 | 0x40000000 | 275 TS_INDEX2VAL(XMIT_SZ_8BIT), 276 .mid_rid = 0xa2, 277 }, 278 { 279 .slave_id = SHDMA_SLAVE_RIIC3_TX, 280 .addr = 0x1e530012, 281 .chcr = SM_INC | 0x800 | 0x40000000 | 282 TS_INDEX2VAL(XMIT_SZ_8BIT), 283 .mid_rid = 0xa9, 284 }, 285 { 286 .slave_id = SHDMA_SLAVE_RIIC3_RX, 287 .addr = 0x1e530013, 288 .chcr = DM_INC | 0x800 | 0x40000000 | 289 TS_INDEX2VAL(XMIT_SZ_8BIT), 290 .mid_rid = 0xaf, 291 }, 292 { 293 .slave_id = SHDMA_SLAVE_RIIC4_TX, 294 .addr = 0x1e540012, 295 .chcr = SM_INC | 0x800 | 0x40000000 | 296 TS_INDEX2VAL(XMIT_SZ_8BIT), 297 .mid_rid = 0xc5, 298 }, 299 { 300 .slave_id = SHDMA_SLAVE_RIIC4_RX, 301 .addr = 0x1e540013, 302 .chcr = DM_INC | 0x800 | 0x40000000 | 303 TS_INDEX2VAL(XMIT_SZ_8BIT), 304 .mid_rid = 0xc6, 305 }, 306 }; 307 308 static const struct sh_dmae_slave_config sh7757_dmae3_slaves[] = { 309 { 310 .slave_id = SHDMA_SLAVE_RIIC5_TX, 311 .addr = 0x1e550012, 312 .chcr = SM_INC | 0x800 | 0x40000000 | 313 TS_INDEX2VAL(XMIT_SZ_8BIT), 314 .mid_rid = 0x21, 315 }, 316 { 317 .slave_id = SHDMA_SLAVE_RIIC5_RX, 318 .addr = 0x1e550013, 319 .chcr = DM_INC | 0x800 | 0x40000000 | 320 TS_INDEX2VAL(XMIT_SZ_8BIT), 321 .mid_rid = 0x22, 322 }, 323 { 324 .slave_id = SHDMA_SLAVE_RIIC6_TX, 325 .addr = 0x1e560012, 326 .chcr = SM_INC | 0x800 | 0x40000000 | 327 TS_INDEX2VAL(XMIT_SZ_8BIT), 328 .mid_rid = 0x29, 329 }, 330 { 331 .slave_id = SHDMA_SLAVE_RIIC6_RX, 332 .addr = 0x1e560013, 333 .chcr = DM_INC | 0x800 | 0x40000000 | 334 TS_INDEX2VAL(XMIT_SZ_8BIT), 335 .mid_rid = 0x2a, 336 }, 337 { 338 .slave_id = SHDMA_SLAVE_RIIC7_TX, 339 .addr = 0x1e570012, 340 .chcr = SM_INC | 0x800 | 0x40000000 | 341 TS_INDEX2VAL(XMIT_SZ_8BIT), 342 .mid_rid = 0x41, 343 }, 344 { 345 .slave_id = SHDMA_SLAVE_RIIC7_RX, 346 .addr = 0x1e570013, 347 .chcr = DM_INC | 0x800 | 0x40000000 | 348 TS_INDEX2VAL(XMIT_SZ_8BIT), 349 .mid_rid = 0x42, 350 }, 351 { 352 .slave_id = SHDMA_SLAVE_RIIC8_TX, 353 .addr = 0x1e580012, 354 .chcr = SM_INC | 0x800 | 0x40000000 | 355 TS_INDEX2VAL(XMIT_SZ_8BIT), 356 .mid_rid = 0x45, 357 }, 358 { 359 .slave_id = SHDMA_SLAVE_RIIC8_RX, 360 .addr = 0x1e580013, 361 .chcr = DM_INC | 0x800 | 0x40000000 | 362 TS_INDEX2VAL(XMIT_SZ_8BIT), 363 .mid_rid = 0x46, 364 }, 365 { 366 .slave_id = SHDMA_SLAVE_RIIC9_TX, 367 .addr = 0x1e590012, 368 .chcr = SM_INC | 0x800 | 0x40000000 | 369 TS_INDEX2VAL(XMIT_SZ_8BIT), 370 .mid_rid = 0x51, 371 }, 372 { 373 .slave_id = SHDMA_SLAVE_RIIC9_RX, 374 .addr = 0x1e590013, 375 .chcr = DM_INC | 0x800 | 0x40000000 | 376 TS_INDEX2VAL(XMIT_SZ_8BIT), 377 .mid_rid = 0x52, 378 }, 379 }; 380 381 static const struct sh_dmae_channel sh7757_dmae_channels[] = { 382 { 383 .offset = 0, 384 .dmars = 0, 385 .dmars_bit = 0, 386 }, { 387 .offset = 0x10, 388 .dmars = 0, 389 .dmars_bit = 8, 390 }, { 391 .offset = 0x20, 392 .dmars = 4, 393 .dmars_bit = 0, 394 }, { 395 .offset = 0x30, 396 .dmars = 4, 397 .dmars_bit = 8, 398 }, { 399 .offset = 0x50, 400 .dmars = 8, 401 .dmars_bit = 0, 402 }, { 403 .offset = 0x60, 404 .dmars = 8, 405 .dmars_bit = 8, 406 } 407 }; 408 409 static const unsigned int ts_shift[] = TS_SHIFT; 410 411 static struct sh_dmae_pdata dma0_platform_data = { 412 .slave = sh7757_dmae0_slaves, 413 .slave_num = ARRAY_SIZE(sh7757_dmae0_slaves), 414 .channel = sh7757_dmae_channels, 415 .channel_num = ARRAY_SIZE(sh7757_dmae_channels), 416 .ts_low_shift = CHCR_TS_LOW_SHIFT, 417 .ts_low_mask = CHCR_TS_LOW_MASK, 418 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 419 .ts_high_mask = CHCR_TS_HIGH_MASK, 420 .ts_shift = ts_shift, 421 .ts_shift_num = ARRAY_SIZE(ts_shift), 422 .dmaor_init = DMAOR_INIT, 423 }; 424 425 static struct sh_dmae_pdata dma1_platform_data = { 426 .slave = sh7757_dmae1_slaves, 427 .slave_num = ARRAY_SIZE(sh7757_dmae1_slaves), 428 .channel = sh7757_dmae_channels, 429 .channel_num = ARRAY_SIZE(sh7757_dmae_channels), 430 .ts_low_shift = CHCR_TS_LOW_SHIFT, 431 .ts_low_mask = CHCR_TS_LOW_MASK, 432 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 433 .ts_high_mask = CHCR_TS_HIGH_MASK, 434 .ts_shift = ts_shift, 435 .ts_shift_num = ARRAY_SIZE(ts_shift), 436 .dmaor_init = DMAOR_INIT, 437 }; 438 439 static struct sh_dmae_pdata dma2_platform_data = { 440 .slave = sh7757_dmae2_slaves, 441 .slave_num = ARRAY_SIZE(sh7757_dmae2_slaves), 442 .channel = sh7757_dmae_channels, 443 .channel_num = ARRAY_SIZE(sh7757_dmae_channels), 444 .ts_low_shift = CHCR_TS_LOW_SHIFT, 445 .ts_low_mask = CHCR_TS_LOW_MASK, 446 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 447 .ts_high_mask = CHCR_TS_HIGH_MASK, 448 .ts_shift = ts_shift, 449 .ts_shift_num = ARRAY_SIZE(ts_shift), 450 .dmaor_init = DMAOR_INIT, 451 }; 452 453 static struct sh_dmae_pdata dma3_platform_data = { 454 .slave = sh7757_dmae3_slaves, 455 .slave_num = ARRAY_SIZE(sh7757_dmae3_slaves), 456 .channel = sh7757_dmae_channels, 457 .channel_num = ARRAY_SIZE(sh7757_dmae_channels), 458 .ts_low_shift = CHCR_TS_LOW_SHIFT, 459 .ts_low_mask = CHCR_TS_LOW_MASK, 460 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 461 .ts_high_mask = CHCR_TS_HIGH_MASK, 462 .ts_shift = ts_shift, 463 .ts_shift_num = ARRAY_SIZE(ts_shift), 464 .dmaor_init = DMAOR_INIT, 465 }; 466 467 /* channel 0 to 5 */ 468 static struct resource sh7757_dmae0_resources[] = { 469 [0] = { 470 /* Channel registers and DMAOR */ 471 .start = 0xff608020, 472 .end = 0xff60808f, 473 .flags = IORESOURCE_MEM, 474 }, 475 [1] = { 476 /* DMARSx */ 477 .start = 0xff609000, 478 .end = 0xff60900b, 479 .flags = IORESOURCE_MEM, 480 }, 481 { 482 .name = "error_irq", 483 .start = evt2irq(0x640), 484 .end = evt2irq(0x640), 485 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 486 }, 487 }; 488 489 /* channel 6 to 11 */ 490 static struct resource sh7757_dmae1_resources[] = { 491 [0] = { 492 /* Channel registers and DMAOR */ 493 .start = 0xff618020, 494 .end = 0xff61808f, 495 .flags = IORESOURCE_MEM, 496 }, 497 [1] = { 498 /* DMARSx */ 499 .start = 0xff619000, 500 .end = 0xff61900b, 501 .flags = IORESOURCE_MEM, 502 }, 503 { 504 .name = "error_irq", 505 .start = evt2irq(0x640), 506 .end = evt2irq(0x640), 507 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 508 }, 509 { 510 /* IRQ for channels 4 */ 511 .start = evt2irq(0x7c0), 512 .end = evt2irq(0x7c0), 513 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 514 }, 515 { 516 /* IRQ for channels 5 */ 517 .start = evt2irq(0x7c0), 518 .end = evt2irq(0x7c0), 519 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 520 }, 521 { 522 /* IRQ for channels 6 */ 523 .start = evt2irq(0xd00), 524 .end = evt2irq(0xd00), 525 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 526 }, 527 { 528 /* IRQ for channels 7 */ 529 .start = evt2irq(0xd00), 530 .end = evt2irq(0xd00), 531 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 532 }, 533 { 534 /* IRQ for channels 8 */ 535 .start = evt2irq(0xd00), 536 .end = evt2irq(0xd00), 537 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 538 }, 539 { 540 /* IRQ for channels 9 */ 541 .start = evt2irq(0xd00), 542 .end = evt2irq(0xd00), 543 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 544 }, 545 { 546 /* IRQ for channels 10 */ 547 .start = evt2irq(0xd00), 548 .end = evt2irq(0xd00), 549 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 550 }, 551 { 552 /* IRQ for channels 11 */ 553 .start = evt2irq(0xd00), 554 .end = evt2irq(0xd00), 555 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 556 }, 557 }; 558 559 /* channel 12 to 17 */ 560 static struct resource sh7757_dmae2_resources[] = { 561 [0] = { 562 /* Channel registers and DMAOR */ 563 .start = 0xff708020, 564 .end = 0xff70808f, 565 .flags = IORESOURCE_MEM, 566 }, 567 [1] = { 568 /* DMARSx */ 569 .start = 0xff709000, 570 .end = 0xff70900b, 571 .flags = IORESOURCE_MEM, 572 }, 573 { 574 .name = "error_irq", 575 .start = evt2irq(0x2a60), 576 .end = evt2irq(0x2a60), 577 .flags = IORESOURCE_IRQ, 578 }, 579 { 580 /* IRQ for channels 12 to 16 */ 581 .start = evt2irq(0x2400), 582 .end = evt2irq(0x2480), 583 .flags = IORESOURCE_IRQ, 584 }, 585 { 586 /* IRQ for channel 17 */ 587 .start = evt2irq(0x24e0), 588 .end = evt2irq(0x24e0), 589 .flags = IORESOURCE_IRQ, 590 }, 591 }; 592 593 /* channel 18 to 23 */ 594 static struct resource sh7757_dmae3_resources[] = { 595 [0] = { 596 /* Channel registers and DMAOR */ 597 .start = 0xff718020, 598 .end = 0xff71808f, 599 .flags = IORESOURCE_MEM, 600 }, 601 [1] = { 602 /* DMARSx */ 603 .start = 0xff719000, 604 .end = 0xff71900b, 605 .flags = IORESOURCE_MEM, 606 }, 607 { 608 .name = "error_irq", 609 .start = evt2irq(0x2a80), 610 .end = evt2irq(0x2a80), 611 .flags = IORESOURCE_IRQ, 612 }, 613 { 614 /* IRQ for channels 18 to 22 */ 615 .start = evt2irq(0x2500), 616 .end = evt2irq(0x2580), 617 .flags = IORESOURCE_IRQ, 618 }, 619 { 620 /* IRQ for channel 23 */ 621 .start = evt2irq(0x2600), 622 .end = evt2irq(0x2600), 623 .flags = IORESOURCE_IRQ, 624 }, 625 }; 626 627 static struct platform_device dma0_device = { 628 .name = "sh-dma-engine", 629 .id = 0, 630 .resource = sh7757_dmae0_resources, 631 .num_resources = ARRAY_SIZE(sh7757_dmae0_resources), 632 .dev = { 633 .platform_data = &dma0_platform_data, 634 }, 635 }; 636 637 static struct platform_device dma1_device = { 638 .name = "sh-dma-engine", 639 .id = 1, 640 .resource = sh7757_dmae1_resources, 641 .num_resources = ARRAY_SIZE(sh7757_dmae1_resources), 642 .dev = { 643 .platform_data = &dma1_platform_data, 644 }, 645 }; 646 647 static struct platform_device dma2_device = { 648 .name = "sh-dma-engine", 649 .id = 2, 650 .resource = sh7757_dmae2_resources, 651 .num_resources = ARRAY_SIZE(sh7757_dmae2_resources), 652 .dev = { 653 .platform_data = &dma2_platform_data, 654 }, 655 }; 656 657 static struct platform_device dma3_device = { 658 .name = "sh-dma-engine", 659 .id = 3, 660 .resource = sh7757_dmae3_resources, 661 .num_resources = ARRAY_SIZE(sh7757_dmae3_resources), 662 .dev = { 663 .platform_data = &dma3_platform_data, 664 }, 665 }; 666 667 static struct platform_device spi0_device = { 668 .name = "sh_spi", 669 .id = 0, 670 .dev = { 671 .dma_mask = NULL, 672 .coherent_dma_mask = 0xffffffff, 673 }, 674 .num_resources = ARRAY_SIZE(spi0_resources), 675 .resource = spi0_resources, 676 }; 677 678 static struct resource spi1_resources[] = { 679 { 680 .start = 0xffd8ee70, 681 .end = 0xffd8eeff, 682 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, 683 }, 684 { 685 .start = evt2irq(0x8c0), 686 .flags = IORESOURCE_IRQ, 687 }, 688 }; 689 690 static struct platform_device spi1_device = { 691 .name = "sh_spi", 692 .id = 1, 693 .num_resources = ARRAY_SIZE(spi1_resources), 694 .resource = spi1_resources, 695 }; 696 697 static struct resource rspi_resources[] = { 698 { 699 .start = 0xfe480000, 700 .end = 0xfe4800ff, 701 .flags = IORESOURCE_MEM, 702 }, 703 { 704 .start = evt2irq(0x1d80), 705 .flags = IORESOURCE_IRQ, 706 }, 707 }; 708 709 static struct platform_device rspi_device = { 710 .name = "rspi", 711 .id = 2, 712 .num_resources = ARRAY_SIZE(rspi_resources), 713 .resource = rspi_resources, 714 }; 715 716 static struct resource usb_ehci_resources[] = { 717 [0] = { 718 .start = 0xfe4f1000, 719 .end = 0xfe4f10ff, 720 .flags = IORESOURCE_MEM, 721 }, 722 [1] = { 723 .start = evt2irq(0x920), 724 .end = evt2irq(0x920), 725 .flags = IORESOURCE_IRQ, 726 }, 727 }; 728 729 static struct platform_device usb_ehci_device = { 730 .name = "sh_ehci", 731 .id = -1, 732 .dev = { 733 .dma_mask = &usb_ehci_device.dev.coherent_dma_mask, 734 .coherent_dma_mask = DMA_BIT_MASK(32), 735 }, 736 .num_resources = ARRAY_SIZE(usb_ehci_resources), 737 .resource = usb_ehci_resources, 738 }; 739 740 static struct resource usb_ohci_resources[] = { 741 [0] = { 742 .start = 0xfe4f1800, 743 .end = 0xfe4f18ff, 744 .flags = IORESOURCE_MEM, 745 }, 746 [1] = { 747 .start = evt2irq(0x920), 748 .end = evt2irq(0x920), 749 .flags = IORESOURCE_IRQ, 750 }, 751 }; 752 753 static struct platform_device usb_ohci_device = { 754 .name = "sh_ohci", 755 .id = -1, 756 .dev = { 757 .dma_mask = &usb_ohci_device.dev.coherent_dma_mask, 758 .coherent_dma_mask = DMA_BIT_MASK(32), 759 }, 760 .num_resources = ARRAY_SIZE(usb_ohci_resources), 761 .resource = usb_ohci_resources, 762 }; 763 764 static struct platform_device *sh7757_devices[] __initdata = { 765 &scif2_device, 766 &scif3_device, 767 &scif4_device, 768 &tmu0_device, 769 &tmu1_device, 770 &dma0_device, 771 &dma1_device, 772 &dma2_device, 773 &dma3_device, 774 &spi0_device, 775 &spi1_device, 776 &rspi_device, 777 &usb_ehci_device, 778 &usb_ohci_device, 779 }; 780 781 static int __init sh7757_devices_setup(void) 782 { 783 return platform_add_devices(sh7757_devices, 784 ARRAY_SIZE(sh7757_devices)); 785 } 786 arch_initcall(sh7757_devices_setup); 787 788 static struct platform_device *sh7757_early_devices[] __initdata = { 789 &scif2_device, 790 &scif3_device, 791 &scif4_device, 792 &tmu0_device, 793 &tmu1_device, 794 }; 795 796 void __init plat_early_device_setup(void) 797 { 798 early_platform_add_devices(sh7757_early_devices, 799 ARRAY_SIZE(sh7757_early_devices)); 800 } 801 802 enum { 803 UNUSED = 0, 804 805 /* interrupt sources */ 806 807 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, 808 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, 809 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, 810 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 811 812 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH, 813 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH, 814 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH, 815 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 816 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 817 818 SDHI, DVC, 819 IRQ8, IRQ9, IRQ11, IRQ10, IRQ12, IRQ13, IRQ14, IRQ15, 820 TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5, 821 HUDI, 822 ARC4, 823 DMAC0_5, DMAC6_7, DMAC8_11, 824 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, 825 USB0, USB1, 826 JMC, 827 SPI0, SPI1, 828 TMR01, TMR23, TMR45, 829 FRT, 830 LPC, LPC5, LPC6, LPC7, LPC8, 831 PECI0, PECI1, PECI2, PECI3, PECI4, PECI5, 832 ETHERC, 833 ADC0, ADC1, 834 SIM, 835 IIC0_0, IIC0_1, IIC0_2, IIC0_3, 836 IIC1_0, IIC1_1, IIC1_2, IIC1_3, 837 IIC2_0, IIC2_1, IIC2_2, IIC2_3, 838 IIC3_0, IIC3_1, IIC3_2, IIC3_3, 839 IIC4_0, IIC4_1, IIC4_2, IIC4_3, 840 IIC5_0, IIC5_1, IIC5_2, IIC5_3, 841 IIC6_0, IIC6_1, IIC6_2, IIC6_3, 842 IIC7_0, IIC7_1, IIC7_2, IIC7_3, 843 IIC8_0, IIC8_1, IIC8_2, IIC8_3, 844 IIC9_0, IIC9_1, IIC9_2, IIC9_3, 845 ONFICTL, 846 MMC1, MMC2, 847 ECCU, 848 PCIC, 849 G200, 850 RSPI, 851 SGPIO, 852 DMINT12, DMINT13, DMINT14, DMINT15, DMINT16, DMINT17, DMINT18, DMINT19, 853 DMINT20, DMINT21, DMINT22, DMINT23, 854 DDRECC, 855 TSIP, 856 PCIE_BRIDGE, 857 WDT0B, WDT1B, WDT2B, WDT3B, WDT4B, WDT5B, WDT6B, WDT7B, WDT8B, 858 GETHER0, GETHER1, GETHER2, 859 PBIA, PBIB, PBIC, 860 DMAE2, DMAE3, 861 SERMUX2, SERMUX3, 862 863 /* interrupt groups */ 864 865 TMU012, TMU345, 866 }; 867 868 static struct intc_vect vectors[] __initdata = { 869 INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0), 870 INTC_VECT(SDHI, 0x4c0), 871 INTC_VECT(DVC, 0x4e0), 872 INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520), 873 INTC_VECT(IRQ10, 0x540), 874 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), 875 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), 876 INTC_VECT(HUDI, 0x600), 877 INTC_VECT(ARC4, 0x620), 878 INTC_VECT(DMAC0_5, 0x640), INTC_VECT(DMAC0_5, 0x660), 879 INTC_VECT(DMAC0_5, 0x680), INTC_VECT(DMAC0_5, 0x6a0), 880 INTC_VECT(DMAC0_5, 0x6c0), 881 INTC_VECT(IRQ11, 0x6e0), 882 INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720), 883 INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760), 884 INTC_VECT(DMAC0_5, 0x780), INTC_VECT(DMAC0_5, 0x7a0), 885 INTC_VECT(DMAC6_7, 0x7c0), INTC_VECT(DMAC6_7, 0x7e0), 886 INTC_VECT(USB0, 0x840), 887 INTC_VECT(IRQ12, 0x880), 888 INTC_VECT(JMC, 0x8a0), 889 INTC_VECT(SPI1, 0x8c0), 890 INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900), 891 INTC_VECT(USB1, 0x920), 892 INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20), 893 INTC_VECT(TMR45, 0xa40), 894 INTC_VECT(FRT, 0xa80), 895 INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0), 896 INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00), 897 INTC_VECT(LPC, 0xb20), 898 INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60), 899 INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0), 900 INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0), 901 INTC_VECT(PECI0, 0xc00), INTC_VECT(PECI1, 0xc20), 902 INTC_VECT(PECI2, 0xc40), 903 INTC_VECT(IRQ15, 0xc60), 904 INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0), 905 INTC_VECT(SPI0, 0xcc0), 906 INTC_VECT(ADC1, 0xce0), 907 INTC_VECT(DMAC8_11, 0xd00), INTC_VECT(DMAC8_11, 0xd20), 908 INTC_VECT(DMAC8_11, 0xd40), INTC_VECT(DMAC8_11, 0xd60), 909 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0), 910 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0), 911 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 912 INTC_VECT(TMU5, 0xe40), 913 INTC_VECT(ADC0, 0xe60), 914 INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20), 915 INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60), 916 INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420), 917 INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460), 918 INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0), 919 INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520), 920 INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560), 921 INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600), 922 INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640), 923 INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700), 924 INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800), 925 INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840), 926 INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880), 927 INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0), 928 INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900), 929 INTC_VECT(IIC6_2, 0x1920), 930 INTC_VECT(ONFICTL, 0x1960), 931 INTC_VECT(IIC6_3, 0x1980), 932 INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00), 933 INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40), 934 INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80), 935 INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40), 936 INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80), 937 INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20), 938 INTC_VECT(MMC1, 0x1c60), INTC_VECT(MMC2, 0x1c80), 939 INTC_VECT(ECCU, 0x1cc0), 940 INTC_VECT(PCIC, 0x1ce0), 941 INTC_VECT(G200, 0x1d00), 942 INTC_VECT(RSPI, 0x1d80), INTC_VECT(RSPI, 0x1da0), 943 INTC_VECT(RSPI, 0x1dc0), INTC_VECT(RSPI, 0x1de0), 944 INTC_VECT(PECI3, 0x1ec0), INTC_VECT(PECI4, 0x1ee0), 945 INTC_VECT(PECI5, 0x1f00), 946 INTC_VECT(SGPIO, 0x1f80), INTC_VECT(SGPIO, 0x1fa0), 947 INTC_VECT(SGPIO, 0x1fc0), 948 INTC_VECT(DMINT12, 0x2400), INTC_VECT(DMINT13, 0x2420), 949 INTC_VECT(DMINT14, 0x2440), INTC_VECT(DMINT15, 0x2460), 950 INTC_VECT(DMINT16, 0x2480), INTC_VECT(DMINT17, 0x24e0), 951 INTC_VECT(DMINT18, 0x2500), INTC_VECT(DMINT19, 0x2520), 952 INTC_VECT(DMINT20, 0x2540), INTC_VECT(DMINT21, 0x2560), 953 INTC_VECT(DMINT22, 0x2580), INTC_VECT(DMINT23, 0x2600), 954 INTC_VECT(DDRECC, 0x2620), 955 INTC_VECT(TSIP, 0x2640), 956 INTC_VECT(PCIE_BRIDGE, 0x27c0), 957 INTC_VECT(WDT0B, 0x2800), INTC_VECT(WDT1B, 0x2820), 958 INTC_VECT(WDT2B, 0x2840), INTC_VECT(WDT3B, 0x2860), 959 INTC_VECT(WDT4B, 0x2880), INTC_VECT(WDT5B, 0x28a0), 960 INTC_VECT(WDT6B, 0x28c0), INTC_VECT(WDT7B, 0x28e0), 961 INTC_VECT(WDT8B, 0x2900), 962 INTC_VECT(GETHER0, 0x2960), INTC_VECT(GETHER1, 0x2980), 963 INTC_VECT(GETHER2, 0x29a0), 964 INTC_VECT(PBIA, 0x2a00), INTC_VECT(PBIB, 0x2a20), 965 INTC_VECT(PBIC, 0x2a40), 966 INTC_VECT(DMAE2, 0x2a60), INTC_VECT(DMAE3, 0x2a80), 967 INTC_VECT(SERMUX2, 0x2aa0), INTC_VECT(SERMUX3, 0x2b40), 968 INTC_VECT(LPC5, 0x2b60), INTC_VECT(LPC6, 0x2b80), 969 INTC_VECT(LPC7, 0x2c00), INTC_VECT(LPC8, 0x2c20), 970 }; 971 972 static struct intc_group groups[] __initdata = { 973 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), 974 INTC_GROUP(TMU345, TMU3, TMU4, TMU5), 975 }; 976 977 static struct intc_mask_reg mask_registers[] __initdata = { 978 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ 979 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 980 981 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ 982 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, 983 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, 984 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, 985 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0, 986 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH, 987 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH, 988 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH, 989 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } }, 990 991 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ 992 { 0, 0, 0, 0, 0, 0, 0, 0, 993 0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45, 994 TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0_5, 995 HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012 996 } }, 997 998 { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */ 999 { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC, 1000 IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1, 1001 ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1, 1002 ARC4, 0, SPI1, JMC, 0, 0, 0, DVC 1003 } }, 1004 1005 { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */ 1006 { IIC4_1, IIC4_2, IIC5_0, ONFICTL, 0, 0, SGPIO, 0, 1007 0, G200, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3, 1008 IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1, 1009 IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, 0, IIC2_2 1010 } }, 1011 1012 { 0xffd100d0, 0xffd100d4, 32, /* INT2MSKR3 / INT2MSKCR3 */ 1013 { MMC1, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, PECI5, MMC2, 1014 IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2, 1015 PCIC, 0, IIC4_0, 0, ECCU, RSPI, 0, IIC9_3, 1016 IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1 1017 } }, 1018 1019 { 0xffd20038, 0xffd2003c, 32, /* INT2MSKR4 / INT2MSKCR4 */ 1020 { WDT0B, WDT1B, WDT3B, GETHER0, 0, 0, 0, 0, 1021 0, 0, 0, LPC7, SERMUX2, DMAE3, DMAE2, PBIC, 1022 PBIB, PBIA, GETHER1, DMINT12, DMINT13, DMINT14, DMINT15, TSIP, 1023 DMINT23, 0, DMINT21, LPC6, 0, DMINT16, 0, DMINT22 1024 } }, 1025 1026 { 0xffd200d0, 0xffd200d4, 32, /* INT2MSKR5 / INT2MSKCR5 */ 1027 { 0, WDT8B, WDT7B, WDT4B, 0, DMINT20, 0, 0, 1028 DMINT19, DMINT18, LPC5, SERMUX3, WDT2B, GETHER2, 0, 0, 1029 0, 0, PCIE_BRIDGE, 0, 0, 0, 0, LPC8, 1030 DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17 1031 } }, 1032 }; 1033 1034 #define INTPRI 0xffd00010 1035 #define INT2PRI0 0xffd40000 1036 #define INT2PRI1 0xffd40004 1037 #define INT2PRI2 0xffd40008 1038 #define INT2PRI3 0xffd4000c 1039 #define INT2PRI4 0xffd40010 1040 #define INT2PRI5 0xffd40014 1041 #define INT2PRI6 0xffd40018 1042 #define INT2PRI7 0xffd4001c 1043 #define INT2PRI8 0xffd400a0 1044 #define INT2PRI9 0xffd400a4 1045 #define INT2PRI10 0xffd400a8 1046 #define INT2PRI11 0xffd400ac 1047 #define INT2PRI12 0xffd400b0 1048 #define INT2PRI13 0xffd400b4 1049 #define INT2PRI14 0xffd400b8 1050 #define INT2PRI15 0xffd400bc 1051 #define INT2PRI16 0xffd10000 1052 #define INT2PRI17 0xffd10004 1053 #define INT2PRI18 0xffd10008 1054 #define INT2PRI19 0xffd1000c 1055 #define INT2PRI20 0xffd10010 1056 #define INT2PRI21 0xffd10014 1057 #define INT2PRI22 0xffd10018 1058 #define INT2PRI23 0xffd1001c 1059 #define INT2PRI24 0xffd100a0 1060 #define INT2PRI25 0xffd100a4 1061 #define INT2PRI26 0xffd100a8 1062 #define INT2PRI27 0xffd100ac 1063 #define INT2PRI28 0xffd100b0 1064 #define INT2PRI29 0xffd100b4 1065 #define INT2PRI30 0xffd100b8 1066 #define INT2PRI31 0xffd100bc 1067 #define INT2PRI32 0xffd20000 1068 #define INT2PRI33 0xffd20004 1069 #define INT2PRI34 0xffd20008 1070 #define INT2PRI35 0xffd2000c 1071 #define INT2PRI36 0xffd20010 1072 #define INT2PRI37 0xffd20014 1073 #define INT2PRI38 0xffd20018 1074 #define INT2PRI39 0xffd2001c 1075 #define INT2PRI40 0xffd200a0 1076 #define INT2PRI41 0xffd200a4 1077 #define INT2PRI42 0xffd200a8 1078 #define INT2PRI43 0xffd200ac 1079 #define INT2PRI44 0xffd200b0 1080 #define INT2PRI45 0xffd200b4 1081 #define INT2PRI46 0xffd200b8 1082 #define INT2PRI47 0xffd200bc 1083 1084 static struct intc_prio_reg prio_registers[] __initdata = { 1085 { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3, 1086 IRQ4, IRQ5, IRQ6, IRQ7 } }, 1087 1088 { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } }, 1089 { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } }, 1090 { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, 0, IRQ8 } }, 1091 { INT2PRI3, 0, 32, 8, { HUDI, DMAC0_5, ADC0, IRQ9 } }, 1092 { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } }, 1093 { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } }, 1094 { INT2PRI6, 0, 32, 8, { PECI0, ETHERC, DMAC8_11, 0 } }, 1095 { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } }, 1096 { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } }, 1097 { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } }, 1098 { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } }, 1099 { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC6_7, IRQ14 } }, 1100 { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } }, 1101 { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } }, 1102 1103 { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } }, 1104 { INT2PRI17, 0, 32, 8, { 0, 0, 0, IIC1_0 } }, 1105 { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } }, 1106 { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } }, 1107 { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } }, 1108 { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } }, 1109 { INT2PRI22, 0, 32, 8, { IIC9_2, MMC2, G200, 0 } }, 1110 { INT2PRI23, 0, 32, 8, { PECI5, SGPIO, IIC3_2, IIC5_1 } }, 1111 { INT2PRI24, 0, 32, 8, { PECI4, PECI3, 0, IIC1_1 } }, 1112 { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } }, 1113 { INT2PRI26, 0, 32, 8, { ECCU, RSPI, 0, IIC9_3 } }, 1114 { INT2PRI27, 0, 32, 8, { PCIC, IIC6_0, IIC4_0, IIC6_1 } }, 1115 { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, MMC1, IIC6_2 } }, 1116 { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } }, 1117 { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, ONFICTL } }, 1118 { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } }, 1119 { INT2PRI32, 0, 32, 8, { DMINT22, 0, 0, 0 } }, 1120 { INT2PRI33, 0, 32, 8, { 0, 0, 0, DMINT16 } }, 1121 { INT2PRI34, 0, 32, 8, { 0, LPC6, DMINT21, DMINT18 } }, 1122 { INT2PRI35, 0, 32, 8, { DMINT23, TSIP, 0, DMINT19 } }, 1123 { INT2PRI36, 0, 32, 8, { DMINT20, GETHER1, PBIA, PBIB } }, 1124 { INT2PRI37, 0, 32, 8, { PBIC, DMAE2, DMAE3, SERMUX2 } }, 1125 { INT2PRI38, 0, 32, 8, { LPC7, 0, 0, 0 } }, 1126 { INT2PRI39, 0, 32, 8, { 0, 0, 0, WDT4B } }, 1127 { INT2PRI40, 0, 32, 8, { 0, 0, 0, DMINT17 } }, 1128 { INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } }, 1129 { INT2PRI42, 0, 32, 8, { 0, 0, 0, LPC8 } }, 1130 { INT2PRI43, 0, 32, 8, { 0, WDT7B, PCIE_BRIDGE, WDT8B } }, 1131 { INT2PRI44, 0, 32, 8, { WDT2B, GETHER2, 0, 0 } }, 1132 { INT2PRI45, 0, 32, 8, { 0, 0, LPC5, SERMUX3 } }, 1133 { INT2PRI46, 0, 32, 8, { WDT0B, WDT1B, WDT3B, GETHER0 } }, 1134 { INT2PRI47, 0, 32, 8, { DMINT12, DMINT13, DMINT14, DMINT15 } }, 1135 }; 1136 1137 static struct intc_sense_reg sense_registers_irq8to15[] __initdata = { 1138 { 0xffd100f8, 32, 2, /* ICR2 */ { IRQ15, IRQ14, IRQ13, IRQ12, 1139 IRQ11, IRQ10, IRQ9, IRQ8 } }, 1140 }; 1141 1142 static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups, 1143 mask_registers, prio_registers, 1144 sense_registers_irq8to15); 1145 1146 /* Support for external interrupt pins in IRQ mode */ 1147 static struct intc_vect vectors_irq0123[] __initdata = { 1148 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240), 1149 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0), 1150 }; 1151 1152 static struct intc_vect vectors_irq4567[] __initdata = { 1153 INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340), 1154 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0), 1155 }; 1156 1157 static struct intc_sense_reg sense_registers[] __initdata = { 1158 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, 1159 IRQ4, IRQ5, IRQ6, IRQ7 } }, 1160 }; 1161 1162 static struct intc_mask_reg ack_registers[] __initdata = { 1163 { 0xffd00024, 0, 32, /* INTREQ */ 1164 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1165 }; 1166 1167 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123", 1168 vectors_irq0123, NULL, mask_registers, 1169 prio_registers, sense_registers, ack_registers); 1170 1171 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567", 1172 vectors_irq4567, NULL, mask_registers, 1173 prio_registers, sense_registers, ack_registers); 1174 1175 /* External interrupt pins in IRL mode */ 1176 static struct intc_vect vectors_irl0123[] __initdata = { 1177 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220), 1178 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260), 1179 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0), 1180 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0), 1181 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320), 1182 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360), 1183 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0), 1184 INTC_VECT(IRL0_HHHL, 0x3c0), 1185 }; 1186 1187 static struct intc_vect vectors_irl4567[] __initdata = { 1188 INTC_VECT(IRL4_LLLL, 0x200), INTC_VECT(IRL4_LLLH, 0x220), 1189 INTC_VECT(IRL4_LLHL, 0x240), INTC_VECT(IRL4_LLHH, 0x260), 1190 INTC_VECT(IRL4_LHLL, 0x280), INTC_VECT(IRL4_LHLH, 0x2a0), 1191 INTC_VECT(IRL4_LHHL, 0x2c0), INTC_VECT(IRL4_LHHH, 0x2e0), 1192 INTC_VECT(IRL4_HLLL, 0x300), INTC_VECT(IRL4_HLLH, 0x320), 1193 INTC_VECT(IRL4_HLHL, 0x340), INTC_VECT(IRL4_HLHH, 0x360), 1194 INTC_VECT(IRL4_HHLL, 0x380), INTC_VECT(IRL4_HHLH, 0x3a0), 1195 INTC_VECT(IRL4_HHHL, 0x3c0), 1196 }; 1197 1198 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123, 1199 NULL, mask_registers, NULL, NULL); 1200 1201 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567, 1202 NULL, mask_registers, NULL, NULL); 1203 1204 #define INTC_ICR0 0xffd00000 1205 #define INTC_INTMSK0 0xffd00044 1206 #define INTC_INTMSK1 0xffd00048 1207 #define INTC_INTMSK2 0xffd40080 1208 #define INTC_INTMSKCLR1 0xffd00068 1209 #define INTC_INTMSKCLR2 0xffd40084 1210 1211 void __init plat_irq_setup(void) 1212 { 1213 /* disable IRQ3-0 + IRQ7-4 */ 1214 __raw_writel(0xff000000, INTC_INTMSK0); 1215 1216 /* disable IRL3-0 + IRL7-4 */ 1217 __raw_writel(0xc0000000, INTC_INTMSK1); 1218 __raw_writel(0xfffefffe, INTC_INTMSK2); 1219 1220 /* select IRL mode for IRL3-0 + IRL7-4 */ 1221 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 1222 1223 /* disable holding function, ie enable "SH-4 Mode" */ 1224 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); 1225 1226 register_intc_controller(&intc_desc); 1227 } 1228 1229 void __init plat_irq_setup_pins(int mode) 1230 { 1231 switch (mode) { 1232 case IRQ_MODE_IRQ7654: 1233 /* select IRQ mode for IRL7-4 */ 1234 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0); 1235 register_intc_controller(&intc_desc_irq4567); 1236 break; 1237 case IRQ_MODE_IRQ3210: 1238 /* select IRQ mode for IRL3-0 */ 1239 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); 1240 register_intc_controller(&intc_desc_irq0123); 1241 break; 1242 case IRQ_MODE_IRL7654: 1243 /* enable IRL7-4 but don't provide any masking */ 1244 __raw_writel(0x40000000, INTC_INTMSKCLR1); 1245 __raw_writel(0x0000fffe, INTC_INTMSKCLR2); 1246 break; 1247 case IRQ_MODE_IRL3210: 1248 /* enable IRL0-3 but don't provide any masking */ 1249 __raw_writel(0x80000000, INTC_INTMSKCLR1); 1250 __raw_writel(0xfffe0000, INTC_INTMSKCLR2); 1251 break; 1252 case IRQ_MODE_IRL7654_MASK: 1253 /* enable IRL7-4 and mask using cpu intc controller */ 1254 __raw_writel(0x40000000, INTC_INTMSKCLR1); 1255 register_intc_controller(&intc_desc_irl4567); 1256 break; 1257 case IRQ_MODE_IRL3210_MASK: 1258 /* enable IRL0-3 and mask using cpu intc controller */ 1259 __raw_writel(0x80000000, INTC_INTMSKCLR1); 1260 register_intc_controller(&intc_desc_irl0123); 1261 break; 1262 default: 1263 BUG(); 1264 } 1265 } 1266 1267 void __init plat_mem_setup(void) 1268 { 1269 } 1270