1 /* 2 * arch/sh/kernel/cpu/sh4a/setup-sh7734.c 3 4 * SH7734 Setup 5 * 6 * Copyright (C) 2011,2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 7 * Copyright (C) 2011,2012 Renesas Solutions Corp. 8 * 9 * This file is subject to the terms and conditions of the GNU General Public 10 * License. See the file "COPYING" in the main directory of this archive 11 * for more details. 12 */ 13 14 #include <linux/platform_device.h> 15 #include <linux/init.h> 16 #include <linux/serial.h> 17 #include <linux/mm.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/serial_sci.h> 20 #include <linux/sh_timer.h> 21 #include <linux/io.h> 22 #include <asm/clock.h> 23 #include <asm/irq.h> 24 #include <cpu/sh7734.h> 25 26 /* SCIF */ 27 static struct plat_sci_port scif0_platform_data = { 28 .flags = UPF_BOOT_AUTOCONF, 29 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 30 .type = PORT_SCIF, 31 .regtype = SCIx_SH4_SCIF_REGTYPE, 32 }; 33 34 static struct resource scif0_resources[] = { 35 DEFINE_RES_MEM(0xffe40000, 0x100), 36 DEFINE_RES_IRQ(evt2irq(0x8c0)), 37 }; 38 39 static struct platform_device scif0_device = { 40 .name = "sh-sci", 41 .id = 0, 42 .resource = scif0_resources, 43 .num_resources = ARRAY_SIZE(scif0_resources), 44 .dev = { 45 .platform_data = &scif0_platform_data, 46 }, 47 }; 48 49 static struct plat_sci_port scif1_platform_data = { 50 .flags = UPF_BOOT_AUTOCONF, 51 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 52 .type = PORT_SCIF, 53 .regtype = SCIx_SH4_SCIF_REGTYPE, 54 }; 55 56 static struct resource scif1_resources[] = { 57 DEFINE_RES_MEM(0xffe41000, 0x100), 58 DEFINE_RES_IRQ(evt2irq(0x8e0)), 59 }; 60 61 static struct platform_device scif1_device = { 62 .name = "sh-sci", 63 .id = 1, 64 .resource = scif1_resources, 65 .num_resources = ARRAY_SIZE(scif1_resources), 66 .dev = { 67 .platform_data = &scif1_platform_data, 68 }, 69 }; 70 71 static struct plat_sci_port scif2_platform_data = { 72 .flags = UPF_BOOT_AUTOCONF, 73 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 74 .type = PORT_SCIF, 75 .regtype = SCIx_SH4_SCIF_REGTYPE, 76 }; 77 78 static struct resource scif2_resources[] = { 79 DEFINE_RES_MEM(0xffe42000, 0x100), 80 DEFINE_RES_IRQ(evt2irq(0x900)), 81 }; 82 83 static struct platform_device scif2_device = { 84 .name = "sh-sci", 85 .id = 2, 86 .resource = scif2_resources, 87 .num_resources = ARRAY_SIZE(scif2_resources), 88 .dev = { 89 .platform_data = &scif2_platform_data, 90 }, 91 }; 92 93 static struct plat_sci_port scif3_platform_data = { 94 .flags = UPF_BOOT_AUTOCONF, 95 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 96 .type = PORT_SCIF, 97 .regtype = SCIx_SH4_SCIF_REGTYPE, 98 }; 99 100 static struct resource scif3_resources[] = { 101 DEFINE_RES_MEM(0xffe43000, 0x100), 102 DEFINE_RES_IRQ(evt2irq(0x920)), 103 }; 104 105 static struct platform_device scif3_device = { 106 .name = "sh-sci", 107 .id = 3, 108 .resource = scif3_resources, 109 .num_resources = ARRAY_SIZE(scif3_resources), 110 .dev = { 111 .platform_data = &scif3_platform_data, 112 }, 113 }; 114 115 static struct plat_sci_port scif4_platform_data = { 116 .flags = UPF_BOOT_AUTOCONF, 117 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 118 .type = PORT_SCIF, 119 .regtype = SCIx_SH4_SCIF_REGTYPE, 120 }; 121 122 static struct resource scif4_resources[] = { 123 DEFINE_RES_MEM(0xffe44000, 0x100), 124 DEFINE_RES_IRQ(evt2irq(0x940)), 125 }; 126 127 static struct platform_device scif4_device = { 128 .name = "sh-sci", 129 .id = 4, 130 .resource = scif4_resources, 131 .num_resources = ARRAY_SIZE(scif4_resources), 132 .dev = { 133 .platform_data = &scif4_platform_data, 134 }, 135 }; 136 137 static struct plat_sci_port scif5_platform_data = { 138 .flags = UPF_BOOT_AUTOCONF, 139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 140 .type = PORT_SCIF, 141 .regtype = SCIx_SH4_SCIF_REGTYPE, 142 }; 143 144 static struct resource scif5_resources[] = { 145 DEFINE_RES_MEM(0xffe43000, 0x100), 146 DEFINE_RES_IRQ(evt2irq(0x960)), 147 }; 148 149 static struct platform_device scif5_device = { 150 .name = "sh-sci", 151 .id = 5, 152 .resource = scif5_resources, 153 .num_resources = ARRAY_SIZE(scif5_resources), 154 .dev = { 155 .platform_data = &scif5_platform_data, 156 }, 157 }; 158 159 /* RTC */ 160 static struct resource rtc_resources[] = { 161 [0] = { 162 .name = "rtc", 163 .start = 0xFFFC5000, 164 .end = 0xFFFC5000 + 0x26 - 1, 165 .flags = IORESOURCE_IO, 166 }, 167 [1] = { 168 .start = evt2irq(0xC00), 169 .flags = IORESOURCE_IRQ, 170 }, 171 }; 172 173 static struct platform_device rtc_device = { 174 .name = "sh-rtc", 175 .id = -1, 176 .num_resources = ARRAY_SIZE(rtc_resources), 177 .resource = rtc_resources, 178 }; 179 180 /* I2C 0 */ 181 static struct resource i2c0_resources[] = { 182 [0] = { 183 .name = "IIC0", 184 .start = 0xFFC70000, 185 .end = 0xFFC7000A - 1, 186 .flags = IORESOURCE_MEM, 187 }, 188 [1] = { 189 .start = evt2irq(0x860), 190 .flags = IORESOURCE_IRQ, 191 }, 192 }; 193 194 static struct platform_device i2c0_device = { 195 .name = "i2c-sh7734", 196 .id = 0, 197 .num_resources = ARRAY_SIZE(i2c0_resources), 198 .resource = i2c0_resources, 199 }; 200 201 /* TMU */ 202 static struct sh_timer_config tmu0_platform_data = { 203 .channel_offset = 0x04, 204 .timer_bit = 0, 205 .clockevent_rating = 200, 206 }; 207 208 static struct resource tmu0_resources[] = { 209 [0] = { 210 .start = 0xFFD80008, 211 .end = 0xFFD80014 - 1, 212 .flags = IORESOURCE_MEM, 213 }, 214 [1] = { 215 .start = evt2irq(0x400), 216 .flags = IORESOURCE_IRQ, 217 }, 218 }; 219 220 static struct platform_device tmu0_device = { 221 .name = "sh_tmu", 222 .id = 0, 223 .dev = { 224 .platform_data = &tmu0_platform_data, 225 }, 226 .resource = tmu0_resources, 227 .num_resources = ARRAY_SIZE(tmu0_resources), 228 }; 229 230 static struct sh_timer_config tmu1_platform_data = { 231 .channel_offset = 0x10, 232 .timer_bit = 1, 233 .clocksource_rating = 200, 234 }; 235 236 static struct resource tmu1_resources[] = { 237 [0] = { 238 .start = 0xFFD80014, 239 .end = 0xFFD80020 - 1, 240 .flags = IORESOURCE_MEM, 241 }, 242 [1] = { 243 .start = evt2irq(0x420), 244 .flags = IORESOURCE_IRQ, 245 }, 246 }; 247 248 static struct platform_device tmu1_device = { 249 .name = "sh_tmu", 250 .id = 1, 251 .dev = { 252 .platform_data = &tmu1_platform_data, 253 }, 254 .resource = tmu1_resources, 255 .num_resources = ARRAY_SIZE(tmu1_resources), 256 }; 257 258 static struct sh_timer_config tmu2_platform_data = { 259 .channel_offset = 0x1c, 260 .timer_bit = 2, 261 }; 262 263 static struct resource tmu2_resources[] = { 264 [0] = { 265 .start = 0xFFD80020, 266 .end = 0xFFD80030 - 1, 267 .flags = IORESOURCE_MEM, 268 }, 269 [1] = { 270 .start = evt2irq(0x440), 271 .flags = IORESOURCE_IRQ, 272 }, 273 }; 274 275 static struct platform_device tmu2_device = { 276 .name = "sh_tmu", 277 .id = 2, 278 .dev = { 279 .platform_data = &tmu2_platform_data, 280 }, 281 .resource = tmu2_resources, 282 .num_resources = ARRAY_SIZE(tmu2_resources), 283 }; 284 285 286 static struct sh_timer_config tmu3_platform_data = { 287 .channel_offset = 0x04, 288 .timer_bit = 0, 289 }; 290 291 static struct resource tmu3_resources[] = { 292 [0] = { 293 .start = 0xFFD81008, 294 .end = 0xFFD81014 - 1, 295 .flags = IORESOURCE_MEM, 296 }, 297 [1] = { 298 .start = evt2irq(0x480), 299 .flags = IORESOURCE_IRQ, 300 }, 301 }; 302 303 static struct platform_device tmu3_device = { 304 .name = "sh_tmu", 305 .id = 3, 306 .dev = { 307 .platform_data = &tmu3_platform_data, 308 }, 309 .resource = tmu3_resources, 310 .num_resources = ARRAY_SIZE(tmu3_resources), 311 }; 312 313 static struct sh_timer_config tmu4_platform_data = { 314 .channel_offset = 0x10, 315 .timer_bit = 1, 316 }; 317 318 static struct resource tmu4_resources[] = { 319 [0] = { 320 .start = 0xFFD81014, 321 .end = 0xFFD81020 - 1, 322 .flags = IORESOURCE_MEM, 323 }, 324 [1] = { 325 .start = evt2irq(0x4A0), 326 .flags = IORESOURCE_IRQ, 327 }, 328 }; 329 330 static struct platform_device tmu4_device = { 331 .name = "sh_tmu", 332 .id = 4, 333 .dev = { 334 .platform_data = &tmu4_platform_data, 335 }, 336 .resource = tmu4_resources, 337 .num_resources = ARRAY_SIZE(tmu4_resources), 338 }; 339 340 static struct sh_timer_config tmu5_platform_data = { 341 .channel_offset = 0x1c, 342 .timer_bit = 2, 343 }; 344 345 static struct resource tmu5_resources[] = { 346 [0] = { 347 .start = 0xFFD81020, 348 .end = 0xFFD81030 - 1, 349 .flags = IORESOURCE_MEM, 350 }, 351 [1] = { 352 .start = evt2irq(0x4C0), 353 .flags = IORESOURCE_IRQ, 354 }, 355 }; 356 357 static struct platform_device tmu5_device = { 358 .name = "sh_tmu", 359 .id = 5, 360 .dev = { 361 .platform_data = &tmu5_platform_data, 362 }, 363 .resource = tmu5_resources, 364 .num_resources = ARRAY_SIZE(tmu5_resources), 365 }; 366 367 static struct sh_timer_config tmu6_platform_data = { 368 .channel_offset = 0x4, 369 .timer_bit = 0, 370 }; 371 372 static struct resource tmu6_resources[] = { 373 [0] = { 374 .start = 0xFFD82008, 375 .end = 0xFFD82014 - 1, 376 .flags = IORESOURCE_MEM, 377 }, 378 [1] = { 379 .start = evt2irq(0x500), 380 .flags = IORESOURCE_IRQ, 381 }, 382 }; 383 384 static struct platform_device tmu6_device = { 385 .name = "sh_tmu", 386 .id = 6, 387 .dev = { 388 .platform_data = &tmu6_platform_data, 389 }, 390 .resource = tmu6_resources, 391 .num_resources = ARRAY_SIZE(tmu6_resources), 392 }; 393 394 static struct sh_timer_config tmu7_platform_data = { 395 .channel_offset = 0x10, 396 .timer_bit = 1, 397 }; 398 399 static struct resource tmu7_resources[] = { 400 [0] = { 401 .start = 0xFFD82014, 402 .end = 0xFFD82020 - 1, 403 .flags = IORESOURCE_MEM, 404 }, 405 [1] = { 406 .start = evt2irq(0x520), 407 .flags = IORESOURCE_IRQ, 408 }, 409 }; 410 411 static struct platform_device tmu7_device = { 412 .name = "sh_tmu", 413 .id = 7, 414 .dev = { 415 .platform_data = &tmu7_platform_data, 416 }, 417 .resource = tmu7_resources, 418 .num_resources = ARRAY_SIZE(tmu7_resources), 419 }; 420 421 static struct sh_timer_config tmu8_platform_data = { 422 .channel_offset = 0x1c, 423 .timer_bit = 2, 424 }; 425 426 static struct resource tmu8_resources[] = { 427 [0] = { 428 .start = 0xFFD82020, 429 .end = 0xFFD82030 - 1, 430 .flags = IORESOURCE_MEM, 431 }, 432 [1] = { 433 .start = evt2irq(0x540), 434 .flags = IORESOURCE_IRQ, 435 }, 436 }; 437 438 static struct platform_device tmu8_device = { 439 .name = "sh_tmu", 440 .id = 8, 441 .dev = { 442 .platform_data = &tmu8_platform_data, 443 }, 444 .resource = tmu8_resources, 445 .num_resources = ARRAY_SIZE(tmu8_resources), 446 }; 447 448 static struct platform_device *sh7734_devices[] __initdata = { 449 &scif0_device, 450 &scif1_device, 451 &scif2_device, 452 &scif3_device, 453 &scif4_device, 454 &scif5_device, 455 &tmu0_device, 456 &tmu1_device, 457 &tmu2_device, 458 &tmu3_device, 459 &tmu4_device, 460 &tmu5_device, 461 &tmu6_device, 462 &tmu7_device, 463 &tmu8_device, 464 &rtc_device, 465 }; 466 467 static struct platform_device *sh7734_early_devices[] __initdata = { 468 &scif0_device, 469 &scif1_device, 470 &scif2_device, 471 &scif3_device, 472 &scif4_device, 473 &scif5_device, 474 &tmu0_device, 475 &tmu1_device, 476 &tmu2_device, 477 &tmu3_device, 478 &tmu4_device, 479 &tmu5_device, 480 &tmu6_device, 481 &tmu7_device, 482 &tmu8_device, 483 }; 484 485 void __init plat_early_device_setup(void) 486 { 487 early_platform_add_devices(sh7734_early_devices, 488 ARRAY_SIZE(sh7734_early_devices)); 489 } 490 491 #define GROUP 0 492 enum { 493 UNUSED = 0, 494 495 /* interrupt sources */ 496 497 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, 498 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, 499 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, 500 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 501 502 IRQ0, IRQ1, IRQ2, IRQ3, 503 DU, 504 TMU00, TMU10, TMU20, TMU21, 505 TMU30, TMU40, TMU50, TMU51, 506 TMU60, TMU70, TMU80, 507 RESET_WDT, 508 USB, 509 HUDI, 510 SHDMAC, 511 SSI0, SSI1, SSI2, SSI3, 512 VIN0, 513 RGPVG, 514 _2DG, 515 MMC, 516 HSPI, 517 LBSCATA, 518 I2C0, 519 RCAN0, 520 MIMLB, 521 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, 522 LBSCDMAC0, LBSCDMAC1, LBSCDMAC2, 523 RCAN1, 524 SDHI0, SDHI1, 525 IEBUS, 526 HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18, HPBDMAC19_22, HPBDMAC23_25_27_28, 527 RTC, 528 VIN1, 529 LCDC, 530 SRC0, SRC1, 531 GETHER, 532 SDHI2, 533 GPIO0_3, GPIO4_5, 534 STIF0, STIF1, 535 ADMAC, 536 HIF, 537 FLCTL, 538 ADC, 539 MTU2, 540 RSPI, 541 QSPI, 542 HSCIF, 543 VEU3F_VE3, 544 545 /* Group */ 546 /* Mask */ 547 STIF_M, 548 GPIO_M, 549 HPBDMAC_M, 550 LBSCDMAC_M, 551 RCAN_M, 552 SRC_M, 553 SCIF_M, 554 LCDC_M, 555 _2DG_M, 556 VIN_M, 557 TMU_3_M, 558 TMU_0_M, 559 560 /* Priority */ 561 RCAN_P, 562 LBSCDMAC_P, 563 564 /* Common */ 565 SDHI, 566 SSI, 567 SPI, 568 }; 569 570 static struct intc_vect vectors[] __initdata = { 571 INTC_VECT(DU, 0x3E0), 572 INTC_VECT(TMU00, 0x400), 573 INTC_VECT(TMU10, 0x420), 574 INTC_VECT(TMU20, 0x440), 575 INTC_VECT(TMU30, 0x480), 576 INTC_VECT(TMU40, 0x4A0), 577 INTC_VECT(TMU50, 0x4C0), 578 INTC_VECT(TMU51, 0x4E0), 579 INTC_VECT(TMU60, 0x500), 580 INTC_VECT(TMU70, 0x520), 581 INTC_VECT(TMU80, 0x540), 582 INTC_VECT(RESET_WDT, 0x560), 583 INTC_VECT(USB, 0x580), 584 INTC_VECT(HUDI, 0x600), 585 INTC_VECT(SHDMAC, 0x620), 586 INTC_VECT(SSI0, 0x6C0), 587 INTC_VECT(SSI1, 0x6E0), 588 INTC_VECT(SSI2, 0x700), 589 INTC_VECT(SSI3, 0x720), 590 INTC_VECT(VIN0, 0x740), 591 INTC_VECT(RGPVG, 0x760), 592 INTC_VECT(_2DG, 0x780), 593 INTC_VECT(MMC, 0x7A0), 594 INTC_VECT(HSPI, 0x7E0), 595 INTC_VECT(LBSCATA, 0x840), 596 INTC_VECT(I2C0, 0x860), 597 INTC_VECT(RCAN0, 0x880), 598 INTC_VECT(SCIF0, 0x8A0), 599 INTC_VECT(SCIF1, 0x8C0), 600 INTC_VECT(SCIF2, 0x900), 601 INTC_VECT(SCIF3, 0x920), 602 INTC_VECT(SCIF4, 0x940), 603 INTC_VECT(SCIF5, 0x960), 604 INTC_VECT(LBSCDMAC0, 0x9E0), 605 INTC_VECT(LBSCDMAC1, 0xA00), 606 INTC_VECT(LBSCDMAC2, 0xA20), 607 INTC_VECT(RCAN1, 0xA60), 608 INTC_VECT(SDHI0, 0xAE0), 609 INTC_VECT(SDHI1, 0xB00), 610 INTC_VECT(IEBUS, 0xB20), 611 INTC_VECT(HPBDMAC0_3, 0xB60), 612 INTC_VECT(HPBDMAC4_10, 0xB80), 613 INTC_VECT(HPBDMAC11_18, 0xBA0), 614 INTC_VECT(HPBDMAC19_22, 0xBC0), 615 INTC_VECT(HPBDMAC23_25_27_28, 0xBE0), 616 INTC_VECT(RTC, 0xC00), 617 INTC_VECT(VIN1, 0xC20), 618 INTC_VECT(LCDC, 0xC40), 619 INTC_VECT(SRC0, 0xC60), 620 INTC_VECT(SRC1, 0xC80), 621 INTC_VECT(GETHER, 0xCA0), 622 INTC_VECT(SDHI2, 0xCC0), 623 INTC_VECT(GPIO0_3, 0xCE0), 624 INTC_VECT(GPIO4_5, 0xD00), 625 INTC_VECT(STIF0, 0xD20), 626 INTC_VECT(STIF1, 0xD40), 627 INTC_VECT(ADMAC, 0xDA0), 628 INTC_VECT(HIF, 0xDC0), 629 INTC_VECT(FLCTL, 0xDE0), 630 INTC_VECT(ADC, 0xE00), 631 INTC_VECT(MTU2, 0xE20), 632 INTC_VECT(RSPI, 0xE40), 633 INTC_VECT(QSPI, 0xE60), 634 INTC_VECT(HSCIF, 0xFC0), 635 INTC_VECT(VEU3F_VE3, 0xF40), 636 }; 637 638 static struct intc_group groups[] __initdata = { 639 /* Common */ 640 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2), 641 INTC_GROUP(SPI, HSPI, RSPI, QSPI), 642 INTC_GROUP(SSI, SSI0, SSI1, SSI2, SSI3), 643 644 /* Mask group */ 645 INTC_GROUP(STIF_M, STIF0, STIF1), /* 22 */ 646 INTC_GROUP(GPIO_M, GPIO0_3, GPIO4_5), /* 21 */ 647 INTC_GROUP(HPBDMAC_M, HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18, 648 HPBDMAC19_22, HPBDMAC23_25_27_28), /* 19 */ 649 INTC_GROUP(LBSCDMAC_M, LBSCDMAC0, LBSCDMAC1, LBSCDMAC2), /* 18 */ 650 INTC_GROUP(RCAN_M, RCAN0, RCAN1, IEBUS), /* 17 */ 651 INTC_GROUP(SRC_M, SRC0, SRC1), /* 16 */ 652 INTC_GROUP(SCIF_M, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, 653 HSCIF), /* 14 */ 654 INTC_GROUP(LCDC_M, LCDC, MIMLB), /* 13 */ 655 INTC_GROUP(_2DG_M, _2DG, RGPVG), /* 12 */ 656 INTC_GROUP(VIN_M, VIN0, VIN1), /* 10 */ 657 INTC_GROUP(TMU_3_M, TMU30, TMU40, TMU50, TMU51, 658 TMU60, TMU60, TMU70, TMU80), /* 2 */ 659 INTC_GROUP(TMU_0_M, TMU00, TMU10, TMU20, TMU21), /* 1 */ 660 661 /* Priority group*/ 662 INTC_GROUP(RCAN_P, RCAN0, RCAN1), /* INT2PRI5 */ 663 INTC_GROUP(LBSCDMAC_P, LBSCDMAC0, LBSCDMAC1), /* INT2PRI5 */ 664 }; 665 666 static struct intc_mask_reg mask_registers[] __initdata = { 667 { 0xFF804040, 0xFF804044, 32, /* INT2MSKRG / INT2MSKCR */ 668 { 0, 669 VEU3F_VE3, 670 SDHI, /* SDHI 0-2 */ 671 ADMAC, 672 FLCTL, 673 RESET_WDT, 674 HIF, 675 ADC, 676 MTU2, 677 STIF_M, /* STIF 0,1 */ 678 GPIO_M, /* GPIO 0-5*/ 679 GETHER, 680 HPBDMAC_M, /* HPBDMAC 0_3 - 23_25_27_28 */ 681 LBSCDMAC_M, /* LBSCDMAC 0 - 2 */ 682 RCAN_M, /* RCAN, IEBUS */ 683 SRC_M, /* SRC 0,1 */ 684 LBSCATA, 685 SCIF_M, /* SCIF 0-5, HSCIF */ 686 LCDC_M, /* LCDC, MIMLB */ 687 _2DG_M, /* 2DG, RGPVG */ 688 SPI, /* HSPI, RSPI, QSPI */ 689 VIN_M, /* VIN0, 1 */ 690 SSI, /* SSI 0-3 */ 691 USB, 692 SHDMAC, 693 HUDI, 694 MMC, 695 RTC, 696 I2C0, /* I2C */ /* I2C 0, 1*/ 697 TMU_3_M, /* TMU30 - TMU80 */ 698 TMU_0_M, /* TMU00 - TMU21 */ 699 DU } }, 700 }; 701 702 static struct intc_prio_reg prio_registers[] __initdata = { 703 { 0xFF804000, 0, 32, 8, /* INT2PRI0 */ 704 { DU, TMU00, TMU10, TMU20 } }, 705 { 0xFF804004, 0, 32, 8, /* INT2PRI1 */ 706 { TMU30, TMU60, RTC, SDHI } }, 707 { 0xFF804008, 0, 32, 8, /* INT2PRI2 */ 708 { HUDI, SHDMAC, USB, SSI } }, 709 { 0xFF80400C, 0, 32, 8, /* INT2PRI3 */ 710 { VIN0, SPI, _2DG, LBSCATA } }, 711 { 0xFF804010, 0, 32, 8, /* INT2PRI4 */ 712 { SCIF0, SCIF3, HSCIF, LCDC } }, 713 { 0xFF804014, 0, 32, 8, /* INT2PRI5 */ 714 { RCAN_P, LBSCDMAC_P, LBSCDMAC2, MMC } }, 715 { 0xFF804018, 0, 32, 8, /* INT2PRI6 */ 716 { HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18, HPBDMAC19_22 } }, 717 { 0xFF80401C, 0, 32, 8, /* INT2PRI7 */ 718 { HPBDMAC23_25_27_28, I2C0, SRC0, SRC1 } }, 719 { 0xFF804020, 0, 32, 8, /* INT2PRI8 */ 720 { 0 /* ADIF */, VIN1, RESET_WDT, HIF } }, 721 { 0xFF804024, 0, 32, 8, /* INT2PRI9 */ 722 { ADMAC, FLCTL, GPIO0_3, GPIO4_5 } }, 723 { 0xFF804028, 0, 32, 8, /* INT2PRI10 */ 724 { STIF0, STIF1, VEU3F_VE3, GETHER } }, 725 { 0xFF80402C, 0, 32, 8, /* INT2PRI11 */ 726 { MTU2, RGPVG, MIMLB, IEBUS } }, 727 }; 728 729 static DECLARE_INTC_DESC(intc_desc, "sh7734", vectors, groups, 730 mask_registers, prio_registers, NULL); 731 732 /* Support for external interrupt pins in IRQ mode */ 733 734 static struct intc_vect irq3210_vectors[] __initdata = { 735 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), 736 INTC_VECT(IRQ2, 0x2C0), INTC_VECT(IRQ3, 0x300), 737 }; 738 739 static struct intc_sense_reg irq3210_sense_registers[] __initdata = { 740 { 0xFF80201C, 32, 2, /* ICR1 */ 741 { IRQ0, IRQ1, IRQ2, IRQ3, } }, 742 }; 743 744 static struct intc_mask_reg irq3210_ack_registers[] __initdata = { 745 { 0xFF802024, 0, 32, /* INTREQ */ 746 { IRQ0, IRQ1, IRQ2, IRQ3, } }, 747 }; 748 749 static struct intc_mask_reg irq3210_mask_registers[] __initdata = { 750 { 0xFF802044, 0xFF802064, 32, /* INTMSK0 / INTMSKCLR0 */ 751 { IRQ0, IRQ1, IRQ2, IRQ3, } }, 752 }; 753 754 static struct intc_prio_reg irq3210_prio_registers[] __initdata = { 755 { 0xFF802010, 0, 32, 4, /* INTPRI */ 756 { IRQ0, IRQ1, IRQ2, IRQ3, } }, 757 }; 758 759 static DECLARE_INTC_DESC_ACK(intc_desc_irq3210, "sh7734-irq3210", 760 irq3210_vectors, NULL, 761 irq3210_mask_registers, irq3210_prio_registers, 762 irq3210_sense_registers, irq3210_ack_registers); 763 764 /* External interrupt pins in IRL mode */ 765 766 static struct intc_vect vectors_irl3210[] __initdata = { 767 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220), 768 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260), 769 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0), 770 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0), 771 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320), 772 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360), 773 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0), 774 INTC_VECT(IRL0_HHHL, 0x3c0), 775 }; 776 777 static DECLARE_INTC_DESC(intc_desc_irl3210, "sh7734-irl3210", 778 vectors_irl3210, NULL, mask_registers, NULL, NULL); 779 780 #define INTC_ICR0 0xFF802000 781 #define INTC_INTMSK0 0xFF802044 782 #define INTC_INTMSK1 0xFF802048 783 #define INTC_INTMSKCLR0 0xFF802064 784 #define INTC_INTMSKCLR1 0xFF802068 785 786 void __init plat_irq_setup(void) 787 { 788 /* disable IRQ3-0 */ 789 __raw_writel(0xF0000000, INTC_INTMSK0); 790 791 /* disable IRL3-0 */ 792 __raw_writel(0x80000000, INTC_INTMSK1); 793 794 /* select IRL mode for IRL3-0 */ 795 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00800000, INTC_ICR0); 796 797 /* disable holding function, ie enable "SH-4 Mode (LVLMODE)" */ 798 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); 799 800 register_intc_controller(&intc_desc); 801 } 802 803 void __init plat_irq_setup_pins(int mode) 804 { 805 switch (mode) { 806 case IRQ_MODE_IRQ3210: 807 /* select IRQ mode for IRL3-0 */ 808 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); 809 register_intc_controller(&intc_desc_irq3210); 810 break; 811 case IRQ_MODE_IRL3210: 812 /* enable IRL0-3 but don't provide any masking */ 813 __raw_writel(0x80000000, INTC_INTMSKCLR1); 814 __raw_writel(0xf0000000, INTC_INTMSKCLR0); 815 break; 816 case IRQ_MODE_IRL3210_MASK: 817 /* enable IRL0-3 and mask using cpu intc controller */ 818 __raw_writel(0x80000000, INTC_INTMSKCLR0); 819 register_intc_controller(&intc_desc_irl3210); 820 break; 821 default: 822 BUG(); 823 } 824 } 825