1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * arch/sh/kernel/cpu/sh4a/setup-sh7734.c 4 * 5 * SH7734 Setup 6 * 7 * Copyright (C) 2011,2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 8 * Copyright (C) 2011,2012 Renesas Solutions Corp. 9 */ 10 11 #include <linux/platform_device.h> 12 #include <linux/init.h> 13 #include <linux/serial.h> 14 #include <linux/mm.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/serial_sci.h> 17 #include <linux/sh_timer.h> 18 #include <linux/io.h> 19 #include <asm/clock.h> 20 #include <asm/irq.h> 21 #include <cpu/sh7734.h> 22 23 /* SCIF */ 24 static struct plat_sci_port scif0_platform_data = { 25 .scscr = SCSCR_REIE, 26 .type = PORT_SCIF, 27 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE, 28 }; 29 30 static struct resource scif0_resources[] = { 31 DEFINE_RES_MEM(0xffe40000, 0x100), 32 DEFINE_RES_IRQ(evt2irq(0x8c0)), 33 }; 34 35 static struct platform_device scif0_device = { 36 .name = "sh-sci", 37 .id = 0, 38 .resource = scif0_resources, 39 .num_resources = ARRAY_SIZE(scif0_resources), 40 .dev = { 41 .platform_data = &scif0_platform_data, 42 }, 43 }; 44 45 static struct plat_sci_port scif1_platform_data = { 46 .scscr = SCSCR_REIE, 47 .type = PORT_SCIF, 48 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE, 49 }; 50 51 static struct resource scif1_resources[] = { 52 DEFINE_RES_MEM(0xffe41000, 0x100), 53 DEFINE_RES_IRQ(evt2irq(0x8e0)), 54 }; 55 56 static struct platform_device scif1_device = { 57 .name = "sh-sci", 58 .id = 1, 59 .resource = scif1_resources, 60 .num_resources = ARRAY_SIZE(scif1_resources), 61 .dev = { 62 .platform_data = &scif1_platform_data, 63 }, 64 }; 65 66 static struct plat_sci_port scif2_platform_data = { 67 .scscr = SCSCR_REIE, 68 .type = PORT_SCIF, 69 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE, 70 }; 71 72 static struct resource scif2_resources[] = { 73 DEFINE_RES_MEM(0xffe42000, 0x100), 74 DEFINE_RES_IRQ(evt2irq(0x900)), 75 }; 76 77 static struct platform_device scif2_device = { 78 .name = "sh-sci", 79 .id = 2, 80 .resource = scif2_resources, 81 .num_resources = ARRAY_SIZE(scif2_resources), 82 .dev = { 83 .platform_data = &scif2_platform_data, 84 }, 85 }; 86 87 static struct plat_sci_port scif3_platform_data = { 88 .scscr = SCSCR_REIE | SCSCR_TOIE, 89 .type = PORT_SCIF, 90 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE, 91 }; 92 93 static struct resource scif3_resources[] = { 94 DEFINE_RES_MEM(0xffe43000, 0x100), 95 DEFINE_RES_IRQ(evt2irq(0x920)), 96 }; 97 98 static struct platform_device scif3_device = { 99 .name = "sh-sci", 100 .id = 3, 101 .resource = scif3_resources, 102 .num_resources = ARRAY_SIZE(scif3_resources), 103 .dev = { 104 .platform_data = &scif3_platform_data, 105 }, 106 }; 107 108 static struct plat_sci_port scif4_platform_data = { 109 .scscr = SCSCR_REIE, 110 .type = PORT_SCIF, 111 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE, 112 }; 113 114 static struct resource scif4_resources[] = { 115 DEFINE_RES_MEM(0xffe44000, 0x100), 116 DEFINE_RES_IRQ(evt2irq(0x940)), 117 }; 118 119 static struct platform_device scif4_device = { 120 .name = "sh-sci", 121 .id = 4, 122 .resource = scif4_resources, 123 .num_resources = ARRAY_SIZE(scif4_resources), 124 .dev = { 125 .platform_data = &scif4_platform_data, 126 }, 127 }; 128 129 static struct plat_sci_port scif5_platform_data = { 130 .scscr = SCSCR_REIE, 131 .type = PORT_SCIF, 132 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE, 133 }; 134 135 static struct resource scif5_resources[] = { 136 DEFINE_RES_MEM(0xffe43000, 0x100), 137 DEFINE_RES_IRQ(evt2irq(0x960)), 138 }; 139 140 static struct platform_device scif5_device = { 141 .name = "sh-sci", 142 .id = 5, 143 .resource = scif5_resources, 144 .num_resources = ARRAY_SIZE(scif5_resources), 145 .dev = { 146 .platform_data = &scif5_platform_data, 147 }, 148 }; 149 150 /* RTC */ 151 static struct resource rtc_resources[] = { 152 [0] = { 153 .name = "rtc", 154 .start = 0xFFFC5000, 155 .end = 0xFFFC5000 + 0x26 - 1, 156 .flags = IORESOURCE_IO, 157 }, 158 [1] = { 159 .start = evt2irq(0xC00), 160 .flags = IORESOURCE_IRQ, 161 }, 162 }; 163 164 static struct platform_device rtc_device = { 165 .name = "sh-rtc", 166 .id = -1, 167 .num_resources = ARRAY_SIZE(rtc_resources), 168 .resource = rtc_resources, 169 }; 170 171 /* I2C 0 */ 172 static struct resource i2c0_resources[] = { 173 [0] = { 174 .name = "IIC0", 175 .start = 0xFFC70000, 176 .end = 0xFFC7000A - 1, 177 .flags = IORESOURCE_MEM, 178 }, 179 [1] = { 180 .start = evt2irq(0x860), 181 .flags = IORESOURCE_IRQ, 182 }, 183 }; 184 185 static struct platform_device i2c0_device = { 186 .name = "i2c-sh7734", 187 .id = 0, 188 .num_resources = ARRAY_SIZE(i2c0_resources), 189 .resource = i2c0_resources, 190 }; 191 192 /* TMU */ 193 static struct sh_timer_config tmu0_platform_data = { 194 .channels_mask = 7, 195 }; 196 197 static struct resource tmu0_resources[] = { 198 DEFINE_RES_MEM(0xffd80000, 0x30), 199 DEFINE_RES_IRQ(evt2irq(0x400)), 200 DEFINE_RES_IRQ(evt2irq(0x420)), 201 DEFINE_RES_IRQ(evt2irq(0x440)), 202 }; 203 204 static struct platform_device tmu0_device = { 205 .name = "sh-tmu", 206 .id = 0, 207 .dev = { 208 .platform_data = &tmu0_platform_data, 209 }, 210 .resource = tmu0_resources, 211 .num_resources = ARRAY_SIZE(tmu0_resources), 212 }; 213 214 static struct sh_timer_config tmu1_platform_data = { 215 .channels_mask = 7, 216 }; 217 218 static struct resource tmu1_resources[] = { 219 DEFINE_RES_MEM(0xffd81000, 0x30), 220 DEFINE_RES_IRQ(evt2irq(0x480)), 221 DEFINE_RES_IRQ(evt2irq(0x4a0)), 222 DEFINE_RES_IRQ(evt2irq(0x4c0)), 223 }; 224 225 static struct platform_device tmu1_device = { 226 .name = "sh-tmu", 227 .id = 1, 228 .dev = { 229 .platform_data = &tmu1_platform_data, 230 }, 231 .resource = tmu1_resources, 232 .num_resources = ARRAY_SIZE(tmu1_resources), 233 }; 234 235 static struct sh_timer_config tmu2_platform_data = { 236 .channels_mask = 7, 237 }; 238 239 static struct resource tmu2_resources[] = { 240 DEFINE_RES_MEM(0xffd82000, 0x30), 241 DEFINE_RES_IRQ(evt2irq(0x500)), 242 DEFINE_RES_IRQ(evt2irq(0x520)), 243 DEFINE_RES_IRQ(evt2irq(0x540)), 244 }; 245 246 static struct platform_device tmu2_device = { 247 .name = "sh-tmu", 248 .id = 2, 249 .dev = { 250 .platform_data = &tmu2_platform_data, 251 }, 252 .resource = tmu2_resources, 253 .num_resources = ARRAY_SIZE(tmu2_resources), 254 }; 255 256 static struct platform_device *sh7734_devices[] __initdata = { 257 &scif0_device, 258 &scif1_device, 259 &scif2_device, 260 &scif3_device, 261 &scif4_device, 262 &scif5_device, 263 &tmu0_device, 264 &tmu1_device, 265 &tmu2_device, 266 &rtc_device, 267 }; 268 269 static struct platform_device *sh7734_early_devices[] __initdata = { 270 &scif0_device, 271 &scif1_device, 272 &scif2_device, 273 &scif3_device, 274 &scif4_device, 275 &scif5_device, 276 &tmu0_device, 277 &tmu1_device, 278 &tmu2_device, 279 }; 280 281 void __init plat_early_device_setup(void) 282 { 283 early_platform_add_devices(sh7734_early_devices, 284 ARRAY_SIZE(sh7734_early_devices)); 285 } 286 287 #define GROUP 0 288 enum { 289 UNUSED = 0, 290 291 /* interrupt sources */ 292 293 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, 294 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, 295 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, 296 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 297 298 IRQ0, IRQ1, IRQ2, IRQ3, 299 DU, 300 TMU00, TMU10, TMU20, TMU21, 301 TMU30, TMU40, TMU50, TMU51, 302 TMU60, TMU70, TMU80, 303 RESET_WDT, 304 USB, 305 HUDI, 306 SHDMAC, 307 SSI0, SSI1, SSI2, SSI3, 308 VIN0, 309 RGPVG, 310 _2DG, 311 MMC, 312 HSPI, 313 LBSCATA, 314 I2C0, 315 RCAN0, 316 MIMLB, 317 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, 318 LBSCDMAC0, LBSCDMAC1, LBSCDMAC2, 319 RCAN1, 320 SDHI0, SDHI1, 321 IEBUS, 322 HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18, HPBDMAC19_22, HPBDMAC23_25_27_28, 323 RTC, 324 VIN1, 325 LCDC, 326 SRC0, SRC1, 327 GETHER, 328 SDHI2, 329 GPIO0_3, GPIO4_5, 330 STIF0, STIF1, 331 ADMAC, 332 HIF, 333 FLCTL, 334 ADC, 335 MTU2, 336 RSPI, 337 QSPI, 338 HSCIF, 339 VEU3F_VE3, 340 341 /* Group */ 342 /* Mask */ 343 STIF_M, 344 GPIO_M, 345 HPBDMAC_M, 346 LBSCDMAC_M, 347 RCAN_M, 348 SRC_M, 349 SCIF_M, 350 LCDC_M, 351 _2DG_M, 352 VIN_M, 353 TMU_3_M, 354 TMU_0_M, 355 356 /* Priority */ 357 RCAN_P, 358 LBSCDMAC_P, 359 360 /* Common */ 361 SDHI, 362 SSI, 363 SPI, 364 }; 365 366 static struct intc_vect vectors[] __initdata = { 367 INTC_VECT(DU, 0x3E0), 368 INTC_VECT(TMU00, 0x400), 369 INTC_VECT(TMU10, 0x420), 370 INTC_VECT(TMU20, 0x440), 371 INTC_VECT(TMU30, 0x480), 372 INTC_VECT(TMU40, 0x4A0), 373 INTC_VECT(TMU50, 0x4C0), 374 INTC_VECT(TMU51, 0x4E0), 375 INTC_VECT(TMU60, 0x500), 376 INTC_VECT(TMU70, 0x520), 377 INTC_VECT(TMU80, 0x540), 378 INTC_VECT(RESET_WDT, 0x560), 379 INTC_VECT(USB, 0x580), 380 INTC_VECT(HUDI, 0x600), 381 INTC_VECT(SHDMAC, 0x620), 382 INTC_VECT(SSI0, 0x6C0), 383 INTC_VECT(SSI1, 0x6E0), 384 INTC_VECT(SSI2, 0x700), 385 INTC_VECT(SSI3, 0x720), 386 INTC_VECT(VIN0, 0x740), 387 INTC_VECT(RGPVG, 0x760), 388 INTC_VECT(_2DG, 0x780), 389 INTC_VECT(MMC, 0x7A0), 390 INTC_VECT(HSPI, 0x7E0), 391 INTC_VECT(LBSCATA, 0x840), 392 INTC_VECT(I2C0, 0x860), 393 INTC_VECT(RCAN0, 0x880), 394 INTC_VECT(SCIF0, 0x8A0), 395 INTC_VECT(SCIF1, 0x8C0), 396 INTC_VECT(SCIF2, 0x900), 397 INTC_VECT(SCIF3, 0x920), 398 INTC_VECT(SCIF4, 0x940), 399 INTC_VECT(SCIF5, 0x960), 400 INTC_VECT(LBSCDMAC0, 0x9E0), 401 INTC_VECT(LBSCDMAC1, 0xA00), 402 INTC_VECT(LBSCDMAC2, 0xA20), 403 INTC_VECT(RCAN1, 0xA60), 404 INTC_VECT(SDHI0, 0xAE0), 405 INTC_VECT(SDHI1, 0xB00), 406 INTC_VECT(IEBUS, 0xB20), 407 INTC_VECT(HPBDMAC0_3, 0xB60), 408 INTC_VECT(HPBDMAC4_10, 0xB80), 409 INTC_VECT(HPBDMAC11_18, 0xBA0), 410 INTC_VECT(HPBDMAC19_22, 0xBC0), 411 INTC_VECT(HPBDMAC23_25_27_28, 0xBE0), 412 INTC_VECT(RTC, 0xC00), 413 INTC_VECT(VIN1, 0xC20), 414 INTC_VECT(LCDC, 0xC40), 415 INTC_VECT(SRC0, 0xC60), 416 INTC_VECT(SRC1, 0xC80), 417 INTC_VECT(GETHER, 0xCA0), 418 INTC_VECT(SDHI2, 0xCC0), 419 INTC_VECT(GPIO0_3, 0xCE0), 420 INTC_VECT(GPIO4_5, 0xD00), 421 INTC_VECT(STIF0, 0xD20), 422 INTC_VECT(STIF1, 0xD40), 423 INTC_VECT(ADMAC, 0xDA0), 424 INTC_VECT(HIF, 0xDC0), 425 INTC_VECT(FLCTL, 0xDE0), 426 INTC_VECT(ADC, 0xE00), 427 INTC_VECT(MTU2, 0xE20), 428 INTC_VECT(RSPI, 0xE40), 429 INTC_VECT(QSPI, 0xE60), 430 INTC_VECT(HSCIF, 0xFC0), 431 INTC_VECT(VEU3F_VE3, 0xF40), 432 }; 433 434 static struct intc_group groups[] __initdata = { 435 /* Common */ 436 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2), 437 INTC_GROUP(SPI, HSPI, RSPI, QSPI), 438 INTC_GROUP(SSI, SSI0, SSI1, SSI2, SSI3), 439 440 /* Mask group */ 441 INTC_GROUP(STIF_M, STIF0, STIF1), /* 22 */ 442 INTC_GROUP(GPIO_M, GPIO0_3, GPIO4_5), /* 21 */ 443 INTC_GROUP(HPBDMAC_M, HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18, 444 HPBDMAC19_22, HPBDMAC23_25_27_28), /* 19 */ 445 INTC_GROUP(LBSCDMAC_M, LBSCDMAC0, LBSCDMAC1, LBSCDMAC2), /* 18 */ 446 INTC_GROUP(RCAN_M, RCAN0, RCAN1, IEBUS), /* 17 */ 447 INTC_GROUP(SRC_M, SRC0, SRC1), /* 16 */ 448 INTC_GROUP(SCIF_M, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, 449 HSCIF), /* 14 */ 450 INTC_GROUP(LCDC_M, LCDC, MIMLB), /* 13 */ 451 INTC_GROUP(_2DG_M, _2DG, RGPVG), /* 12 */ 452 INTC_GROUP(VIN_M, VIN0, VIN1), /* 10 */ 453 INTC_GROUP(TMU_3_M, TMU30, TMU40, TMU50, TMU51, 454 TMU60, TMU60, TMU70, TMU80), /* 2 */ 455 INTC_GROUP(TMU_0_M, TMU00, TMU10, TMU20, TMU21), /* 1 */ 456 457 /* Priority group*/ 458 INTC_GROUP(RCAN_P, RCAN0, RCAN1), /* INT2PRI5 */ 459 INTC_GROUP(LBSCDMAC_P, LBSCDMAC0, LBSCDMAC1), /* INT2PRI5 */ 460 }; 461 462 static struct intc_mask_reg mask_registers[] __initdata = { 463 { 0xFF804040, 0xFF804044, 32, /* INT2MSKRG / INT2MSKCR */ 464 { 0, 465 VEU3F_VE3, 466 SDHI, /* SDHI 0-2 */ 467 ADMAC, 468 FLCTL, 469 RESET_WDT, 470 HIF, 471 ADC, 472 MTU2, 473 STIF_M, /* STIF 0,1 */ 474 GPIO_M, /* GPIO 0-5*/ 475 GETHER, 476 HPBDMAC_M, /* HPBDMAC 0_3 - 23_25_27_28 */ 477 LBSCDMAC_M, /* LBSCDMAC 0 - 2 */ 478 RCAN_M, /* RCAN, IEBUS */ 479 SRC_M, /* SRC 0,1 */ 480 LBSCATA, 481 SCIF_M, /* SCIF 0-5, HSCIF */ 482 LCDC_M, /* LCDC, MIMLB */ 483 _2DG_M, /* 2DG, RGPVG */ 484 SPI, /* HSPI, RSPI, QSPI */ 485 VIN_M, /* VIN0, 1 */ 486 SSI, /* SSI 0-3 */ 487 USB, 488 SHDMAC, 489 HUDI, 490 MMC, 491 RTC, 492 I2C0, /* I2C */ /* I2C 0, 1*/ 493 TMU_3_M, /* TMU30 - TMU80 */ 494 TMU_0_M, /* TMU00 - TMU21 */ 495 DU } }, 496 }; 497 498 static struct intc_prio_reg prio_registers[] __initdata = { 499 { 0xFF804000, 0, 32, 8, /* INT2PRI0 */ 500 { DU, TMU00, TMU10, TMU20 } }, 501 { 0xFF804004, 0, 32, 8, /* INT2PRI1 */ 502 { TMU30, TMU60, RTC, SDHI } }, 503 { 0xFF804008, 0, 32, 8, /* INT2PRI2 */ 504 { HUDI, SHDMAC, USB, SSI } }, 505 { 0xFF80400C, 0, 32, 8, /* INT2PRI3 */ 506 { VIN0, SPI, _2DG, LBSCATA } }, 507 { 0xFF804010, 0, 32, 8, /* INT2PRI4 */ 508 { SCIF0, SCIF3, HSCIF, LCDC } }, 509 { 0xFF804014, 0, 32, 8, /* INT2PRI5 */ 510 { RCAN_P, LBSCDMAC_P, LBSCDMAC2, MMC } }, 511 { 0xFF804018, 0, 32, 8, /* INT2PRI6 */ 512 { HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18, HPBDMAC19_22 } }, 513 { 0xFF80401C, 0, 32, 8, /* INT2PRI7 */ 514 { HPBDMAC23_25_27_28, I2C0, SRC0, SRC1 } }, 515 { 0xFF804020, 0, 32, 8, /* INT2PRI8 */ 516 { 0 /* ADIF */, VIN1, RESET_WDT, HIF } }, 517 { 0xFF804024, 0, 32, 8, /* INT2PRI9 */ 518 { ADMAC, FLCTL, GPIO0_3, GPIO4_5 } }, 519 { 0xFF804028, 0, 32, 8, /* INT2PRI10 */ 520 { STIF0, STIF1, VEU3F_VE3, GETHER } }, 521 { 0xFF80402C, 0, 32, 8, /* INT2PRI11 */ 522 { MTU2, RGPVG, MIMLB, IEBUS } }, 523 }; 524 525 static DECLARE_INTC_DESC(intc_desc, "sh7734", vectors, groups, 526 mask_registers, prio_registers, NULL); 527 528 /* Support for external interrupt pins in IRQ mode */ 529 530 static struct intc_vect irq3210_vectors[] __initdata = { 531 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), 532 INTC_VECT(IRQ2, 0x2C0), INTC_VECT(IRQ3, 0x300), 533 }; 534 535 static struct intc_sense_reg irq3210_sense_registers[] __initdata = { 536 { 0xFF80201C, 32, 2, /* ICR1 */ 537 { IRQ0, IRQ1, IRQ2, IRQ3, } }, 538 }; 539 540 static struct intc_mask_reg irq3210_ack_registers[] __initdata = { 541 { 0xFF802024, 0, 32, /* INTREQ */ 542 { IRQ0, IRQ1, IRQ2, IRQ3, } }, 543 }; 544 545 static struct intc_mask_reg irq3210_mask_registers[] __initdata = { 546 { 0xFF802044, 0xFF802064, 32, /* INTMSK0 / INTMSKCLR0 */ 547 { IRQ0, IRQ1, IRQ2, IRQ3, } }, 548 }; 549 550 static struct intc_prio_reg irq3210_prio_registers[] __initdata = { 551 { 0xFF802010, 0, 32, 4, /* INTPRI */ 552 { IRQ0, IRQ1, IRQ2, IRQ3, } }, 553 }; 554 555 static DECLARE_INTC_DESC_ACK(intc_desc_irq3210, "sh7734-irq3210", 556 irq3210_vectors, NULL, 557 irq3210_mask_registers, irq3210_prio_registers, 558 irq3210_sense_registers, irq3210_ack_registers); 559 560 /* External interrupt pins in IRL mode */ 561 562 static struct intc_vect vectors_irl3210[] __initdata = { 563 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220), 564 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260), 565 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0), 566 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0), 567 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320), 568 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360), 569 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0), 570 INTC_VECT(IRL0_HHHL, 0x3c0), 571 }; 572 573 static DECLARE_INTC_DESC(intc_desc_irl3210, "sh7734-irl3210", 574 vectors_irl3210, NULL, mask_registers, NULL, NULL); 575 576 #define INTC_ICR0 0xFF802000 577 #define INTC_INTMSK0 0xFF802044 578 #define INTC_INTMSK1 0xFF802048 579 #define INTC_INTMSKCLR0 0xFF802064 580 #define INTC_INTMSKCLR1 0xFF802068 581 582 void __init plat_irq_setup(void) 583 { 584 /* disable IRQ3-0 */ 585 __raw_writel(0xF0000000, INTC_INTMSK0); 586 587 /* disable IRL3-0 */ 588 __raw_writel(0x80000000, INTC_INTMSK1); 589 590 /* select IRL mode for IRL3-0 */ 591 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00800000, INTC_ICR0); 592 593 /* disable holding function, ie enable "SH-4 Mode (LVLMODE)" */ 594 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); 595 596 register_intc_controller(&intc_desc); 597 } 598 599 void __init plat_irq_setup_pins(int mode) 600 { 601 switch (mode) { 602 case IRQ_MODE_IRQ3210: 603 /* select IRQ mode for IRL3-0 */ 604 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); 605 register_intc_controller(&intc_desc_irq3210); 606 break; 607 case IRQ_MODE_IRL3210: 608 /* enable IRL0-3 but don't provide any masking */ 609 __raw_writel(0x80000000, INTC_INTMSKCLR1); 610 __raw_writel(0xf0000000, INTC_INTMSKCLR0); 611 break; 612 case IRQ_MODE_IRL3210_MASK: 613 /* enable IRL0-3 and mask using cpu intc controller */ 614 __raw_writel(0x80000000, INTC_INTMSKCLR0); 615 register_intc_controller(&intc_desc_irl3210); 616 break; 617 default: 618 BUG(); 619 } 620 } 621