1 /* 2 * SH7724 Setup 3 * 4 * Copyright (C) 2009 Renesas Solutions Corp. 5 * 6 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 7 * 8 * Based on SH7723 Setup 9 * Copyright (C) 2008 Paul Mundt 10 * 11 * This file is subject to the terms and conditions of the GNU General Public 12 * License. See the file "COPYING" in the main directory of this archive 13 * for more details. 14 */ 15 #include <linux/platform_device.h> 16 #include <linux/init.h> 17 #include <linux/serial.h> 18 #include <linux/mm.h> 19 #include <linux/serial_sci.h> 20 #include <linux/uio_driver.h> 21 #include <linux/sh_dma.h> 22 #include <linux/sh_timer.h> 23 #include <linux/io.h> 24 #include <linux/notifier.h> 25 26 #include <asm/suspend.h> 27 #include <asm/clock.h> 28 #include <asm/mmzone.h> 29 30 #include <cpu/dma-register.h> 31 #include <cpu/sh7724.h> 32 33 /* DMA */ 34 static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = { 35 { 36 .slave_id = SHDMA_SLAVE_SCIF0_TX, 37 .addr = 0xffe0000c, 38 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 39 .mid_rid = 0x21, 40 }, { 41 .slave_id = SHDMA_SLAVE_SCIF0_RX, 42 .addr = 0xffe00014, 43 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 44 .mid_rid = 0x22, 45 }, { 46 .slave_id = SHDMA_SLAVE_SCIF1_TX, 47 .addr = 0xffe1000c, 48 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 49 .mid_rid = 0x25, 50 }, { 51 .slave_id = SHDMA_SLAVE_SCIF1_RX, 52 .addr = 0xffe10014, 53 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 54 .mid_rid = 0x26, 55 }, { 56 .slave_id = SHDMA_SLAVE_SCIF2_TX, 57 .addr = 0xffe2000c, 58 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 59 .mid_rid = 0x29, 60 }, { 61 .slave_id = SHDMA_SLAVE_SCIF2_RX, 62 .addr = 0xffe20014, 63 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 64 .mid_rid = 0x2a, 65 }, { 66 .slave_id = SHDMA_SLAVE_SCIF3_TX, 67 .addr = 0xa4e30020, 68 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 69 .mid_rid = 0x2d, 70 }, { 71 .slave_id = SHDMA_SLAVE_SCIF3_RX, 72 .addr = 0xa4e30024, 73 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 74 .mid_rid = 0x2e, 75 }, { 76 .slave_id = SHDMA_SLAVE_SCIF4_TX, 77 .addr = 0xa4e40020, 78 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 79 .mid_rid = 0x31, 80 }, { 81 .slave_id = SHDMA_SLAVE_SCIF4_RX, 82 .addr = 0xa4e40024, 83 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 84 .mid_rid = 0x32, 85 }, { 86 .slave_id = SHDMA_SLAVE_SCIF5_TX, 87 .addr = 0xa4e50020, 88 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 89 .mid_rid = 0x35, 90 }, { 91 .slave_id = SHDMA_SLAVE_SCIF5_RX, 92 .addr = 0xa4e50024, 93 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 94 .mid_rid = 0x36, 95 }, { 96 .slave_id = SHDMA_SLAVE_SDHI0_TX, 97 .addr = 0x04ce0030, 98 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 99 .mid_rid = 0xc1, 100 }, { 101 .slave_id = SHDMA_SLAVE_SDHI0_RX, 102 .addr = 0x04ce0030, 103 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 104 .mid_rid = 0xc2, 105 }, { 106 .slave_id = SHDMA_SLAVE_SDHI1_TX, 107 .addr = 0x04cf0030, 108 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 109 .mid_rid = 0xc9, 110 }, { 111 .slave_id = SHDMA_SLAVE_SDHI1_RX, 112 .addr = 0x04cf0030, 113 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 114 .mid_rid = 0xca, 115 }, 116 }; 117 118 static const struct sh_dmae_channel sh7724_dmae_channels[] = { 119 { 120 .offset = 0, 121 .dmars = 0, 122 .dmars_bit = 0, 123 }, { 124 .offset = 0x10, 125 .dmars = 0, 126 .dmars_bit = 8, 127 }, { 128 .offset = 0x20, 129 .dmars = 4, 130 .dmars_bit = 0, 131 }, { 132 .offset = 0x30, 133 .dmars = 4, 134 .dmars_bit = 8, 135 }, { 136 .offset = 0x50, 137 .dmars = 8, 138 .dmars_bit = 0, 139 }, { 140 .offset = 0x60, 141 .dmars = 8, 142 .dmars_bit = 8, 143 } 144 }; 145 146 static const unsigned int ts_shift[] = TS_SHIFT; 147 148 static struct sh_dmae_pdata dma_platform_data = { 149 .slave = sh7724_dmae_slaves, 150 .slave_num = ARRAY_SIZE(sh7724_dmae_slaves), 151 .channel = sh7724_dmae_channels, 152 .channel_num = ARRAY_SIZE(sh7724_dmae_channels), 153 .ts_low_shift = CHCR_TS_LOW_SHIFT, 154 .ts_low_mask = CHCR_TS_LOW_MASK, 155 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 156 .ts_high_mask = CHCR_TS_HIGH_MASK, 157 .ts_shift = ts_shift, 158 .ts_shift_num = ARRAY_SIZE(ts_shift), 159 .dmaor_init = DMAOR_INIT, 160 }; 161 162 /* Resource order important! */ 163 static struct resource sh7724_dmae0_resources[] = { 164 { 165 /* Channel registers and DMAOR */ 166 .start = 0xfe008020, 167 .end = 0xfe00808f, 168 .flags = IORESOURCE_MEM, 169 }, 170 { 171 /* DMARSx */ 172 .start = 0xfe009000, 173 .end = 0xfe00900b, 174 .flags = IORESOURCE_MEM, 175 }, 176 { 177 /* DMA error IRQ */ 178 .start = 78, 179 .end = 78, 180 .flags = IORESOURCE_IRQ, 181 }, 182 { 183 /* IRQ for channels 0-3 */ 184 .start = 48, 185 .end = 51, 186 .flags = IORESOURCE_IRQ, 187 }, 188 { 189 /* IRQ for channels 4-5 */ 190 .start = 76, 191 .end = 77, 192 .flags = IORESOURCE_IRQ, 193 }, 194 }; 195 196 /* Resource order important! */ 197 static struct resource sh7724_dmae1_resources[] = { 198 { 199 /* Channel registers and DMAOR */ 200 .start = 0xfdc08020, 201 .end = 0xfdc0808f, 202 .flags = IORESOURCE_MEM, 203 }, 204 { 205 /* DMARSx */ 206 .start = 0xfdc09000, 207 .end = 0xfdc0900b, 208 .flags = IORESOURCE_MEM, 209 }, 210 { 211 /* DMA error IRQ */ 212 .start = 74, 213 .end = 74, 214 .flags = IORESOURCE_IRQ, 215 }, 216 { 217 /* IRQ for channels 0-3 */ 218 .start = 40, 219 .end = 43, 220 .flags = IORESOURCE_IRQ, 221 }, 222 { 223 /* IRQ for channels 4-5 */ 224 .start = 72, 225 .end = 73, 226 .flags = IORESOURCE_IRQ, 227 }, 228 }; 229 230 static struct platform_device dma0_device = { 231 .name = "sh-dma-engine", 232 .id = 0, 233 .resource = sh7724_dmae0_resources, 234 .num_resources = ARRAY_SIZE(sh7724_dmae0_resources), 235 .dev = { 236 .platform_data = &dma_platform_data, 237 }, 238 .archdata = { 239 .hwblk_id = HWBLK_DMAC0, 240 }, 241 }; 242 243 static struct platform_device dma1_device = { 244 .name = "sh-dma-engine", 245 .id = 1, 246 .resource = sh7724_dmae1_resources, 247 .num_resources = ARRAY_SIZE(sh7724_dmae1_resources), 248 .dev = { 249 .platform_data = &dma_platform_data, 250 }, 251 .archdata = { 252 .hwblk_id = HWBLK_DMAC1, 253 }, 254 }; 255 256 /* Serial */ 257 static struct plat_sci_port scif0_platform_data = { 258 .mapbase = 0xffe00000, 259 .flags = UPF_BOOT_AUTOCONF, 260 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 261 .scbrr_algo_id = SCBRR_ALGO_2, 262 .type = PORT_SCIF, 263 .irqs = { 80, 80, 80, 80 }, 264 }; 265 266 static struct platform_device scif0_device = { 267 .name = "sh-sci", 268 .id = 0, 269 .dev = { 270 .platform_data = &scif0_platform_data, 271 }, 272 }; 273 274 static struct plat_sci_port scif1_platform_data = { 275 .mapbase = 0xffe10000, 276 .flags = UPF_BOOT_AUTOCONF, 277 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 278 .scbrr_algo_id = SCBRR_ALGO_2, 279 .type = PORT_SCIF, 280 .irqs = { 81, 81, 81, 81 }, 281 }; 282 283 static struct platform_device scif1_device = { 284 .name = "sh-sci", 285 .id = 1, 286 .dev = { 287 .platform_data = &scif1_platform_data, 288 }, 289 }; 290 291 static struct plat_sci_port scif2_platform_data = { 292 .mapbase = 0xffe20000, 293 .flags = UPF_BOOT_AUTOCONF, 294 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 295 .scbrr_algo_id = SCBRR_ALGO_2, 296 .type = PORT_SCIF, 297 .irqs = { 82, 82, 82, 82 }, 298 }; 299 300 static struct platform_device scif2_device = { 301 .name = "sh-sci", 302 .id = 2, 303 .dev = { 304 .platform_data = &scif2_platform_data, 305 }, 306 }; 307 308 static struct plat_sci_port scif3_platform_data = { 309 .mapbase = 0xa4e30000, 310 .flags = UPF_BOOT_AUTOCONF, 311 .scscr = SCSCR_RE | SCSCR_TE, 312 .scbrr_algo_id = SCBRR_ALGO_3, 313 .type = PORT_SCIFA, 314 .irqs = { 56, 56, 56, 56 }, 315 }; 316 317 static struct platform_device scif3_device = { 318 .name = "sh-sci", 319 .id = 3, 320 .dev = { 321 .platform_data = &scif3_platform_data, 322 }, 323 }; 324 325 static struct plat_sci_port scif4_platform_data = { 326 .mapbase = 0xa4e40000, 327 .flags = UPF_BOOT_AUTOCONF, 328 .scscr = SCSCR_RE | SCSCR_TE, 329 .scbrr_algo_id = SCBRR_ALGO_3, 330 .type = PORT_SCIFA, 331 .irqs = { 88, 88, 88, 88 }, 332 }; 333 334 static struct platform_device scif4_device = { 335 .name = "sh-sci", 336 .id = 4, 337 .dev = { 338 .platform_data = &scif4_platform_data, 339 }, 340 }; 341 342 static struct plat_sci_port scif5_platform_data = { 343 .mapbase = 0xa4e50000, 344 .flags = UPF_BOOT_AUTOCONF, 345 .scscr = SCSCR_RE | SCSCR_TE, 346 .scbrr_algo_id = SCBRR_ALGO_3, 347 .type = PORT_SCIFA, 348 .irqs = { 109, 109, 109, 109 }, 349 }; 350 351 static struct platform_device scif5_device = { 352 .name = "sh-sci", 353 .id = 5, 354 .dev = { 355 .platform_data = &scif5_platform_data, 356 }, 357 }; 358 359 /* RTC */ 360 static struct resource rtc_resources[] = { 361 [0] = { 362 .start = 0xa465fec0, 363 .end = 0xa465fec0 + 0x58 - 1, 364 .flags = IORESOURCE_IO, 365 }, 366 [1] = { 367 /* Period IRQ */ 368 .start = 69, 369 .flags = IORESOURCE_IRQ, 370 }, 371 [2] = { 372 /* Carry IRQ */ 373 .start = 70, 374 .flags = IORESOURCE_IRQ, 375 }, 376 [3] = { 377 /* Alarm IRQ */ 378 .start = 68, 379 .flags = IORESOURCE_IRQ, 380 }, 381 }; 382 383 static struct platform_device rtc_device = { 384 .name = "sh-rtc", 385 .id = -1, 386 .num_resources = ARRAY_SIZE(rtc_resources), 387 .resource = rtc_resources, 388 .archdata = { 389 .hwblk_id = HWBLK_RTC, 390 }, 391 }; 392 393 /* I2C0 */ 394 static struct resource iic0_resources[] = { 395 [0] = { 396 .name = "IIC0", 397 .start = 0x04470000, 398 .end = 0x04470018 - 1, 399 .flags = IORESOURCE_MEM, 400 }, 401 [1] = { 402 .start = 96, 403 .end = 99, 404 .flags = IORESOURCE_IRQ, 405 }, 406 }; 407 408 static struct platform_device iic0_device = { 409 .name = "i2c-sh_mobile", 410 .id = 0, /* "i2c0" clock */ 411 .num_resources = ARRAY_SIZE(iic0_resources), 412 .resource = iic0_resources, 413 .archdata = { 414 .hwblk_id = HWBLK_IIC0, 415 }, 416 }; 417 418 /* I2C1 */ 419 static struct resource iic1_resources[] = { 420 [0] = { 421 .name = "IIC1", 422 .start = 0x04750000, 423 .end = 0x04750018 - 1, 424 .flags = IORESOURCE_MEM, 425 }, 426 [1] = { 427 .start = 92, 428 .end = 95, 429 .flags = IORESOURCE_IRQ, 430 }, 431 }; 432 433 static struct platform_device iic1_device = { 434 .name = "i2c-sh_mobile", 435 .id = 1, /* "i2c1" clock */ 436 .num_resources = ARRAY_SIZE(iic1_resources), 437 .resource = iic1_resources, 438 .archdata = { 439 .hwblk_id = HWBLK_IIC1, 440 }, 441 }; 442 443 /* VPU */ 444 static struct uio_info vpu_platform_data = { 445 .name = "VPU5F", 446 .version = "0", 447 .irq = 60, 448 }; 449 450 static struct resource vpu_resources[] = { 451 [0] = { 452 .name = "VPU", 453 .start = 0xfe900000, 454 .end = 0xfe902807, 455 .flags = IORESOURCE_MEM, 456 }, 457 [1] = { 458 /* place holder for contiguous memory */ 459 }, 460 }; 461 462 static struct platform_device vpu_device = { 463 .name = "uio_pdrv_genirq", 464 .id = 0, 465 .dev = { 466 .platform_data = &vpu_platform_data, 467 }, 468 .resource = vpu_resources, 469 .num_resources = ARRAY_SIZE(vpu_resources), 470 .archdata = { 471 .hwblk_id = HWBLK_VPU, 472 }, 473 }; 474 475 /* VEU0 */ 476 static struct uio_info veu0_platform_data = { 477 .name = "VEU3F0", 478 .version = "0", 479 .irq = 83, 480 }; 481 482 static struct resource veu0_resources[] = { 483 [0] = { 484 .name = "VEU3F0", 485 .start = 0xfe920000, 486 .end = 0xfe9200cb, 487 .flags = IORESOURCE_MEM, 488 }, 489 [1] = { 490 /* place holder for contiguous memory */ 491 }, 492 }; 493 494 static struct platform_device veu0_device = { 495 .name = "uio_pdrv_genirq", 496 .id = 1, 497 .dev = { 498 .platform_data = &veu0_platform_data, 499 }, 500 .resource = veu0_resources, 501 .num_resources = ARRAY_SIZE(veu0_resources), 502 .archdata = { 503 .hwblk_id = HWBLK_VEU0, 504 }, 505 }; 506 507 /* VEU1 */ 508 static struct uio_info veu1_platform_data = { 509 .name = "VEU3F1", 510 .version = "0", 511 .irq = 54, 512 }; 513 514 static struct resource veu1_resources[] = { 515 [0] = { 516 .name = "VEU3F1", 517 .start = 0xfe924000, 518 .end = 0xfe9240cb, 519 .flags = IORESOURCE_MEM, 520 }, 521 [1] = { 522 /* place holder for contiguous memory */ 523 }, 524 }; 525 526 static struct platform_device veu1_device = { 527 .name = "uio_pdrv_genirq", 528 .id = 2, 529 .dev = { 530 .platform_data = &veu1_platform_data, 531 }, 532 .resource = veu1_resources, 533 .num_resources = ARRAY_SIZE(veu1_resources), 534 .archdata = { 535 .hwblk_id = HWBLK_VEU1, 536 }, 537 }; 538 539 /* BEU0 */ 540 static struct uio_info beu0_platform_data = { 541 .name = "BEU0", 542 .version = "0", 543 .irq = evt2irq(0x8A0), 544 }; 545 546 static struct resource beu0_resources[] = { 547 [0] = { 548 .name = "BEU0", 549 .start = 0xfe930000, 550 .end = 0xfe933400, 551 .flags = IORESOURCE_MEM, 552 }, 553 [1] = { 554 /* place holder for contiguous memory */ 555 }, 556 }; 557 558 static struct platform_device beu0_device = { 559 .name = "uio_pdrv_genirq", 560 .id = 6, 561 .dev = { 562 .platform_data = &beu0_platform_data, 563 }, 564 .resource = beu0_resources, 565 .num_resources = ARRAY_SIZE(beu0_resources), 566 .archdata = { 567 .hwblk_id = HWBLK_BEU0, 568 }, 569 }; 570 571 /* BEU1 */ 572 static struct uio_info beu1_platform_data = { 573 .name = "BEU1", 574 .version = "0", 575 .irq = evt2irq(0xA00), 576 }; 577 578 static struct resource beu1_resources[] = { 579 [0] = { 580 .name = "BEU1", 581 .start = 0xfe940000, 582 .end = 0xfe943400, 583 .flags = IORESOURCE_MEM, 584 }, 585 [1] = { 586 /* place holder for contiguous memory */ 587 }, 588 }; 589 590 static struct platform_device beu1_device = { 591 .name = "uio_pdrv_genirq", 592 .id = 7, 593 .dev = { 594 .platform_data = &beu1_platform_data, 595 }, 596 .resource = beu1_resources, 597 .num_resources = ARRAY_SIZE(beu1_resources), 598 .archdata = { 599 .hwblk_id = HWBLK_BEU1, 600 }, 601 }; 602 603 static struct sh_timer_config cmt_platform_data = { 604 .channel_offset = 0x60, 605 .timer_bit = 5, 606 .clockevent_rating = 125, 607 .clocksource_rating = 200, 608 }; 609 610 static struct resource cmt_resources[] = { 611 [0] = { 612 .start = 0x044a0060, 613 .end = 0x044a006b, 614 .flags = IORESOURCE_MEM, 615 }, 616 [1] = { 617 .start = 104, 618 .flags = IORESOURCE_IRQ, 619 }, 620 }; 621 622 static struct platform_device cmt_device = { 623 .name = "sh_cmt", 624 .id = 0, 625 .dev = { 626 .platform_data = &cmt_platform_data, 627 }, 628 .resource = cmt_resources, 629 .num_resources = ARRAY_SIZE(cmt_resources), 630 .archdata = { 631 .hwblk_id = HWBLK_CMT, 632 }, 633 }; 634 635 static struct sh_timer_config tmu0_platform_data = { 636 .channel_offset = 0x04, 637 .timer_bit = 0, 638 .clockevent_rating = 200, 639 }; 640 641 static struct resource tmu0_resources[] = { 642 [0] = { 643 .start = 0xffd80008, 644 .end = 0xffd80013, 645 .flags = IORESOURCE_MEM, 646 }, 647 [1] = { 648 .start = 16, 649 .flags = IORESOURCE_IRQ, 650 }, 651 }; 652 653 static struct platform_device tmu0_device = { 654 .name = "sh_tmu", 655 .id = 0, 656 .dev = { 657 .platform_data = &tmu0_platform_data, 658 }, 659 .resource = tmu0_resources, 660 .num_resources = ARRAY_SIZE(tmu0_resources), 661 .archdata = { 662 .hwblk_id = HWBLK_TMU0, 663 }, 664 }; 665 666 static struct sh_timer_config tmu1_platform_data = { 667 .channel_offset = 0x10, 668 .timer_bit = 1, 669 .clocksource_rating = 200, 670 }; 671 672 static struct resource tmu1_resources[] = { 673 [0] = { 674 .start = 0xffd80014, 675 .end = 0xffd8001f, 676 .flags = IORESOURCE_MEM, 677 }, 678 [1] = { 679 .start = 17, 680 .flags = IORESOURCE_IRQ, 681 }, 682 }; 683 684 static struct platform_device tmu1_device = { 685 .name = "sh_tmu", 686 .id = 1, 687 .dev = { 688 .platform_data = &tmu1_platform_data, 689 }, 690 .resource = tmu1_resources, 691 .num_resources = ARRAY_SIZE(tmu1_resources), 692 .archdata = { 693 .hwblk_id = HWBLK_TMU0, 694 }, 695 }; 696 697 static struct sh_timer_config tmu2_platform_data = { 698 .channel_offset = 0x1c, 699 .timer_bit = 2, 700 }; 701 702 static struct resource tmu2_resources[] = { 703 [0] = { 704 .start = 0xffd80020, 705 .end = 0xffd8002b, 706 .flags = IORESOURCE_MEM, 707 }, 708 [1] = { 709 .start = 18, 710 .flags = IORESOURCE_IRQ, 711 }, 712 }; 713 714 static struct platform_device tmu2_device = { 715 .name = "sh_tmu", 716 .id = 2, 717 .dev = { 718 .platform_data = &tmu2_platform_data, 719 }, 720 .resource = tmu2_resources, 721 .num_resources = ARRAY_SIZE(tmu2_resources), 722 .archdata = { 723 .hwblk_id = HWBLK_TMU0, 724 }, 725 }; 726 727 728 static struct sh_timer_config tmu3_platform_data = { 729 .channel_offset = 0x04, 730 .timer_bit = 0, 731 }; 732 733 static struct resource tmu3_resources[] = { 734 [0] = { 735 .start = 0xffd90008, 736 .end = 0xffd90013, 737 .flags = IORESOURCE_MEM, 738 }, 739 [1] = { 740 .start = 57, 741 .flags = IORESOURCE_IRQ, 742 }, 743 }; 744 745 static struct platform_device tmu3_device = { 746 .name = "sh_tmu", 747 .id = 3, 748 .dev = { 749 .platform_data = &tmu3_platform_data, 750 }, 751 .resource = tmu3_resources, 752 .num_resources = ARRAY_SIZE(tmu3_resources), 753 .archdata = { 754 .hwblk_id = HWBLK_TMU1, 755 }, 756 }; 757 758 static struct sh_timer_config tmu4_platform_data = { 759 .channel_offset = 0x10, 760 .timer_bit = 1, 761 }; 762 763 static struct resource tmu4_resources[] = { 764 [0] = { 765 .start = 0xffd90014, 766 .end = 0xffd9001f, 767 .flags = IORESOURCE_MEM, 768 }, 769 [1] = { 770 .start = 58, 771 .flags = IORESOURCE_IRQ, 772 }, 773 }; 774 775 static struct platform_device tmu4_device = { 776 .name = "sh_tmu", 777 .id = 4, 778 .dev = { 779 .platform_data = &tmu4_platform_data, 780 }, 781 .resource = tmu4_resources, 782 .num_resources = ARRAY_SIZE(tmu4_resources), 783 .archdata = { 784 .hwblk_id = HWBLK_TMU1, 785 }, 786 }; 787 788 static struct sh_timer_config tmu5_platform_data = { 789 .channel_offset = 0x1c, 790 .timer_bit = 2, 791 }; 792 793 static struct resource tmu5_resources[] = { 794 [0] = { 795 .start = 0xffd90020, 796 .end = 0xffd9002b, 797 .flags = IORESOURCE_MEM, 798 }, 799 [1] = { 800 .start = 57, 801 .flags = IORESOURCE_IRQ, 802 }, 803 }; 804 805 static struct platform_device tmu5_device = { 806 .name = "sh_tmu", 807 .id = 5, 808 .dev = { 809 .platform_data = &tmu5_platform_data, 810 }, 811 .resource = tmu5_resources, 812 .num_resources = ARRAY_SIZE(tmu5_resources), 813 .archdata = { 814 .hwblk_id = HWBLK_TMU1, 815 }, 816 }; 817 818 /* JPU */ 819 static struct uio_info jpu_platform_data = { 820 .name = "JPU", 821 .version = "0", 822 .irq = 27, 823 }; 824 825 static struct resource jpu_resources[] = { 826 [0] = { 827 .name = "JPU", 828 .start = 0xfe980000, 829 .end = 0xfe9902d3, 830 .flags = IORESOURCE_MEM, 831 }, 832 [1] = { 833 /* place holder for contiguous memory */ 834 }, 835 }; 836 837 static struct platform_device jpu_device = { 838 .name = "uio_pdrv_genirq", 839 .id = 3, 840 .dev = { 841 .platform_data = &jpu_platform_data, 842 }, 843 .resource = jpu_resources, 844 .num_resources = ARRAY_SIZE(jpu_resources), 845 .archdata = { 846 .hwblk_id = HWBLK_JPU, 847 }, 848 }; 849 850 /* SPU2DSP0 */ 851 static struct uio_info spu0_platform_data = { 852 .name = "SPU2DSP0", 853 .version = "0", 854 .irq = 86, 855 }; 856 857 static struct resource spu0_resources[] = { 858 [0] = { 859 .name = "SPU2DSP0", 860 .start = 0xFE200000, 861 .end = 0xFE2FFFFF, 862 .flags = IORESOURCE_MEM, 863 }, 864 [1] = { 865 /* place holder for contiguous memory */ 866 }, 867 }; 868 869 static struct platform_device spu0_device = { 870 .name = "uio_pdrv_genirq", 871 .id = 4, 872 .dev = { 873 .platform_data = &spu0_platform_data, 874 }, 875 .resource = spu0_resources, 876 .num_resources = ARRAY_SIZE(spu0_resources), 877 .archdata = { 878 .hwblk_id = HWBLK_SPU, 879 }, 880 }; 881 882 /* SPU2DSP1 */ 883 static struct uio_info spu1_platform_data = { 884 .name = "SPU2DSP1", 885 .version = "0", 886 .irq = 87, 887 }; 888 889 static struct resource spu1_resources[] = { 890 [0] = { 891 .name = "SPU2DSP1", 892 .start = 0xFE300000, 893 .end = 0xFE3FFFFF, 894 .flags = IORESOURCE_MEM, 895 }, 896 [1] = { 897 /* place holder for contiguous memory */ 898 }, 899 }; 900 901 static struct platform_device spu1_device = { 902 .name = "uio_pdrv_genirq", 903 .id = 5, 904 .dev = { 905 .platform_data = &spu1_platform_data, 906 }, 907 .resource = spu1_resources, 908 .num_resources = ARRAY_SIZE(spu1_resources), 909 .archdata = { 910 .hwblk_id = HWBLK_SPU, 911 }, 912 }; 913 914 static struct platform_device *sh7724_devices[] __initdata = { 915 &scif0_device, 916 &scif1_device, 917 &scif2_device, 918 &scif3_device, 919 &scif4_device, 920 &scif5_device, 921 &cmt_device, 922 &tmu0_device, 923 &tmu1_device, 924 &tmu2_device, 925 &tmu3_device, 926 &tmu4_device, 927 &tmu5_device, 928 &dma0_device, 929 &dma1_device, 930 &rtc_device, 931 &iic0_device, 932 &iic1_device, 933 &vpu_device, 934 &veu0_device, 935 &veu1_device, 936 &beu0_device, 937 &beu1_device, 938 &jpu_device, 939 &spu0_device, 940 &spu1_device, 941 }; 942 943 static int __init sh7724_devices_setup(void) 944 { 945 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 946 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 947 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 948 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); 949 platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20); 950 platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20); 951 952 return platform_add_devices(sh7724_devices, 953 ARRAY_SIZE(sh7724_devices)); 954 } 955 arch_initcall(sh7724_devices_setup); 956 957 static struct platform_device *sh7724_early_devices[] __initdata = { 958 &scif0_device, 959 &scif1_device, 960 &scif2_device, 961 &scif3_device, 962 &scif4_device, 963 &scif5_device, 964 &cmt_device, 965 &tmu0_device, 966 &tmu1_device, 967 &tmu2_device, 968 &tmu3_device, 969 &tmu4_device, 970 &tmu5_device, 971 }; 972 973 void __init plat_early_device_setup(void) 974 { 975 early_platform_add_devices(sh7724_early_devices, 976 ARRAY_SIZE(sh7724_early_devices)); 977 } 978 979 #define RAMCR_CACHE_L2FC 0x0002 980 #define RAMCR_CACHE_L2E 0x0001 981 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) 982 983 void l2_cache_init(void) 984 { 985 /* Enable L2 cache */ 986 __raw_writel(L2_CACHE_ENABLE, RAMCR); 987 } 988 989 enum { 990 UNUSED = 0, 991 ENABLED, 992 DISABLED, 993 994 /* interrupt sources */ 995 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 996 HUDI, 997 DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3, 998 _2DG_TRI, _2DG_INI, _2DG_CEI, 999 DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3, 1000 VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU, 1001 SCIFA3, 1002 VPU, 1003 TPU, 1004 CEU1, 1005 BEU1, 1006 USB0, USB1, 1007 ATAPI, 1008 RTC_ATI, RTC_PRI, RTC_CUI, 1009 DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR, 1010 DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR, 1011 KEYSC, 1012 SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2, 1013 VEU0, 1014 MSIOF_MSIOFI0, MSIOF_MSIOFI1, 1015 SPU_SPUI0, SPU_SPUI1, 1016 SCIFA4, 1017 ICB, 1018 ETHI, 1019 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI, 1020 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, 1021 CMT, 1022 TSIF, 1023 FSI, 1024 SCIFA5, 1025 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, 1026 IRDA, 1027 JPU, 1028 _2DDMAC, 1029 MMC_MMC2I, MMC_MMC3I, 1030 LCDC, 1031 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 1032 1033 /* interrupt groups */ 1034 DMAC1A, _2DG, DMAC0A, VIO, USB, RTC, 1035 DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF, 1036 }; 1037 1038 static struct intc_vect vectors[] __initdata = { 1039 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 1040 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 1041 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 1042 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 1043 1044 INTC_VECT(DMAC1A_DEI0, 0x700), 1045 INTC_VECT(DMAC1A_DEI1, 0x720), 1046 INTC_VECT(DMAC1A_DEI2, 0x740), 1047 INTC_VECT(DMAC1A_DEI3, 0x760), 1048 1049 INTC_VECT(_2DG_TRI, 0x780), 1050 INTC_VECT(_2DG_INI, 0x7A0), 1051 INTC_VECT(_2DG_CEI, 0x7C0), 1052 1053 INTC_VECT(DMAC0A_DEI0, 0x800), 1054 INTC_VECT(DMAC0A_DEI1, 0x820), 1055 INTC_VECT(DMAC0A_DEI2, 0x840), 1056 INTC_VECT(DMAC0A_DEI3, 0x860), 1057 1058 INTC_VECT(VIO_CEU0, 0x880), 1059 INTC_VECT(VIO_BEU0, 0x8A0), 1060 INTC_VECT(VIO_VEU1, 0x8C0), 1061 INTC_VECT(VIO_VOU, 0x8E0), 1062 1063 INTC_VECT(SCIFA3, 0x900), 1064 INTC_VECT(VPU, 0x980), 1065 INTC_VECT(TPU, 0x9A0), 1066 INTC_VECT(CEU1, 0x9E0), 1067 INTC_VECT(BEU1, 0xA00), 1068 INTC_VECT(USB0, 0xA20), 1069 INTC_VECT(USB1, 0xA40), 1070 INTC_VECT(ATAPI, 0xA60), 1071 1072 INTC_VECT(RTC_ATI, 0xA80), 1073 INTC_VECT(RTC_PRI, 0xAA0), 1074 INTC_VECT(RTC_CUI, 0xAC0), 1075 1076 INTC_VECT(DMAC1B_DEI4, 0xB00), 1077 INTC_VECT(DMAC1B_DEI5, 0xB20), 1078 INTC_VECT(DMAC1B_DADERR, 0xB40), 1079 1080 INTC_VECT(DMAC0B_DEI4, 0xB80), 1081 INTC_VECT(DMAC0B_DEI5, 0xBA0), 1082 INTC_VECT(DMAC0B_DADERR, 0xBC0), 1083 1084 INTC_VECT(KEYSC, 0xBE0), 1085 INTC_VECT(SCIF_SCIF0, 0xC00), 1086 INTC_VECT(SCIF_SCIF1, 0xC20), 1087 INTC_VECT(SCIF_SCIF2, 0xC40), 1088 INTC_VECT(VEU0, 0xC60), 1089 INTC_VECT(MSIOF_MSIOFI0, 0xC80), 1090 INTC_VECT(MSIOF_MSIOFI1, 0xCA0), 1091 INTC_VECT(SPU_SPUI0, 0xCC0), 1092 INTC_VECT(SPU_SPUI1, 0xCE0), 1093 INTC_VECT(SCIFA4, 0xD00), 1094 1095 INTC_VECT(ICB, 0xD20), 1096 INTC_VECT(ETHI, 0xD60), 1097 1098 INTC_VECT(I2C1_ALI, 0xD80), 1099 INTC_VECT(I2C1_TACKI, 0xDA0), 1100 INTC_VECT(I2C1_WAITI, 0xDC0), 1101 INTC_VECT(I2C1_DTEI, 0xDE0), 1102 1103 INTC_VECT(I2C0_ALI, 0xE00), 1104 INTC_VECT(I2C0_TACKI, 0xE20), 1105 INTC_VECT(I2C0_WAITI, 0xE40), 1106 INTC_VECT(I2C0_DTEI, 0xE60), 1107 1108 INTC_VECT(SDHI0, 0xE80), 1109 INTC_VECT(SDHI0, 0xEA0), 1110 INTC_VECT(SDHI0, 0xEC0), 1111 INTC_VECT(SDHI0, 0xEE0), 1112 1113 INTC_VECT(CMT, 0xF00), 1114 INTC_VECT(TSIF, 0xF20), 1115 INTC_VECT(FSI, 0xF80), 1116 INTC_VECT(SCIFA5, 0xFA0), 1117 1118 INTC_VECT(TMU0_TUNI0, 0x400), 1119 INTC_VECT(TMU0_TUNI1, 0x420), 1120 INTC_VECT(TMU0_TUNI2, 0x440), 1121 1122 INTC_VECT(IRDA, 0x480), 1123 1124 INTC_VECT(SDHI1, 0x4E0), 1125 INTC_VECT(SDHI1, 0x500), 1126 INTC_VECT(SDHI1, 0x520), 1127 1128 INTC_VECT(JPU, 0x560), 1129 INTC_VECT(_2DDMAC, 0x4A0), 1130 1131 INTC_VECT(MMC_MMC2I, 0x5A0), 1132 INTC_VECT(MMC_MMC3I, 0x5C0), 1133 1134 INTC_VECT(LCDC, 0xF40), 1135 1136 INTC_VECT(TMU1_TUNI0, 0x920), 1137 INTC_VECT(TMU1_TUNI1, 0x940), 1138 INTC_VECT(TMU1_TUNI2, 0x960), 1139 }; 1140 1141 static struct intc_group groups[] __initdata = { 1142 INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3), 1143 INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI), 1144 INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3), 1145 INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU), 1146 INTC_GROUP(USB, USB0, USB1), 1147 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 1148 INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR), 1149 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR), 1150 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI), 1151 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI), 1152 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1), 1153 INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I), 1154 }; 1155 1156 static struct intc_mask_reg mask_registers[] __initdata = { 1157 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 1158 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, 1159 0, ENABLED, ENABLED, ENABLED } }, 1160 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 1161 { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0, 1162 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } }, 1163 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 1164 { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } }, 1165 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 1166 { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0, 1167 SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } }, 1168 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 1169 { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0, 1170 JPU, 0, 0, LCDC } }, 1171 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 1172 { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4, 1173 VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } }, 1174 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 1175 { 0, 0, ICB, SCIFA4, 1176 CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } }, 1177 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 1178 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, 1179 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } }, 1180 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 1181 { DISABLED, ENABLED, ENABLED, ENABLED, 1182 0, 0, SCIFA5, FSI } }, 1183 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 1184 { 0, 0, 0, CMT, 0, USB1, USB0, 0 } }, 1185 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 1186 { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4, 1187 0, RTC_CUI, RTC_PRI, RTC_ATI } }, 1188 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 1189 { 0, _2DG_CEI, _2DG_INI, _2DG_TRI, 1190 0, TPU, 0, TSIF } }, 1191 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */ 1192 { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } }, 1193 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 1194 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1195 }; 1196 1197 static struct intc_prio_reg prio_registers[] __initdata = { 1198 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, 1199 TMU0_TUNI2, IRDA } }, 1200 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } }, 1201 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, 1202 TMU1_TUNI2, SPU } }, 1203 { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } }, 1204 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } }, 1205 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } }, 1206 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, 1207 SCIF_SCIF2, VEU0 } }, 1208 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1, 1209 I2C1, I2C0 } }, 1210 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } }, 1211 { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } }, 1212 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } }, 1213 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } }, 1214 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 1215 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1216 }; 1217 1218 static struct intc_sense_reg sense_registers[] __initdata = { 1219 { 0xa414001c, 16, 2, /* ICR1 */ 1220 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1221 }; 1222 1223 static struct intc_mask_reg ack_registers[] __initdata = { 1224 { 0xa4140024, 0, 8, /* INTREQ00 */ 1225 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1226 }; 1227 1228 static struct intc_desc intc_desc __initdata = { 1229 .name = "sh7724", 1230 .force_enable = ENABLED, 1231 .force_disable = DISABLED, 1232 .hw = INTC_HW_DESC(vectors, groups, mask_registers, 1233 prio_registers, sense_registers, ack_registers), 1234 }; 1235 1236 void __init plat_irq_setup(void) 1237 { 1238 register_intc_controller(&intc_desc); 1239 } 1240 1241 static struct { 1242 /* BSC */ 1243 unsigned long mmselr; 1244 unsigned long cs0bcr; 1245 unsigned long cs4bcr; 1246 unsigned long cs5abcr; 1247 unsigned long cs5bbcr; 1248 unsigned long cs6abcr; 1249 unsigned long cs6bbcr; 1250 unsigned long cs4wcr; 1251 unsigned long cs5awcr; 1252 unsigned long cs5bwcr; 1253 unsigned long cs6awcr; 1254 unsigned long cs6bwcr; 1255 /* INTC */ 1256 unsigned short ipra; 1257 unsigned short iprb; 1258 unsigned short iprc; 1259 unsigned short iprd; 1260 unsigned short ipre; 1261 unsigned short iprf; 1262 unsigned short iprg; 1263 unsigned short iprh; 1264 unsigned short ipri; 1265 unsigned short iprj; 1266 unsigned short iprk; 1267 unsigned short iprl; 1268 unsigned char imr0; 1269 unsigned char imr1; 1270 unsigned char imr2; 1271 unsigned char imr3; 1272 unsigned char imr4; 1273 unsigned char imr5; 1274 unsigned char imr6; 1275 unsigned char imr7; 1276 unsigned char imr8; 1277 unsigned char imr9; 1278 unsigned char imr10; 1279 unsigned char imr11; 1280 unsigned char imr12; 1281 /* RWDT */ 1282 unsigned short rwtcnt; 1283 unsigned short rwtcsr; 1284 /* CPG */ 1285 unsigned long irdaclk; 1286 unsigned long spuclk; 1287 } sh7724_rstandby_state; 1288 1289 static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb, 1290 unsigned long flags, void *unused) 1291 { 1292 if (!(flags & SUSP_SH_RSTANDBY)) 1293 return NOTIFY_DONE; 1294 1295 /* BCR */ 1296 sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */ 1297 sh7724_rstandby_state.mmselr |= 0xa5a50000; 1298 sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */ 1299 sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */ 1300 sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */ 1301 sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */ 1302 sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */ 1303 sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */ 1304 sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */ 1305 sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */ 1306 sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */ 1307 sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */ 1308 sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */ 1309 1310 /* INTC */ 1311 sh7724_rstandby_state.ipra = __raw_readw(0xa4080000); /* IPRA */ 1312 sh7724_rstandby_state.iprb = __raw_readw(0xa4080004); /* IPRB */ 1313 sh7724_rstandby_state.iprc = __raw_readw(0xa4080008); /* IPRC */ 1314 sh7724_rstandby_state.iprd = __raw_readw(0xa408000c); /* IPRD */ 1315 sh7724_rstandby_state.ipre = __raw_readw(0xa4080010); /* IPRE */ 1316 sh7724_rstandby_state.iprf = __raw_readw(0xa4080014); /* IPRF */ 1317 sh7724_rstandby_state.iprg = __raw_readw(0xa4080018); /* IPRG */ 1318 sh7724_rstandby_state.iprh = __raw_readw(0xa408001c); /* IPRH */ 1319 sh7724_rstandby_state.ipri = __raw_readw(0xa4080020); /* IPRI */ 1320 sh7724_rstandby_state.iprj = __raw_readw(0xa4080024); /* IPRJ */ 1321 sh7724_rstandby_state.iprk = __raw_readw(0xa4080028); /* IPRK */ 1322 sh7724_rstandby_state.iprl = __raw_readw(0xa408002c); /* IPRL */ 1323 sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */ 1324 sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */ 1325 sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */ 1326 sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */ 1327 sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */ 1328 sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */ 1329 sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */ 1330 sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */ 1331 sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */ 1332 sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */ 1333 sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */ 1334 sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */ 1335 sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */ 1336 1337 /* RWDT */ 1338 sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */ 1339 sh7724_rstandby_state.rwtcnt |= 0x5a00; 1340 sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */ 1341 sh7724_rstandby_state.rwtcsr |= 0xa500; 1342 __raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004); 1343 1344 /* CPG */ 1345 sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */ 1346 sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */ 1347 1348 return NOTIFY_DONE; 1349 } 1350 1351 static int sh7724_post_sleep_notifier_call(struct notifier_block *nb, 1352 unsigned long flags, void *unused) 1353 { 1354 if (!(flags & SUSP_SH_RSTANDBY)) 1355 return NOTIFY_DONE; 1356 1357 /* BCR */ 1358 __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */ 1359 __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */ 1360 __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */ 1361 __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */ 1362 __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */ 1363 __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */ 1364 __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */ 1365 __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */ 1366 __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */ 1367 __raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */ 1368 __raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */ 1369 __raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */ 1370 1371 /* INTC */ 1372 __raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */ 1373 __raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */ 1374 __raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */ 1375 __raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */ 1376 __raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */ 1377 __raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */ 1378 __raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */ 1379 __raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */ 1380 __raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */ 1381 __raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */ 1382 __raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */ 1383 __raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */ 1384 __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */ 1385 __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */ 1386 __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */ 1387 __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */ 1388 __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */ 1389 __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */ 1390 __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */ 1391 __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */ 1392 __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */ 1393 __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */ 1394 __raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8); /* IMR10 */ 1395 __raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac); /* IMR11 */ 1396 __raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0); /* IMR12 */ 1397 1398 /* RWDT */ 1399 __raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */ 1400 __raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */ 1401 1402 /* CPG */ 1403 __raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018); /* IRDACLKCR */ 1404 __raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c); /* SPUCLKCR */ 1405 1406 return NOTIFY_DONE; 1407 } 1408 1409 static struct notifier_block sh7724_pre_sleep_notifier = { 1410 .notifier_call = sh7724_pre_sleep_notifier_call, 1411 .priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU), 1412 }; 1413 1414 static struct notifier_block sh7724_post_sleep_notifier = { 1415 .notifier_call = sh7724_post_sleep_notifier_call, 1416 .priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU), 1417 }; 1418 1419 static int __init sh7724_sleep_setup(void) 1420 { 1421 atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list, 1422 &sh7724_pre_sleep_notifier); 1423 1424 atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list, 1425 &sh7724_post_sleep_notifier); 1426 return 0; 1427 } 1428 arch_initcall(sh7724_sleep_setup); 1429 1430