1 /* 2 * SH7724 Setup 3 * 4 * Copyright (C) 2009 Renesas Solutions Corp. 5 * 6 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 7 * 8 * Based on SH7723 Setup 9 * Copyright (C) 2008 Paul Mundt 10 * 11 * This file is subject to the terms and conditions of the GNU General Public 12 * License. See the file "COPYING" in the main directory of this archive 13 * for more details. 14 */ 15 #include <linux/platform_device.h> 16 #include <linux/init.h> 17 #include <linux/serial.h> 18 #include <linux/mm.h> 19 #include <linux/serial_sci.h> 20 #include <linux/uio_driver.h> 21 #include <linux/sh_dma.h> 22 #include <linux/sh_timer.h> 23 #include <linux/sh_intc.h> 24 #include <linux/io.h> 25 #include <linux/notifier.h> 26 27 #include <asm/suspend.h> 28 #include <asm/clock.h> 29 #include <asm/mmzone.h> 30 31 #include <cpu/dma-register.h> 32 #include <cpu/sh7724.h> 33 34 /* DMA */ 35 static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = { 36 { 37 .slave_id = SHDMA_SLAVE_SCIF0_TX, 38 .addr = 0xffe0000c, 39 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 40 .mid_rid = 0x21, 41 }, { 42 .slave_id = SHDMA_SLAVE_SCIF0_RX, 43 .addr = 0xffe00014, 44 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 45 .mid_rid = 0x22, 46 }, { 47 .slave_id = SHDMA_SLAVE_SCIF1_TX, 48 .addr = 0xffe1000c, 49 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 50 .mid_rid = 0x25, 51 }, { 52 .slave_id = SHDMA_SLAVE_SCIF1_RX, 53 .addr = 0xffe10014, 54 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 55 .mid_rid = 0x26, 56 }, { 57 .slave_id = SHDMA_SLAVE_SCIF2_TX, 58 .addr = 0xffe2000c, 59 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 60 .mid_rid = 0x29, 61 }, { 62 .slave_id = SHDMA_SLAVE_SCIF2_RX, 63 .addr = 0xffe20014, 64 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 65 .mid_rid = 0x2a, 66 }, { 67 .slave_id = SHDMA_SLAVE_SCIF3_TX, 68 .addr = 0xa4e30020, 69 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 70 .mid_rid = 0x2d, 71 }, { 72 .slave_id = SHDMA_SLAVE_SCIF3_RX, 73 .addr = 0xa4e30024, 74 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 75 .mid_rid = 0x2e, 76 }, { 77 .slave_id = SHDMA_SLAVE_SCIF4_TX, 78 .addr = 0xa4e40020, 79 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 80 .mid_rid = 0x31, 81 }, { 82 .slave_id = SHDMA_SLAVE_SCIF4_RX, 83 .addr = 0xa4e40024, 84 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 85 .mid_rid = 0x32, 86 }, { 87 .slave_id = SHDMA_SLAVE_SCIF5_TX, 88 .addr = 0xa4e50020, 89 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 90 .mid_rid = 0x35, 91 }, { 92 .slave_id = SHDMA_SLAVE_SCIF5_RX, 93 .addr = 0xa4e50024, 94 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 95 .mid_rid = 0x36, 96 }, { 97 .slave_id = SHDMA_SLAVE_USB0D0_TX, 98 .addr = 0xA4D80100, 99 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 100 .mid_rid = 0x73, 101 }, { 102 .slave_id = SHDMA_SLAVE_USB0D0_RX, 103 .addr = 0xA4D80100, 104 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 105 .mid_rid = 0x73, 106 }, { 107 .slave_id = SHDMA_SLAVE_USB0D1_TX, 108 .addr = 0xA4D80120, 109 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 110 .mid_rid = 0x77, 111 }, { 112 .slave_id = SHDMA_SLAVE_USB0D1_RX, 113 .addr = 0xA4D80120, 114 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 115 .mid_rid = 0x77, 116 }, { 117 .slave_id = SHDMA_SLAVE_USB1D0_TX, 118 .addr = 0xA4D90100, 119 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 120 .mid_rid = 0xab, 121 }, { 122 .slave_id = SHDMA_SLAVE_USB1D0_RX, 123 .addr = 0xA4D90100, 124 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 125 .mid_rid = 0xab, 126 }, { 127 .slave_id = SHDMA_SLAVE_USB1D1_TX, 128 .addr = 0xA4D90120, 129 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 130 .mid_rid = 0xaf, 131 }, { 132 .slave_id = SHDMA_SLAVE_USB1D1_RX, 133 .addr = 0xA4D90120, 134 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 135 .mid_rid = 0xaf, 136 }, { 137 .slave_id = SHDMA_SLAVE_SDHI0_TX, 138 .addr = 0x04ce0030, 139 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT), 140 .mid_rid = 0xc1, 141 }, { 142 .slave_id = SHDMA_SLAVE_SDHI0_RX, 143 .addr = 0x04ce0030, 144 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT), 145 .mid_rid = 0xc2, 146 }, { 147 .slave_id = SHDMA_SLAVE_SDHI1_TX, 148 .addr = 0x04cf0030, 149 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT), 150 .mid_rid = 0xc9, 151 }, { 152 .slave_id = SHDMA_SLAVE_SDHI1_RX, 153 .addr = 0x04cf0030, 154 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT), 155 .mid_rid = 0xca, 156 }, 157 }; 158 159 static const struct sh_dmae_channel sh7724_dmae_channels[] = { 160 { 161 .offset = 0, 162 .dmars = 0, 163 .dmars_bit = 0, 164 }, { 165 .offset = 0x10, 166 .dmars = 0, 167 .dmars_bit = 8, 168 }, { 169 .offset = 0x20, 170 .dmars = 4, 171 .dmars_bit = 0, 172 }, { 173 .offset = 0x30, 174 .dmars = 4, 175 .dmars_bit = 8, 176 }, { 177 .offset = 0x50, 178 .dmars = 8, 179 .dmars_bit = 0, 180 }, { 181 .offset = 0x60, 182 .dmars = 8, 183 .dmars_bit = 8, 184 } 185 }; 186 187 static const unsigned int ts_shift[] = TS_SHIFT; 188 189 static struct sh_dmae_pdata dma_platform_data = { 190 .slave = sh7724_dmae_slaves, 191 .slave_num = ARRAY_SIZE(sh7724_dmae_slaves), 192 .channel = sh7724_dmae_channels, 193 .channel_num = ARRAY_SIZE(sh7724_dmae_channels), 194 .ts_low_shift = CHCR_TS_LOW_SHIFT, 195 .ts_low_mask = CHCR_TS_LOW_MASK, 196 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 197 .ts_high_mask = CHCR_TS_HIGH_MASK, 198 .ts_shift = ts_shift, 199 .ts_shift_num = ARRAY_SIZE(ts_shift), 200 .dmaor_init = DMAOR_INIT, 201 }; 202 203 /* Resource order important! */ 204 static struct resource sh7724_dmae0_resources[] = { 205 { 206 /* Channel registers and DMAOR */ 207 .start = 0xfe008020, 208 .end = 0xfe00808f, 209 .flags = IORESOURCE_MEM, 210 }, 211 { 212 /* DMARSx */ 213 .start = 0xfe009000, 214 .end = 0xfe00900b, 215 .flags = IORESOURCE_MEM, 216 }, 217 { 218 .name = "error_irq", 219 .start = evt2irq(0xbc0), 220 .end = evt2irq(0xbc0), 221 .flags = IORESOURCE_IRQ, 222 }, 223 { 224 /* IRQ for channels 0-3 */ 225 .start = evt2irq(0x800), 226 .end = evt2irq(0x860), 227 .flags = IORESOURCE_IRQ, 228 }, 229 { 230 /* IRQ for channels 4-5 */ 231 .start = evt2irq(0xb80), 232 .end = evt2irq(0xba0), 233 .flags = IORESOURCE_IRQ, 234 }, 235 }; 236 237 /* Resource order important! */ 238 static struct resource sh7724_dmae1_resources[] = { 239 { 240 /* Channel registers and DMAOR */ 241 .start = 0xfdc08020, 242 .end = 0xfdc0808f, 243 .flags = IORESOURCE_MEM, 244 }, 245 { 246 /* DMARSx */ 247 .start = 0xfdc09000, 248 .end = 0xfdc0900b, 249 .flags = IORESOURCE_MEM, 250 }, 251 { 252 .name = "error_irq", 253 .start = evt2irq(0xb40), 254 .end = evt2irq(0xb40), 255 .flags = IORESOURCE_IRQ, 256 }, 257 { 258 /* IRQ for channels 0-3 */ 259 .start = evt2irq(0x700), 260 .end = evt2irq(0x760), 261 .flags = IORESOURCE_IRQ, 262 }, 263 { 264 /* IRQ for channels 4-5 */ 265 .start = evt2irq(0xb00), 266 .end = evt2irq(0xb20), 267 .flags = IORESOURCE_IRQ, 268 }, 269 }; 270 271 static struct platform_device dma0_device = { 272 .name = "sh-dma-engine", 273 .id = 0, 274 .resource = sh7724_dmae0_resources, 275 .num_resources = ARRAY_SIZE(sh7724_dmae0_resources), 276 .dev = { 277 .platform_data = &dma_platform_data, 278 }, 279 }; 280 281 static struct platform_device dma1_device = { 282 .name = "sh-dma-engine", 283 .id = 1, 284 .resource = sh7724_dmae1_resources, 285 .num_resources = ARRAY_SIZE(sh7724_dmae1_resources), 286 .dev = { 287 .platform_data = &dma_platform_data, 288 }, 289 }; 290 291 /* Serial */ 292 static struct plat_sci_port scif0_platform_data = { 293 .scscr = SCSCR_REIE, 294 .type = PORT_SCIF, 295 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 296 }; 297 298 static struct resource scif0_resources[] = { 299 DEFINE_RES_MEM(0xffe00000, 0x100), 300 DEFINE_RES_IRQ(evt2irq(0xc00)), 301 }; 302 303 static struct platform_device scif0_device = { 304 .name = "sh-sci", 305 .id = 0, 306 .resource = scif0_resources, 307 .num_resources = ARRAY_SIZE(scif0_resources), 308 .dev = { 309 .platform_data = &scif0_platform_data, 310 }, 311 }; 312 313 static struct plat_sci_port scif1_platform_data = { 314 .scscr = SCSCR_REIE, 315 .type = PORT_SCIF, 316 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 317 }; 318 319 static struct resource scif1_resources[] = { 320 DEFINE_RES_MEM(0xffe10000, 0x100), 321 DEFINE_RES_IRQ(evt2irq(0xc20)), 322 }; 323 324 static struct platform_device scif1_device = { 325 .name = "sh-sci", 326 .id = 1, 327 .resource = scif1_resources, 328 .num_resources = ARRAY_SIZE(scif1_resources), 329 .dev = { 330 .platform_data = &scif1_platform_data, 331 }, 332 }; 333 334 static struct plat_sci_port scif2_platform_data = { 335 .scscr = SCSCR_REIE, 336 .type = PORT_SCIF, 337 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 338 }; 339 340 static struct resource scif2_resources[] = { 341 DEFINE_RES_MEM(0xffe20000, 0x100), 342 DEFINE_RES_IRQ(evt2irq(0xc40)), 343 }; 344 345 static struct platform_device scif2_device = { 346 .name = "sh-sci", 347 .id = 2, 348 .resource = scif2_resources, 349 .num_resources = ARRAY_SIZE(scif2_resources), 350 .dev = { 351 .platform_data = &scif2_platform_data, 352 }, 353 }; 354 355 static struct plat_sci_port scif3_platform_data = { 356 .sampling_rate = 8, 357 .type = PORT_SCIFA, 358 }; 359 360 static struct resource scif3_resources[] = { 361 DEFINE_RES_MEM(0xa4e30000, 0x100), 362 DEFINE_RES_IRQ(evt2irq(0x900)), 363 }; 364 365 static struct platform_device scif3_device = { 366 .name = "sh-sci", 367 .id = 3, 368 .resource = scif3_resources, 369 .num_resources = ARRAY_SIZE(scif3_resources), 370 .dev = { 371 .platform_data = &scif3_platform_data, 372 }, 373 }; 374 375 static struct plat_sci_port scif4_platform_data = { 376 .sampling_rate = 8, 377 .type = PORT_SCIFA, 378 }; 379 380 static struct resource scif4_resources[] = { 381 DEFINE_RES_MEM(0xa4e40000, 0x100), 382 DEFINE_RES_IRQ(evt2irq(0xd00)), 383 }; 384 385 static struct platform_device scif4_device = { 386 .name = "sh-sci", 387 .id = 4, 388 .resource = scif4_resources, 389 .num_resources = ARRAY_SIZE(scif4_resources), 390 .dev = { 391 .platform_data = &scif4_platform_data, 392 }, 393 }; 394 395 static struct plat_sci_port scif5_platform_data = { 396 .sampling_rate = 8, 397 .type = PORT_SCIFA, 398 }; 399 400 static struct resource scif5_resources[] = { 401 DEFINE_RES_MEM(0xa4e50000, 0x100), 402 DEFINE_RES_IRQ(evt2irq(0xfa0)), 403 }; 404 405 static struct platform_device scif5_device = { 406 .name = "sh-sci", 407 .id = 5, 408 .resource = scif5_resources, 409 .num_resources = ARRAY_SIZE(scif5_resources), 410 .dev = { 411 .platform_data = &scif5_platform_data, 412 }, 413 }; 414 415 /* RTC */ 416 static struct resource rtc_resources[] = { 417 [0] = { 418 .start = 0xa465fec0, 419 .end = 0xa465fec0 + 0x58 - 1, 420 .flags = IORESOURCE_IO, 421 }, 422 [1] = { 423 /* Period IRQ */ 424 .start = evt2irq(0xaa0), 425 .flags = IORESOURCE_IRQ, 426 }, 427 [2] = { 428 /* Carry IRQ */ 429 .start = evt2irq(0xac0), 430 .flags = IORESOURCE_IRQ, 431 }, 432 [3] = { 433 /* Alarm IRQ */ 434 .start = evt2irq(0xa80), 435 .flags = IORESOURCE_IRQ, 436 }, 437 }; 438 439 static struct platform_device rtc_device = { 440 .name = "sh-rtc", 441 .id = -1, 442 .num_resources = ARRAY_SIZE(rtc_resources), 443 .resource = rtc_resources, 444 }; 445 446 /* I2C0 */ 447 static struct resource iic0_resources[] = { 448 [0] = { 449 .name = "IIC0", 450 .start = 0x04470000, 451 .end = 0x04470018 - 1, 452 .flags = IORESOURCE_MEM, 453 }, 454 [1] = { 455 .start = evt2irq(0xe00), 456 .end = evt2irq(0xe60), 457 .flags = IORESOURCE_IRQ, 458 }, 459 }; 460 461 static struct platform_device iic0_device = { 462 .name = "i2c-sh_mobile", 463 .id = 0, /* "i2c0" clock */ 464 .num_resources = ARRAY_SIZE(iic0_resources), 465 .resource = iic0_resources, 466 }; 467 468 /* I2C1 */ 469 static struct resource iic1_resources[] = { 470 [0] = { 471 .name = "IIC1", 472 .start = 0x04750000, 473 .end = 0x04750018 - 1, 474 .flags = IORESOURCE_MEM, 475 }, 476 [1] = { 477 .start = evt2irq(0xd80), 478 .end = evt2irq(0xde0), 479 .flags = IORESOURCE_IRQ, 480 }, 481 }; 482 483 static struct platform_device iic1_device = { 484 .name = "i2c-sh_mobile", 485 .id = 1, /* "i2c1" clock */ 486 .num_resources = ARRAY_SIZE(iic1_resources), 487 .resource = iic1_resources, 488 }; 489 490 /* VPU */ 491 static struct uio_info vpu_platform_data = { 492 .name = "VPU5F", 493 .version = "0", 494 .irq = evt2irq(0x980), 495 }; 496 497 static struct resource vpu_resources[] = { 498 [0] = { 499 .name = "VPU", 500 .start = 0xfe900000, 501 .end = 0xfe902807, 502 .flags = IORESOURCE_MEM, 503 }, 504 [1] = { 505 /* place holder for contiguous memory */ 506 }, 507 }; 508 509 static struct platform_device vpu_device = { 510 .name = "uio_pdrv_genirq", 511 .id = 0, 512 .dev = { 513 .platform_data = &vpu_platform_data, 514 }, 515 .resource = vpu_resources, 516 .num_resources = ARRAY_SIZE(vpu_resources), 517 }; 518 519 /* VEU0 */ 520 static struct uio_info veu0_platform_data = { 521 .name = "VEU3F0", 522 .version = "0", 523 .irq = evt2irq(0xc60), 524 }; 525 526 static struct resource veu0_resources[] = { 527 [0] = { 528 .name = "VEU3F0", 529 .start = 0xfe920000, 530 .end = 0xfe9200cb, 531 .flags = IORESOURCE_MEM, 532 }, 533 [1] = { 534 /* place holder for contiguous memory */ 535 }, 536 }; 537 538 static struct platform_device veu0_device = { 539 .name = "uio_pdrv_genirq", 540 .id = 1, 541 .dev = { 542 .platform_data = &veu0_platform_data, 543 }, 544 .resource = veu0_resources, 545 .num_resources = ARRAY_SIZE(veu0_resources), 546 }; 547 548 /* VEU1 */ 549 static struct uio_info veu1_platform_data = { 550 .name = "VEU3F1", 551 .version = "0", 552 .irq = evt2irq(0x8c0), 553 }; 554 555 static struct resource veu1_resources[] = { 556 [0] = { 557 .name = "VEU3F1", 558 .start = 0xfe924000, 559 .end = 0xfe9240cb, 560 .flags = IORESOURCE_MEM, 561 }, 562 [1] = { 563 /* place holder for contiguous memory */ 564 }, 565 }; 566 567 static struct platform_device veu1_device = { 568 .name = "uio_pdrv_genirq", 569 .id = 2, 570 .dev = { 571 .platform_data = &veu1_platform_data, 572 }, 573 .resource = veu1_resources, 574 .num_resources = ARRAY_SIZE(veu1_resources), 575 }; 576 577 /* BEU0 */ 578 static struct uio_info beu0_platform_data = { 579 .name = "BEU0", 580 .version = "0", 581 .irq = evt2irq(0x8A0), 582 }; 583 584 static struct resource beu0_resources[] = { 585 [0] = { 586 .name = "BEU0", 587 .start = 0xfe930000, 588 .end = 0xfe933400, 589 .flags = IORESOURCE_MEM, 590 }, 591 [1] = { 592 /* place holder for contiguous memory */ 593 }, 594 }; 595 596 static struct platform_device beu0_device = { 597 .name = "uio_pdrv_genirq", 598 .id = 6, 599 .dev = { 600 .platform_data = &beu0_platform_data, 601 }, 602 .resource = beu0_resources, 603 .num_resources = ARRAY_SIZE(beu0_resources), 604 }; 605 606 /* BEU1 */ 607 static struct uio_info beu1_platform_data = { 608 .name = "BEU1", 609 .version = "0", 610 .irq = evt2irq(0xA00), 611 }; 612 613 static struct resource beu1_resources[] = { 614 [0] = { 615 .name = "BEU1", 616 .start = 0xfe940000, 617 .end = 0xfe943400, 618 .flags = IORESOURCE_MEM, 619 }, 620 [1] = { 621 /* place holder for contiguous memory */ 622 }, 623 }; 624 625 static struct platform_device beu1_device = { 626 .name = "uio_pdrv_genirq", 627 .id = 7, 628 .dev = { 629 .platform_data = &beu1_platform_data, 630 }, 631 .resource = beu1_resources, 632 .num_resources = ARRAY_SIZE(beu1_resources), 633 }; 634 635 static struct sh_timer_config cmt_platform_data = { 636 .channels_mask = 0x20, 637 }; 638 639 static struct resource cmt_resources[] = { 640 DEFINE_RES_MEM(0x044a0000, 0x70), 641 DEFINE_RES_IRQ(evt2irq(0xf00)), 642 }; 643 644 static struct platform_device cmt_device = { 645 .name = "sh-cmt-32", 646 .id = 0, 647 .dev = { 648 .platform_data = &cmt_platform_data, 649 }, 650 .resource = cmt_resources, 651 .num_resources = ARRAY_SIZE(cmt_resources), 652 }; 653 654 static struct sh_timer_config tmu0_platform_data = { 655 .channels_mask = 7, 656 }; 657 658 static struct resource tmu0_resources[] = { 659 DEFINE_RES_MEM(0xffd80000, 0x2c), 660 DEFINE_RES_IRQ(evt2irq(0x400)), 661 DEFINE_RES_IRQ(evt2irq(0x420)), 662 DEFINE_RES_IRQ(evt2irq(0x440)), 663 }; 664 665 static struct platform_device tmu0_device = { 666 .name = "sh-tmu", 667 .id = 0, 668 .dev = { 669 .platform_data = &tmu0_platform_data, 670 }, 671 .resource = tmu0_resources, 672 .num_resources = ARRAY_SIZE(tmu0_resources), 673 }; 674 675 static struct sh_timer_config tmu1_platform_data = { 676 .channels_mask = 7, 677 }; 678 679 static struct resource tmu1_resources[] = { 680 DEFINE_RES_MEM(0xffd90000, 0x2c), 681 DEFINE_RES_IRQ(evt2irq(0x920)), 682 DEFINE_RES_IRQ(evt2irq(0x940)), 683 DEFINE_RES_IRQ(evt2irq(0x960)), 684 }; 685 686 static struct platform_device tmu1_device = { 687 .name = "sh-tmu", 688 .id = 1, 689 .dev = { 690 .platform_data = &tmu1_platform_data, 691 }, 692 .resource = tmu1_resources, 693 .num_resources = ARRAY_SIZE(tmu1_resources), 694 }; 695 696 /* JPU */ 697 static struct uio_info jpu_platform_data = { 698 .name = "JPU", 699 .version = "0", 700 .irq = evt2irq(0x560), 701 }; 702 703 static struct resource jpu_resources[] = { 704 [0] = { 705 .name = "JPU", 706 .start = 0xfe980000, 707 .end = 0xfe9902d3, 708 .flags = IORESOURCE_MEM, 709 }, 710 [1] = { 711 /* place holder for contiguous memory */ 712 }, 713 }; 714 715 static struct platform_device jpu_device = { 716 .name = "uio_pdrv_genirq", 717 .id = 3, 718 .dev = { 719 .platform_data = &jpu_platform_data, 720 }, 721 .resource = jpu_resources, 722 .num_resources = ARRAY_SIZE(jpu_resources), 723 }; 724 725 /* SPU2DSP0 */ 726 static struct uio_info spu0_platform_data = { 727 .name = "SPU2DSP0", 728 .version = "0", 729 .irq = evt2irq(0xcc0), 730 }; 731 732 static struct resource spu0_resources[] = { 733 [0] = { 734 .name = "SPU2DSP0", 735 .start = 0xFE200000, 736 .end = 0xFE2FFFFF, 737 .flags = IORESOURCE_MEM, 738 }, 739 [1] = { 740 /* place holder for contiguous memory */ 741 }, 742 }; 743 744 static struct platform_device spu0_device = { 745 .name = "uio_pdrv_genirq", 746 .id = 4, 747 .dev = { 748 .platform_data = &spu0_platform_data, 749 }, 750 .resource = spu0_resources, 751 .num_resources = ARRAY_SIZE(spu0_resources), 752 }; 753 754 /* SPU2DSP1 */ 755 static struct uio_info spu1_platform_data = { 756 .name = "SPU2DSP1", 757 .version = "0", 758 .irq = evt2irq(0xce0), 759 }; 760 761 static struct resource spu1_resources[] = { 762 [0] = { 763 .name = "SPU2DSP1", 764 .start = 0xFE300000, 765 .end = 0xFE3FFFFF, 766 .flags = IORESOURCE_MEM, 767 }, 768 [1] = { 769 /* place holder for contiguous memory */ 770 }, 771 }; 772 773 static struct platform_device spu1_device = { 774 .name = "uio_pdrv_genirq", 775 .id = 5, 776 .dev = { 777 .platform_data = &spu1_platform_data, 778 }, 779 .resource = spu1_resources, 780 .num_resources = ARRAY_SIZE(spu1_resources), 781 }; 782 783 static struct platform_device *sh7724_devices[] __initdata = { 784 &scif0_device, 785 &scif1_device, 786 &scif2_device, 787 &scif3_device, 788 &scif4_device, 789 &scif5_device, 790 &cmt_device, 791 &tmu0_device, 792 &tmu1_device, 793 &dma0_device, 794 &dma1_device, 795 &rtc_device, 796 &iic0_device, 797 &iic1_device, 798 &vpu_device, 799 &veu0_device, 800 &veu1_device, 801 &beu0_device, 802 &beu1_device, 803 &jpu_device, 804 &spu0_device, 805 &spu1_device, 806 }; 807 808 static int __init sh7724_devices_setup(void) 809 { 810 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 811 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 812 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 813 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); 814 platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20); 815 platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20); 816 817 return platform_add_devices(sh7724_devices, 818 ARRAY_SIZE(sh7724_devices)); 819 } 820 arch_initcall(sh7724_devices_setup); 821 822 static struct platform_device *sh7724_early_devices[] __initdata = { 823 &scif0_device, 824 &scif1_device, 825 &scif2_device, 826 &scif3_device, 827 &scif4_device, 828 &scif5_device, 829 &cmt_device, 830 &tmu0_device, 831 &tmu1_device, 832 }; 833 834 void __init plat_early_device_setup(void) 835 { 836 early_platform_add_devices(sh7724_early_devices, 837 ARRAY_SIZE(sh7724_early_devices)); 838 } 839 840 #define RAMCR_CACHE_L2FC 0x0002 841 #define RAMCR_CACHE_L2E 0x0001 842 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) 843 844 void l2_cache_init(void) 845 { 846 /* Enable L2 cache */ 847 __raw_writel(L2_CACHE_ENABLE, RAMCR); 848 } 849 850 enum { 851 UNUSED = 0, 852 ENABLED, 853 DISABLED, 854 855 /* interrupt sources */ 856 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 857 HUDI, 858 DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3, 859 _2DG_TRI, _2DG_INI, _2DG_CEI, 860 DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3, 861 VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU, 862 SCIFA3, 863 VPU, 864 TPU, 865 CEU1, 866 BEU1, 867 USB0, USB1, 868 ATAPI, 869 RTC_ATI, RTC_PRI, RTC_CUI, 870 DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR, 871 DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR, 872 KEYSC, 873 SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2, 874 VEU0, 875 MSIOF_MSIOFI0, MSIOF_MSIOFI1, 876 SPU_SPUI0, SPU_SPUI1, 877 SCIFA4, 878 ICB, 879 ETHI, 880 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI, 881 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, 882 CMT, 883 TSIF, 884 FSI, 885 SCIFA5, 886 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, 887 IRDA, 888 JPU, 889 _2DDMAC, 890 MMC_MMC2I, MMC_MMC3I, 891 LCDC, 892 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 893 894 /* interrupt groups */ 895 DMAC1A, _2DG, DMAC0A, VIO, USB, RTC, 896 DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF, 897 }; 898 899 static struct intc_vect vectors[] __initdata = { 900 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 901 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 902 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 903 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 904 905 INTC_VECT(DMAC1A_DEI0, 0x700), 906 INTC_VECT(DMAC1A_DEI1, 0x720), 907 INTC_VECT(DMAC1A_DEI2, 0x740), 908 INTC_VECT(DMAC1A_DEI3, 0x760), 909 910 INTC_VECT(_2DG_TRI, 0x780), 911 INTC_VECT(_2DG_INI, 0x7A0), 912 INTC_VECT(_2DG_CEI, 0x7C0), 913 914 INTC_VECT(DMAC0A_DEI0, 0x800), 915 INTC_VECT(DMAC0A_DEI1, 0x820), 916 INTC_VECT(DMAC0A_DEI2, 0x840), 917 INTC_VECT(DMAC0A_DEI3, 0x860), 918 919 INTC_VECT(VIO_CEU0, 0x880), 920 INTC_VECT(VIO_BEU0, 0x8A0), 921 INTC_VECT(VIO_VEU1, 0x8C0), 922 INTC_VECT(VIO_VOU, 0x8E0), 923 924 INTC_VECT(SCIFA3, 0x900), 925 INTC_VECT(VPU, 0x980), 926 INTC_VECT(TPU, 0x9A0), 927 INTC_VECT(CEU1, 0x9E0), 928 INTC_VECT(BEU1, 0xA00), 929 INTC_VECT(USB0, 0xA20), 930 INTC_VECT(USB1, 0xA40), 931 INTC_VECT(ATAPI, 0xA60), 932 933 INTC_VECT(RTC_ATI, 0xA80), 934 INTC_VECT(RTC_PRI, 0xAA0), 935 INTC_VECT(RTC_CUI, 0xAC0), 936 937 INTC_VECT(DMAC1B_DEI4, 0xB00), 938 INTC_VECT(DMAC1B_DEI5, 0xB20), 939 INTC_VECT(DMAC1B_DADERR, 0xB40), 940 941 INTC_VECT(DMAC0B_DEI4, 0xB80), 942 INTC_VECT(DMAC0B_DEI5, 0xBA0), 943 INTC_VECT(DMAC0B_DADERR, 0xBC0), 944 945 INTC_VECT(KEYSC, 0xBE0), 946 INTC_VECT(SCIF_SCIF0, 0xC00), 947 INTC_VECT(SCIF_SCIF1, 0xC20), 948 INTC_VECT(SCIF_SCIF2, 0xC40), 949 INTC_VECT(VEU0, 0xC60), 950 INTC_VECT(MSIOF_MSIOFI0, 0xC80), 951 INTC_VECT(MSIOF_MSIOFI1, 0xCA0), 952 INTC_VECT(SPU_SPUI0, 0xCC0), 953 INTC_VECT(SPU_SPUI1, 0xCE0), 954 INTC_VECT(SCIFA4, 0xD00), 955 956 INTC_VECT(ICB, 0xD20), 957 INTC_VECT(ETHI, 0xD60), 958 959 INTC_VECT(I2C1_ALI, 0xD80), 960 INTC_VECT(I2C1_TACKI, 0xDA0), 961 INTC_VECT(I2C1_WAITI, 0xDC0), 962 INTC_VECT(I2C1_DTEI, 0xDE0), 963 964 INTC_VECT(I2C0_ALI, 0xE00), 965 INTC_VECT(I2C0_TACKI, 0xE20), 966 INTC_VECT(I2C0_WAITI, 0xE40), 967 INTC_VECT(I2C0_DTEI, 0xE60), 968 969 INTC_VECT(SDHI0, 0xE80), 970 INTC_VECT(SDHI0, 0xEA0), 971 INTC_VECT(SDHI0, 0xEC0), 972 INTC_VECT(SDHI0, 0xEE0), 973 974 INTC_VECT(CMT, 0xF00), 975 INTC_VECT(TSIF, 0xF20), 976 INTC_VECT(FSI, 0xF80), 977 INTC_VECT(SCIFA5, 0xFA0), 978 979 INTC_VECT(TMU0_TUNI0, 0x400), 980 INTC_VECT(TMU0_TUNI1, 0x420), 981 INTC_VECT(TMU0_TUNI2, 0x440), 982 983 INTC_VECT(IRDA, 0x480), 984 985 INTC_VECT(SDHI1, 0x4E0), 986 INTC_VECT(SDHI1, 0x500), 987 INTC_VECT(SDHI1, 0x520), 988 989 INTC_VECT(JPU, 0x560), 990 INTC_VECT(_2DDMAC, 0x4A0), 991 992 INTC_VECT(MMC_MMC2I, 0x5A0), 993 INTC_VECT(MMC_MMC3I, 0x5C0), 994 995 INTC_VECT(LCDC, 0xF40), 996 997 INTC_VECT(TMU1_TUNI0, 0x920), 998 INTC_VECT(TMU1_TUNI1, 0x940), 999 INTC_VECT(TMU1_TUNI2, 0x960), 1000 }; 1001 1002 static struct intc_group groups[] __initdata = { 1003 INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3), 1004 INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI), 1005 INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3), 1006 INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU), 1007 INTC_GROUP(USB, USB0, USB1), 1008 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 1009 INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR), 1010 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR), 1011 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI), 1012 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI), 1013 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1), 1014 INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I), 1015 }; 1016 1017 static struct intc_mask_reg mask_registers[] __initdata = { 1018 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 1019 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, 1020 0, ENABLED, ENABLED, ENABLED } }, 1021 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 1022 { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0, 1023 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } }, 1024 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 1025 { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } }, 1026 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 1027 { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0, 1028 SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } }, 1029 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 1030 { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0, 1031 JPU, 0, 0, LCDC } }, 1032 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 1033 { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4, 1034 VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } }, 1035 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 1036 { 0, 0, ICB, SCIFA4, 1037 CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } }, 1038 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 1039 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, 1040 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } }, 1041 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 1042 { DISABLED, ENABLED, ENABLED, ENABLED, 1043 0, 0, SCIFA5, FSI } }, 1044 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 1045 { 0, 0, 0, CMT, 0, USB1, USB0, 0 } }, 1046 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 1047 { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4, 1048 0, RTC_CUI, RTC_PRI, RTC_ATI } }, 1049 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 1050 { 0, _2DG_CEI, _2DG_INI, _2DG_TRI, 1051 0, TPU, 0, TSIF } }, 1052 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */ 1053 { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } }, 1054 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 1055 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1056 }; 1057 1058 static struct intc_prio_reg prio_registers[] __initdata = { 1059 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, 1060 TMU0_TUNI2, IRDA } }, 1061 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } }, 1062 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, 1063 TMU1_TUNI2, SPU } }, 1064 { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } }, 1065 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } }, 1066 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } }, 1067 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, 1068 SCIF_SCIF2, VEU0 } }, 1069 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1, 1070 I2C1, I2C0 } }, 1071 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } }, 1072 { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } }, 1073 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } }, 1074 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } }, 1075 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 1076 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1077 }; 1078 1079 static struct intc_sense_reg sense_registers[] __initdata = { 1080 { 0xa414001c, 16, 2, /* ICR1 */ 1081 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1082 }; 1083 1084 static struct intc_mask_reg ack_registers[] __initdata = { 1085 { 0xa4140024, 0, 8, /* INTREQ00 */ 1086 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1087 }; 1088 1089 static struct intc_desc intc_desc __initdata = { 1090 .name = "sh7724", 1091 .force_enable = ENABLED, 1092 .force_disable = DISABLED, 1093 .hw = INTC_HW_DESC(vectors, groups, mask_registers, 1094 prio_registers, sense_registers, ack_registers), 1095 }; 1096 1097 void __init plat_irq_setup(void) 1098 { 1099 register_intc_controller(&intc_desc); 1100 } 1101 1102 static struct { 1103 /* BSC */ 1104 unsigned long mmselr; 1105 unsigned long cs0bcr; 1106 unsigned long cs4bcr; 1107 unsigned long cs5abcr; 1108 unsigned long cs5bbcr; 1109 unsigned long cs6abcr; 1110 unsigned long cs6bbcr; 1111 unsigned long cs4wcr; 1112 unsigned long cs5awcr; 1113 unsigned long cs5bwcr; 1114 unsigned long cs6awcr; 1115 unsigned long cs6bwcr; 1116 /* INTC */ 1117 unsigned short ipra; 1118 unsigned short iprb; 1119 unsigned short iprc; 1120 unsigned short iprd; 1121 unsigned short ipre; 1122 unsigned short iprf; 1123 unsigned short iprg; 1124 unsigned short iprh; 1125 unsigned short ipri; 1126 unsigned short iprj; 1127 unsigned short iprk; 1128 unsigned short iprl; 1129 unsigned char imr0; 1130 unsigned char imr1; 1131 unsigned char imr2; 1132 unsigned char imr3; 1133 unsigned char imr4; 1134 unsigned char imr5; 1135 unsigned char imr6; 1136 unsigned char imr7; 1137 unsigned char imr8; 1138 unsigned char imr9; 1139 unsigned char imr10; 1140 unsigned char imr11; 1141 unsigned char imr12; 1142 /* RWDT */ 1143 unsigned short rwtcnt; 1144 unsigned short rwtcsr; 1145 /* CPG */ 1146 unsigned long irdaclk; 1147 unsigned long spuclk; 1148 } sh7724_rstandby_state; 1149 1150 static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb, 1151 unsigned long flags, void *unused) 1152 { 1153 if (!(flags & SUSP_SH_RSTANDBY)) 1154 return NOTIFY_DONE; 1155 1156 /* BCR */ 1157 sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */ 1158 sh7724_rstandby_state.mmselr |= 0xa5a50000; 1159 sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */ 1160 sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */ 1161 sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */ 1162 sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */ 1163 sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */ 1164 sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */ 1165 sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */ 1166 sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */ 1167 sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */ 1168 sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */ 1169 sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */ 1170 1171 /* INTC */ 1172 sh7724_rstandby_state.ipra = __raw_readw(0xa4080000); /* IPRA */ 1173 sh7724_rstandby_state.iprb = __raw_readw(0xa4080004); /* IPRB */ 1174 sh7724_rstandby_state.iprc = __raw_readw(0xa4080008); /* IPRC */ 1175 sh7724_rstandby_state.iprd = __raw_readw(0xa408000c); /* IPRD */ 1176 sh7724_rstandby_state.ipre = __raw_readw(0xa4080010); /* IPRE */ 1177 sh7724_rstandby_state.iprf = __raw_readw(0xa4080014); /* IPRF */ 1178 sh7724_rstandby_state.iprg = __raw_readw(0xa4080018); /* IPRG */ 1179 sh7724_rstandby_state.iprh = __raw_readw(0xa408001c); /* IPRH */ 1180 sh7724_rstandby_state.ipri = __raw_readw(0xa4080020); /* IPRI */ 1181 sh7724_rstandby_state.iprj = __raw_readw(0xa4080024); /* IPRJ */ 1182 sh7724_rstandby_state.iprk = __raw_readw(0xa4080028); /* IPRK */ 1183 sh7724_rstandby_state.iprl = __raw_readw(0xa408002c); /* IPRL */ 1184 sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */ 1185 sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */ 1186 sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */ 1187 sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */ 1188 sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */ 1189 sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */ 1190 sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */ 1191 sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */ 1192 sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */ 1193 sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */ 1194 sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */ 1195 sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */ 1196 sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */ 1197 1198 /* RWDT */ 1199 sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */ 1200 sh7724_rstandby_state.rwtcnt |= 0x5a00; 1201 sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */ 1202 sh7724_rstandby_state.rwtcsr |= 0xa500; 1203 __raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004); 1204 1205 /* CPG */ 1206 sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */ 1207 sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */ 1208 1209 return NOTIFY_DONE; 1210 } 1211 1212 static int sh7724_post_sleep_notifier_call(struct notifier_block *nb, 1213 unsigned long flags, void *unused) 1214 { 1215 if (!(flags & SUSP_SH_RSTANDBY)) 1216 return NOTIFY_DONE; 1217 1218 /* BCR */ 1219 __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */ 1220 __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */ 1221 __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */ 1222 __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */ 1223 __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */ 1224 __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */ 1225 __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */ 1226 __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */ 1227 __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */ 1228 __raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */ 1229 __raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */ 1230 __raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */ 1231 1232 /* INTC */ 1233 __raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */ 1234 __raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */ 1235 __raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */ 1236 __raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */ 1237 __raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */ 1238 __raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */ 1239 __raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */ 1240 __raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */ 1241 __raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */ 1242 __raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */ 1243 __raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */ 1244 __raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */ 1245 __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */ 1246 __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */ 1247 __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */ 1248 __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */ 1249 __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */ 1250 __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */ 1251 __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */ 1252 __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */ 1253 __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */ 1254 __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */ 1255 __raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8); /* IMR10 */ 1256 __raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac); /* IMR11 */ 1257 __raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0); /* IMR12 */ 1258 1259 /* RWDT */ 1260 __raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */ 1261 __raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */ 1262 1263 /* CPG */ 1264 __raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018); /* IRDACLKCR */ 1265 __raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c); /* SPUCLKCR */ 1266 1267 return NOTIFY_DONE; 1268 } 1269 1270 static struct notifier_block sh7724_pre_sleep_notifier = { 1271 .notifier_call = sh7724_pre_sleep_notifier_call, 1272 .priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU), 1273 }; 1274 1275 static struct notifier_block sh7724_post_sleep_notifier = { 1276 .notifier_call = sh7724_post_sleep_notifier_call, 1277 .priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU), 1278 }; 1279 1280 static int __init sh7724_sleep_setup(void) 1281 { 1282 atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list, 1283 &sh7724_pre_sleep_notifier); 1284 1285 atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list, 1286 &sh7724_post_sleep_notifier); 1287 return 0; 1288 } 1289 arch_initcall(sh7724_sleep_setup); 1290 1291