1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SH7724 Setup 4 * 5 * Copyright (C) 2009 Renesas Solutions Corp. 6 * 7 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 8 * 9 * Based on SH7723 Setup 10 * Copyright (C) 2008 Paul Mundt 11 */ 12 #include <linux/platform_device.h> 13 #include <linux/init.h> 14 #include <linux/serial.h> 15 #include <linux/mm.h> 16 #include <linux/serial_sci.h> 17 #include <linux/uio_driver.h> 18 #include <linux/sh_dma.h> 19 #include <linux/sh_timer.h> 20 #include <linux/sh_intc.h> 21 #include <linux/io.h> 22 #include <linux/notifier.h> 23 24 #include <asm/suspend.h> 25 #include <asm/clock.h> 26 #include <asm/mmzone.h> 27 28 #include <cpu/dma-register.h> 29 #include <cpu/sh7724.h> 30 31 /* DMA */ 32 static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = { 33 { 34 .slave_id = SHDMA_SLAVE_SCIF0_TX, 35 .addr = 0xffe0000c, 36 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 37 .mid_rid = 0x21, 38 }, { 39 .slave_id = SHDMA_SLAVE_SCIF0_RX, 40 .addr = 0xffe00014, 41 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 42 .mid_rid = 0x22, 43 }, { 44 .slave_id = SHDMA_SLAVE_SCIF1_TX, 45 .addr = 0xffe1000c, 46 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 47 .mid_rid = 0x25, 48 }, { 49 .slave_id = SHDMA_SLAVE_SCIF1_RX, 50 .addr = 0xffe10014, 51 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 52 .mid_rid = 0x26, 53 }, { 54 .slave_id = SHDMA_SLAVE_SCIF2_TX, 55 .addr = 0xffe2000c, 56 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 57 .mid_rid = 0x29, 58 }, { 59 .slave_id = SHDMA_SLAVE_SCIF2_RX, 60 .addr = 0xffe20014, 61 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 62 .mid_rid = 0x2a, 63 }, { 64 .slave_id = SHDMA_SLAVE_SCIF3_TX, 65 .addr = 0xa4e30020, 66 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 67 .mid_rid = 0x2d, 68 }, { 69 .slave_id = SHDMA_SLAVE_SCIF3_RX, 70 .addr = 0xa4e30024, 71 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 72 .mid_rid = 0x2e, 73 }, { 74 .slave_id = SHDMA_SLAVE_SCIF4_TX, 75 .addr = 0xa4e40020, 76 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 77 .mid_rid = 0x31, 78 }, { 79 .slave_id = SHDMA_SLAVE_SCIF4_RX, 80 .addr = 0xa4e40024, 81 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 82 .mid_rid = 0x32, 83 }, { 84 .slave_id = SHDMA_SLAVE_SCIF5_TX, 85 .addr = 0xa4e50020, 86 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 87 .mid_rid = 0x35, 88 }, { 89 .slave_id = SHDMA_SLAVE_SCIF5_RX, 90 .addr = 0xa4e50024, 91 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 92 .mid_rid = 0x36, 93 }, { 94 .slave_id = SHDMA_SLAVE_USB0D0_TX, 95 .addr = 0xA4D80100, 96 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 97 .mid_rid = 0x73, 98 }, { 99 .slave_id = SHDMA_SLAVE_USB0D0_RX, 100 .addr = 0xA4D80100, 101 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 102 .mid_rid = 0x73, 103 }, { 104 .slave_id = SHDMA_SLAVE_USB0D1_TX, 105 .addr = 0xA4D80120, 106 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 107 .mid_rid = 0x77, 108 }, { 109 .slave_id = SHDMA_SLAVE_USB0D1_RX, 110 .addr = 0xA4D80120, 111 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 112 .mid_rid = 0x77, 113 }, { 114 .slave_id = SHDMA_SLAVE_USB1D0_TX, 115 .addr = 0xA4D90100, 116 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 117 .mid_rid = 0xab, 118 }, { 119 .slave_id = SHDMA_SLAVE_USB1D0_RX, 120 .addr = 0xA4D90100, 121 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 122 .mid_rid = 0xab, 123 }, { 124 .slave_id = SHDMA_SLAVE_USB1D1_TX, 125 .addr = 0xA4D90120, 126 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 127 .mid_rid = 0xaf, 128 }, { 129 .slave_id = SHDMA_SLAVE_USB1D1_RX, 130 .addr = 0xA4D90120, 131 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 132 .mid_rid = 0xaf, 133 }, { 134 .slave_id = SHDMA_SLAVE_SDHI0_TX, 135 .addr = 0x04ce0030, 136 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT), 137 .mid_rid = 0xc1, 138 }, { 139 .slave_id = SHDMA_SLAVE_SDHI0_RX, 140 .addr = 0x04ce0030, 141 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT), 142 .mid_rid = 0xc2, 143 }, { 144 .slave_id = SHDMA_SLAVE_SDHI1_TX, 145 .addr = 0x04cf0030, 146 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT), 147 .mid_rid = 0xc9, 148 }, { 149 .slave_id = SHDMA_SLAVE_SDHI1_RX, 150 .addr = 0x04cf0030, 151 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT), 152 .mid_rid = 0xca, 153 }, 154 }; 155 156 static const struct sh_dmae_channel sh7724_dmae_channels[] = { 157 { 158 .offset = 0, 159 .dmars = 0, 160 .dmars_bit = 0, 161 }, { 162 .offset = 0x10, 163 .dmars = 0, 164 .dmars_bit = 8, 165 }, { 166 .offset = 0x20, 167 .dmars = 4, 168 .dmars_bit = 0, 169 }, { 170 .offset = 0x30, 171 .dmars = 4, 172 .dmars_bit = 8, 173 }, { 174 .offset = 0x50, 175 .dmars = 8, 176 .dmars_bit = 0, 177 }, { 178 .offset = 0x60, 179 .dmars = 8, 180 .dmars_bit = 8, 181 } 182 }; 183 184 static const unsigned int ts_shift[] = TS_SHIFT; 185 186 static struct sh_dmae_pdata dma_platform_data = { 187 .slave = sh7724_dmae_slaves, 188 .slave_num = ARRAY_SIZE(sh7724_dmae_slaves), 189 .channel = sh7724_dmae_channels, 190 .channel_num = ARRAY_SIZE(sh7724_dmae_channels), 191 .ts_low_shift = CHCR_TS_LOW_SHIFT, 192 .ts_low_mask = CHCR_TS_LOW_MASK, 193 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 194 .ts_high_mask = CHCR_TS_HIGH_MASK, 195 .ts_shift = ts_shift, 196 .ts_shift_num = ARRAY_SIZE(ts_shift), 197 .dmaor_init = DMAOR_INIT, 198 }; 199 200 /* Resource order important! */ 201 static struct resource sh7724_dmae0_resources[] = { 202 { 203 /* Channel registers and DMAOR */ 204 .start = 0xfe008020, 205 .end = 0xfe00808f, 206 .flags = IORESOURCE_MEM, 207 }, 208 { 209 /* DMARSx */ 210 .start = 0xfe009000, 211 .end = 0xfe00900b, 212 .flags = IORESOURCE_MEM, 213 }, 214 { 215 .name = "error_irq", 216 .start = evt2irq(0xbc0), 217 .end = evt2irq(0xbc0), 218 .flags = IORESOURCE_IRQ, 219 }, 220 { 221 /* IRQ for channels 0-3 */ 222 .start = evt2irq(0x800), 223 .end = evt2irq(0x860), 224 .flags = IORESOURCE_IRQ, 225 }, 226 { 227 /* IRQ for channels 4-5 */ 228 .start = evt2irq(0xb80), 229 .end = evt2irq(0xba0), 230 .flags = IORESOURCE_IRQ, 231 }, 232 }; 233 234 /* Resource order important! */ 235 static struct resource sh7724_dmae1_resources[] = { 236 { 237 /* Channel registers and DMAOR */ 238 .start = 0xfdc08020, 239 .end = 0xfdc0808f, 240 .flags = IORESOURCE_MEM, 241 }, 242 { 243 /* DMARSx */ 244 .start = 0xfdc09000, 245 .end = 0xfdc0900b, 246 .flags = IORESOURCE_MEM, 247 }, 248 { 249 .name = "error_irq", 250 .start = evt2irq(0xb40), 251 .end = evt2irq(0xb40), 252 .flags = IORESOURCE_IRQ, 253 }, 254 { 255 /* IRQ for channels 0-3 */ 256 .start = evt2irq(0x700), 257 .end = evt2irq(0x760), 258 .flags = IORESOURCE_IRQ, 259 }, 260 { 261 /* IRQ for channels 4-5 */ 262 .start = evt2irq(0xb00), 263 .end = evt2irq(0xb20), 264 .flags = IORESOURCE_IRQ, 265 }, 266 }; 267 268 static struct platform_device dma0_device = { 269 .name = "sh-dma-engine", 270 .id = 0, 271 .resource = sh7724_dmae0_resources, 272 .num_resources = ARRAY_SIZE(sh7724_dmae0_resources), 273 .dev = { 274 .platform_data = &dma_platform_data, 275 }, 276 }; 277 278 static struct platform_device dma1_device = { 279 .name = "sh-dma-engine", 280 .id = 1, 281 .resource = sh7724_dmae1_resources, 282 .num_resources = ARRAY_SIZE(sh7724_dmae1_resources), 283 .dev = { 284 .platform_data = &dma_platform_data, 285 }, 286 }; 287 288 /* Serial */ 289 static struct plat_sci_port scif0_platform_data = { 290 .scscr = SCSCR_REIE, 291 .type = PORT_SCIF, 292 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 293 }; 294 295 static struct resource scif0_resources[] = { 296 DEFINE_RES_MEM(0xffe00000, 0x100), 297 DEFINE_RES_IRQ(evt2irq(0xc00)), 298 }; 299 300 static struct platform_device scif0_device = { 301 .name = "sh-sci", 302 .id = 0, 303 .resource = scif0_resources, 304 .num_resources = ARRAY_SIZE(scif0_resources), 305 .dev = { 306 .platform_data = &scif0_platform_data, 307 }, 308 }; 309 310 static struct plat_sci_port scif1_platform_data = { 311 .scscr = SCSCR_REIE, 312 .type = PORT_SCIF, 313 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 314 }; 315 316 static struct resource scif1_resources[] = { 317 DEFINE_RES_MEM(0xffe10000, 0x100), 318 DEFINE_RES_IRQ(evt2irq(0xc20)), 319 }; 320 321 static struct platform_device scif1_device = { 322 .name = "sh-sci", 323 .id = 1, 324 .resource = scif1_resources, 325 .num_resources = ARRAY_SIZE(scif1_resources), 326 .dev = { 327 .platform_data = &scif1_platform_data, 328 }, 329 }; 330 331 static struct plat_sci_port scif2_platform_data = { 332 .scscr = SCSCR_REIE, 333 .type = PORT_SCIF, 334 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 335 }; 336 337 static struct resource scif2_resources[] = { 338 DEFINE_RES_MEM(0xffe20000, 0x100), 339 DEFINE_RES_IRQ(evt2irq(0xc40)), 340 }; 341 342 static struct platform_device scif2_device = { 343 .name = "sh-sci", 344 .id = 2, 345 .resource = scif2_resources, 346 .num_resources = ARRAY_SIZE(scif2_resources), 347 .dev = { 348 .platform_data = &scif2_platform_data, 349 }, 350 }; 351 352 static struct plat_sci_port scif3_platform_data = { 353 .sampling_rate = 8, 354 .type = PORT_SCIFA, 355 }; 356 357 static struct resource scif3_resources[] = { 358 DEFINE_RES_MEM(0xa4e30000, 0x100), 359 DEFINE_RES_IRQ(evt2irq(0x900)), 360 }; 361 362 static struct platform_device scif3_device = { 363 .name = "sh-sci", 364 .id = 3, 365 .resource = scif3_resources, 366 .num_resources = ARRAY_SIZE(scif3_resources), 367 .dev = { 368 .platform_data = &scif3_platform_data, 369 }, 370 }; 371 372 static struct plat_sci_port scif4_platform_data = { 373 .sampling_rate = 8, 374 .type = PORT_SCIFA, 375 }; 376 377 static struct resource scif4_resources[] = { 378 DEFINE_RES_MEM(0xa4e40000, 0x100), 379 DEFINE_RES_IRQ(evt2irq(0xd00)), 380 }; 381 382 static struct platform_device scif4_device = { 383 .name = "sh-sci", 384 .id = 4, 385 .resource = scif4_resources, 386 .num_resources = ARRAY_SIZE(scif4_resources), 387 .dev = { 388 .platform_data = &scif4_platform_data, 389 }, 390 }; 391 392 static struct plat_sci_port scif5_platform_data = { 393 .sampling_rate = 8, 394 .type = PORT_SCIFA, 395 }; 396 397 static struct resource scif5_resources[] = { 398 DEFINE_RES_MEM(0xa4e50000, 0x100), 399 DEFINE_RES_IRQ(evt2irq(0xfa0)), 400 }; 401 402 static struct platform_device scif5_device = { 403 .name = "sh-sci", 404 .id = 5, 405 .resource = scif5_resources, 406 .num_resources = ARRAY_SIZE(scif5_resources), 407 .dev = { 408 .platform_data = &scif5_platform_data, 409 }, 410 }; 411 412 /* RTC */ 413 static struct resource rtc_resources[] = { 414 [0] = { 415 .start = 0xa465fec0, 416 .end = 0xa465fec0 + 0x58 - 1, 417 .flags = IORESOURCE_IO, 418 }, 419 [1] = { 420 /* Period IRQ */ 421 .start = evt2irq(0xaa0), 422 .flags = IORESOURCE_IRQ, 423 }, 424 [2] = { 425 /* Carry IRQ */ 426 .start = evt2irq(0xac0), 427 .flags = IORESOURCE_IRQ, 428 }, 429 [3] = { 430 /* Alarm IRQ */ 431 .start = evt2irq(0xa80), 432 .flags = IORESOURCE_IRQ, 433 }, 434 }; 435 436 static struct platform_device rtc_device = { 437 .name = "sh-rtc", 438 .id = -1, 439 .num_resources = ARRAY_SIZE(rtc_resources), 440 .resource = rtc_resources, 441 }; 442 443 /* I2C0 */ 444 static struct resource iic0_resources[] = { 445 [0] = { 446 .name = "IIC0", 447 .start = 0x04470000, 448 .end = 0x04470018 - 1, 449 .flags = IORESOURCE_MEM, 450 }, 451 [1] = { 452 .start = evt2irq(0xe00), 453 .end = evt2irq(0xe60), 454 .flags = IORESOURCE_IRQ, 455 }, 456 }; 457 458 static struct platform_device iic0_device = { 459 .name = "i2c-sh_mobile", 460 .id = 0, /* "i2c0" clock */ 461 .num_resources = ARRAY_SIZE(iic0_resources), 462 .resource = iic0_resources, 463 }; 464 465 /* I2C1 */ 466 static struct resource iic1_resources[] = { 467 [0] = { 468 .name = "IIC1", 469 .start = 0x04750000, 470 .end = 0x04750018 - 1, 471 .flags = IORESOURCE_MEM, 472 }, 473 [1] = { 474 .start = evt2irq(0xd80), 475 .end = evt2irq(0xde0), 476 .flags = IORESOURCE_IRQ, 477 }, 478 }; 479 480 static struct platform_device iic1_device = { 481 .name = "i2c-sh_mobile", 482 .id = 1, /* "i2c1" clock */ 483 .num_resources = ARRAY_SIZE(iic1_resources), 484 .resource = iic1_resources, 485 }; 486 487 /* VPU */ 488 static struct uio_info vpu_platform_data = { 489 .name = "VPU5F", 490 .version = "0", 491 .irq = evt2irq(0x980), 492 }; 493 494 static struct resource vpu_resources[] = { 495 [0] = { 496 .name = "VPU", 497 .start = 0xfe900000, 498 .end = 0xfe902807, 499 .flags = IORESOURCE_MEM, 500 }, 501 [1] = { 502 /* place holder for contiguous memory */ 503 }, 504 }; 505 506 static struct platform_device vpu_device = { 507 .name = "uio_pdrv_genirq", 508 .id = 0, 509 .dev = { 510 .platform_data = &vpu_platform_data, 511 }, 512 .resource = vpu_resources, 513 .num_resources = ARRAY_SIZE(vpu_resources), 514 }; 515 516 /* VEU0 */ 517 static struct uio_info veu0_platform_data = { 518 .name = "VEU3F0", 519 .version = "0", 520 .irq = evt2irq(0xc60), 521 }; 522 523 static struct resource veu0_resources[] = { 524 [0] = { 525 .name = "VEU3F0", 526 .start = 0xfe920000, 527 .end = 0xfe9200cb, 528 .flags = IORESOURCE_MEM, 529 }, 530 [1] = { 531 /* place holder for contiguous memory */ 532 }, 533 }; 534 535 static struct platform_device veu0_device = { 536 .name = "uio_pdrv_genirq", 537 .id = 1, 538 .dev = { 539 .platform_data = &veu0_platform_data, 540 }, 541 .resource = veu0_resources, 542 .num_resources = ARRAY_SIZE(veu0_resources), 543 }; 544 545 /* VEU1 */ 546 static struct uio_info veu1_platform_data = { 547 .name = "VEU3F1", 548 .version = "0", 549 .irq = evt2irq(0x8c0), 550 }; 551 552 static struct resource veu1_resources[] = { 553 [0] = { 554 .name = "VEU3F1", 555 .start = 0xfe924000, 556 .end = 0xfe9240cb, 557 .flags = IORESOURCE_MEM, 558 }, 559 [1] = { 560 /* place holder for contiguous memory */ 561 }, 562 }; 563 564 static struct platform_device veu1_device = { 565 .name = "uio_pdrv_genirq", 566 .id = 2, 567 .dev = { 568 .platform_data = &veu1_platform_data, 569 }, 570 .resource = veu1_resources, 571 .num_resources = ARRAY_SIZE(veu1_resources), 572 }; 573 574 /* BEU0 */ 575 static struct uio_info beu0_platform_data = { 576 .name = "BEU0", 577 .version = "0", 578 .irq = evt2irq(0x8A0), 579 }; 580 581 static struct resource beu0_resources[] = { 582 [0] = { 583 .name = "BEU0", 584 .start = 0xfe930000, 585 .end = 0xfe933400, 586 .flags = IORESOURCE_MEM, 587 }, 588 [1] = { 589 /* place holder for contiguous memory */ 590 }, 591 }; 592 593 static struct platform_device beu0_device = { 594 .name = "uio_pdrv_genirq", 595 .id = 6, 596 .dev = { 597 .platform_data = &beu0_platform_data, 598 }, 599 .resource = beu0_resources, 600 .num_resources = ARRAY_SIZE(beu0_resources), 601 }; 602 603 /* BEU1 */ 604 static struct uio_info beu1_platform_data = { 605 .name = "BEU1", 606 .version = "0", 607 .irq = evt2irq(0xA00), 608 }; 609 610 static struct resource beu1_resources[] = { 611 [0] = { 612 .name = "BEU1", 613 .start = 0xfe940000, 614 .end = 0xfe943400, 615 .flags = IORESOURCE_MEM, 616 }, 617 [1] = { 618 /* place holder for contiguous memory */ 619 }, 620 }; 621 622 static struct platform_device beu1_device = { 623 .name = "uio_pdrv_genirq", 624 .id = 7, 625 .dev = { 626 .platform_data = &beu1_platform_data, 627 }, 628 .resource = beu1_resources, 629 .num_resources = ARRAY_SIZE(beu1_resources), 630 }; 631 632 static struct sh_timer_config cmt_platform_data = { 633 .channels_mask = 0x20, 634 }; 635 636 static struct resource cmt_resources[] = { 637 DEFINE_RES_MEM(0x044a0000, 0x70), 638 DEFINE_RES_IRQ(evt2irq(0xf00)), 639 }; 640 641 static struct platform_device cmt_device = { 642 .name = "sh-cmt-32", 643 .id = 0, 644 .dev = { 645 .platform_data = &cmt_platform_data, 646 }, 647 .resource = cmt_resources, 648 .num_resources = ARRAY_SIZE(cmt_resources), 649 }; 650 651 static struct sh_timer_config tmu0_platform_data = { 652 .channels_mask = 7, 653 }; 654 655 static struct resource tmu0_resources[] = { 656 DEFINE_RES_MEM(0xffd80000, 0x2c), 657 DEFINE_RES_IRQ(evt2irq(0x400)), 658 DEFINE_RES_IRQ(evt2irq(0x420)), 659 DEFINE_RES_IRQ(evt2irq(0x440)), 660 }; 661 662 static struct platform_device tmu0_device = { 663 .name = "sh-tmu", 664 .id = 0, 665 .dev = { 666 .platform_data = &tmu0_platform_data, 667 }, 668 .resource = tmu0_resources, 669 .num_resources = ARRAY_SIZE(tmu0_resources), 670 }; 671 672 static struct sh_timer_config tmu1_platform_data = { 673 .channels_mask = 7, 674 }; 675 676 static struct resource tmu1_resources[] = { 677 DEFINE_RES_MEM(0xffd90000, 0x2c), 678 DEFINE_RES_IRQ(evt2irq(0x920)), 679 DEFINE_RES_IRQ(evt2irq(0x940)), 680 DEFINE_RES_IRQ(evt2irq(0x960)), 681 }; 682 683 static struct platform_device tmu1_device = { 684 .name = "sh-tmu", 685 .id = 1, 686 .dev = { 687 .platform_data = &tmu1_platform_data, 688 }, 689 .resource = tmu1_resources, 690 .num_resources = ARRAY_SIZE(tmu1_resources), 691 }; 692 693 /* JPU */ 694 static struct uio_info jpu_platform_data = { 695 .name = "JPU", 696 .version = "0", 697 .irq = evt2irq(0x560), 698 }; 699 700 static struct resource jpu_resources[] = { 701 [0] = { 702 .name = "JPU", 703 .start = 0xfe980000, 704 .end = 0xfe9902d3, 705 .flags = IORESOURCE_MEM, 706 }, 707 [1] = { 708 /* place holder for contiguous memory */ 709 }, 710 }; 711 712 static struct platform_device jpu_device = { 713 .name = "uio_pdrv_genirq", 714 .id = 3, 715 .dev = { 716 .platform_data = &jpu_platform_data, 717 }, 718 .resource = jpu_resources, 719 .num_resources = ARRAY_SIZE(jpu_resources), 720 }; 721 722 /* SPU2DSP0 */ 723 static struct uio_info spu0_platform_data = { 724 .name = "SPU2DSP0", 725 .version = "0", 726 .irq = evt2irq(0xcc0), 727 }; 728 729 static struct resource spu0_resources[] = { 730 [0] = { 731 .name = "SPU2DSP0", 732 .start = 0xFE200000, 733 .end = 0xFE2FFFFF, 734 .flags = IORESOURCE_MEM, 735 }, 736 [1] = { 737 /* place holder for contiguous memory */ 738 }, 739 }; 740 741 static struct platform_device spu0_device = { 742 .name = "uio_pdrv_genirq", 743 .id = 4, 744 .dev = { 745 .platform_data = &spu0_platform_data, 746 }, 747 .resource = spu0_resources, 748 .num_resources = ARRAY_SIZE(spu0_resources), 749 }; 750 751 /* SPU2DSP1 */ 752 static struct uio_info spu1_platform_data = { 753 .name = "SPU2DSP1", 754 .version = "0", 755 .irq = evt2irq(0xce0), 756 }; 757 758 static struct resource spu1_resources[] = { 759 [0] = { 760 .name = "SPU2DSP1", 761 .start = 0xFE300000, 762 .end = 0xFE3FFFFF, 763 .flags = IORESOURCE_MEM, 764 }, 765 [1] = { 766 /* place holder for contiguous memory */ 767 }, 768 }; 769 770 static struct platform_device spu1_device = { 771 .name = "uio_pdrv_genirq", 772 .id = 5, 773 .dev = { 774 .platform_data = &spu1_platform_data, 775 }, 776 .resource = spu1_resources, 777 .num_resources = ARRAY_SIZE(spu1_resources), 778 }; 779 780 static struct platform_device *sh7724_devices[] __initdata = { 781 &scif0_device, 782 &scif1_device, 783 &scif2_device, 784 &scif3_device, 785 &scif4_device, 786 &scif5_device, 787 &cmt_device, 788 &tmu0_device, 789 &tmu1_device, 790 &dma0_device, 791 &dma1_device, 792 &rtc_device, 793 &iic0_device, 794 &iic1_device, 795 &vpu_device, 796 &veu0_device, 797 &veu1_device, 798 &beu0_device, 799 &beu1_device, 800 &jpu_device, 801 &spu0_device, 802 &spu1_device, 803 }; 804 805 static int __init sh7724_devices_setup(void) 806 { 807 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 808 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 809 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 810 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); 811 platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20); 812 platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20); 813 814 return platform_add_devices(sh7724_devices, 815 ARRAY_SIZE(sh7724_devices)); 816 } 817 arch_initcall(sh7724_devices_setup); 818 819 static struct platform_device *sh7724_early_devices[] __initdata = { 820 &scif0_device, 821 &scif1_device, 822 &scif2_device, 823 &scif3_device, 824 &scif4_device, 825 &scif5_device, 826 &cmt_device, 827 &tmu0_device, 828 &tmu1_device, 829 }; 830 831 void __init plat_early_device_setup(void) 832 { 833 early_platform_add_devices(sh7724_early_devices, 834 ARRAY_SIZE(sh7724_early_devices)); 835 } 836 837 #define RAMCR_CACHE_L2FC 0x0002 838 #define RAMCR_CACHE_L2E 0x0001 839 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) 840 841 void l2_cache_init(void) 842 { 843 /* Enable L2 cache */ 844 __raw_writel(L2_CACHE_ENABLE, RAMCR); 845 } 846 847 enum { 848 UNUSED = 0, 849 ENABLED, 850 DISABLED, 851 852 /* interrupt sources */ 853 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 854 HUDI, 855 DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3, 856 _2DG_TRI, _2DG_INI, _2DG_CEI, 857 DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3, 858 VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU, 859 SCIFA3, 860 VPU, 861 TPU, 862 CEU1, 863 BEU1, 864 USB0, USB1, 865 ATAPI, 866 RTC_ATI, RTC_PRI, RTC_CUI, 867 DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR, 868 DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR, 869 KEYSC, 870 SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2, 871 VEU0, 872 MSIOF_MSIOFI0, MSIOF_MSIOFI1, 873 SPU_SPUI0, SPU_SPUI1, 874 SCIFA4, 875 ICB, 876 ETHI, 877 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI, 878 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, 879 CMT, 880 TSIF, 881 FSI, 882 SCIFA5, 883 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, 884 IRDA, 885 JPU, 886 _2DDMAC, 887 MMC_MMC2I, MMC_MMC3I, 888 LCDC, 889 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 890 891 /* interrupt groups */ 892 DMAC1A, _2DG, DMAC0A, VIO, USB, RTC, 893 DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF, 894 }; 895 896 static struct intc_vect vectors[] __initdata = { 897 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 898 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 899 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 900 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 901 902 INTC_VECT(DMAC1A_DEI0, 0x700), 903 INTC_VECT(DMAC1A_DEI1, 0x720), 904 INTC_VECT(DMAC1A_DEI2, 0x740), 905 INTC_VECT(DMAC1A_DEI3, 0x760), 906 907 INTC_VECT(_2DG_TRI, 0x780), 908 INTC_VECT(_2DG_INI, 0x7A0), 909 INTC_VECT(_2DG_CEI, 0x7C0), 910 911 INTC_VECT(DMAC0A_DEI0, 0x800), 912 INTC_VECT(DMAC0A_DEI1, 0x820), 913 INTC_VECT(DMAC0A_DEI2, 0x840), 914 INTC_VECT(DMAC0A_DEI3, 0x860), 915 916 INTC_VECT(VIO_CEU0, 0x880), 917 INTC_VECT(VIO_BEU0, 0x8A0), 918 INTC_VECT(VIO_VEU1, 0x8C0), 919 INTC_VECT(VIO_VOU, 0x8E0), 920 921 INTC_VECT(SCIFA3, 0x900), 922 INTC_VECT(VPU, 0x980), 923 INTC_VECT(TPU, 0x9A0), 924 INTC_VECT(CEU1, 0x9E0), 925 INTC_VECT(BEU1, 0xA00), 926 INTC_VECT(USB0, 0xA20), 927 INTC_VECT(USB1, 0xA40), 928 INTC_VECT(ATAPI, 0xA60), 929 930 INTC_VECT(RTC_ATI, 0xA80), 931 INTC_VECT(RTC_PRI, 0xAA0), 932 INTC_VECT(RTC_CUI, 0xAC0), 933 934 INTC_VECT(DMAC1B_DEI4, 0xB00), 935 INTC_VECT(DMAC1B_DEI5, 0xB20), 936 INTC_VECT(DMAC1B_DADERR, 0xB40), 937 938 INTC_VECT(DMAC0B_DEI4, 0xB80), 939 INTC_VECT(DMAC0B_DEI5, 0xBA0), 940 INTC_VECT(DMAC0B_DADERR, 0xBC0), 941 942 INTC_VECT(KEYSC, 0xBE0), 943 INTC_VECT(SCIF_SCIF0, 0xC00), 944 INTC_VECT(SCIF_SCIF1, 0xC20), 945 INTC_VECT(SCIF_SCIF2, 0xC40), 946 INTC_VECT(VEU0, 0xC60), 947 INTC_VECT(MSIOF_MSIOFI0, 0xC80), 948 INTC_VECT(MSIOF_MSIOFI1, 0xCA0), 949 INTC_VECT(SPU_SPUI0, 0xCC0), 950 INTC_VECT(SPU_SPUI1, 0xCE0), 951 INTC_VECT(SCIFA4, 0xD00), 952 953 INTC_VECT(ICB, 0xD20), 954 INTC_VECT(ETHI, 0xD60), 955 956 INTC_VECT(I2C1_ALI, 0xD80), 957 INTC_VECT(I2C1_TACKI, 0xDA0), 958 INTC_VECT(I2C1_WAITI, 0xDC0), 959 INTC_VECT(I2C1_DTEI, 0xDE0), 960 961 INTC_VECT(I2C0_ALI, 0xE00), 962 INTC_VECT(I2C0_TACKI, 0xE20), 963 INTC_VECT(I2C0_WAITI, 0xE40), 964 INTC_VECT(I2C0_DTEI, 0xE60), 965 966 INTC_VECT(SDHI0, 0xE80), 967 INTC_VECT(SDHI0, 0xEA0), 968 INTC_VECT(SDHI0, 0xEC0), 969 INTC_VECT(SDHI0, 0xEE0), 970 971 INTC_VECT(CMT, 0xF00), 972 INTC_VECT(TSIF, 0xF20), 973 INTC_VECT(FSI, 0xF80), 974 INTC_VECT(SCIFA5, 0xFA0), 975 976 INTC_VECT(TMU0_TUNI0, 0x400), 977 INTC_VECT(TMU0_TUNI1, 0x420), 978 INTC_VECT(TMU0_TUNI2, 0x440), 979 980 INTC_VECT(IRDA, 0x480), 981 982 INTC_VECT(SDHI1, 0x4E0), 983 INTC_VECT(SDHI1, 0x500), 984 INTC_VECT(SDHI1, 0x520), 985 986 INTC_VECT(JPU, 0x560), 987 INTC_VECT(_2DDMAC, 0x4A0), 988 989 INTC_VECT(MMC_MMC2I, 0x5A0), 990 INTC_VECT(MMC_MMC3I, 0x5C0), 991 992 INTC_VECT(LCDC, 0xF40), 993 994 INTC_VECT(TMU1_TUNI0, 0x920), 995 INTC_VECT(TMU1_TUNI1, 0x940), 996 INTC_VECT(TMU1_TUNI2, 0x960), 997 }; 998 999 static struct intc_group groups[] __initdata = { 1000 INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3), 1001 INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI), 1002 INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3), 1003 INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU), 1004 INTC_GROUP(USB, USB0, USB1), 1005 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 1006 INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR), 1007 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR), 1008 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI), 1009 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI), 1010 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1), 1011 INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I), 1012 }; 1013 1014 static struct intc_mask_reg mask_registers[] __initdata = { 1015 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 1016 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, 1017 0, ENABLED, ENABLED, ENABLED } }, 1018 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 1019 { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0, 1020 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } }, 1021 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 1022 { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } }, 1023 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 1024 { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0, 1025 SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } }, 1026 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 1027 { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0, 1028 JPU, 0, 0, LCDC } }, 1029 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 1030 { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4, 1031 VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } }, 1032 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 1033 { 0, 0, ICB, SCIFA4, 1034 CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } }, 1035 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 1036 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, 1037 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } }, 1038 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 1039 { DISABLED, ENABLED, ENABLED, ENABLED, 1040 0, 0, SCIFA5, FSI } }, 1041 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 1042 { 0, 0, 0, CMT, 0, USB1, USB0, 0 } }, 1043 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 1044 { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4, 1045 0, RTC_CUI, RTC_PRI, RTC_ATI } }, 1046 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 1047 { 0, _2DG_CEI, _2DG_INI, _2DG_TRI, 1048 0, TPU, 0, TSIF } }, 1049 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */ 1050 { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } }, 1051 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 1052 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1053 }; 1054 1055 static struct intc_prio_reg prio_registers[] __initdata = { 1056 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, 1057 TMU0_TUNI2, IRDA } }, 1058 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } }, 1059 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, 1060 TMU1_TUNI2, SPU } }, 1061 { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } }, 1062 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } }, 1063 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } }, 1064 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, 1065 SCIF_SCIF2, VEU0 } }, 1066 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1, 1067 I2C1, I2C0 } }, 1068 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } }, 1069 { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } }, 1070 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } }, 1071 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } }, 1072 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 1073 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1074 }; 1075 1076 static struct intc_sense_reg sense_registers[] __initdata = { 1077 { 0xa414001c, 16, 2, /* ICR1 */ 1078 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1079 }; 1080 1081 static struct intc_mask_reg ack_registers[] __initdata = { 1082 { 0xa4140024, 0, 8, /* INTREQ00 */ 1083 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1084 }; 1085 1086 static struct intc_desc intc_desc __initdata = { 1087 .name = "sh7724", 1088 .force_enable = ENABLED, 1089 .force_disable = DISABLED, 1090 .hw = INTC_HW_DESC(vectors, groups, mask_registers, 1091 prio_registers, sense_registers, ack_registers), 1092 }; 1093 1094 void __init plat_irq_setup(void) 1095 { 1096 register_intc_controller(&intc_desc); 1097 } 1098 1099 static struct { 1100 /* BSC */ 1101 unsigned long mmselr; 1102 unsigned long cs0bcr; 1103 unsigned long cs4bcr; 1104 unsigned long cs5abcr; 1105 unsigned long cs5bbcr; 1106 unsigned long cs6abcr; 1107 unsigned long cs6bbcr; 1108 unsigned long cs4wcr; 1109 unsigned long cs5awcr; 1110 unsigned long cs5bwcr; 1111 unsigned long cs6awcr; 1112 unsigned long cs6bwcr; 1113 /* INTC */ 1114 unsigned short ipra; 1115 unsigned short iprb; 1116 unsigned short iprc; 1117 unsigned short iprd; 1118 unsigned short ipre; 1119 unsigned short iprf; 1120 unsigned short iprg; 1121 unsigned short iprh; 1122 unsigned short ipri; 1123 unsigned short iprj; 1124 unsigned short iprk; 1125 unsigned short iprl; 1126 unsigned char imr0; 1127 unsigned char imr1; 1128 unsigned char imr2; 1129 unsigned char imr3; 1130 unsigned char imr4; 1131 unsigned char imr5; 1132 unsigned char imr6; 1133 unsigned char imr7; 1134 unsigned char imr8; 1135 unsigned char imr9; 1136 unsigned char imr10; 1137 unsigned char imr11; 1138 unsigned char imr12; 1139 /* RWDT */ 1140 unsigned short rwtcnt; 1141 unsigned short rwtcsr; 1142 /* CPG */ 1143 unsigned long irdaclk; 1144 unsigned long spuclk; 1145 } sh7724_rstandby_state; 1146 1147 static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb, 1148 unsigned long flags, void *unused) 1149 { 1150 if (!(flags & SUSP_SH_RSTANDBY)) 1151 return NOTIFY_DONE; 1152 1153 /* BCR */ 1154 sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */ 1155 sh7724_rstandby_state.mmselr |= 0xa5a50000; 1156 sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */ 1157 sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */ 1158 sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */ 1159 sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */ 1160 sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */ 1161 sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */ 1162 sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */ 1163 sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */ 1164 sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */ 1165 sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */ 1166 sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */ 1167 1168 /* INTC */ 1169 sh7724_rstandby_state.ipra = __raw_readw(0xa4080000); /* IPRA */ 1170 sh7724_rstandby_state.iprb = __raw_readw(0xa4080004); /* IPRB */ 1171 sh7724_rstandby_state.iprc = __raw_readw(0xa4080008); /* IPRC */ 1172 sh7724_rstandby_state.iprd = __raw_readw(0xa408000c); /* IPRD */ 1173 sh7724_rstandby_state.ipre = __raw_readw(0xa4080010); /* IPRE */ 1174 sh7724_rstandby_state.iprf = __raw_readw(0xa4080014); /* IPRF */ 1175 sh7724_rstandby_state.iprg = __raw_readw(0xa4080018); /* IPRG */ 1176 sh7724_rstandby_state.iprh = __raw_readw(0xa408001c); /* IPRH */ 1177 sh7724_rstandby_state.ipri = __raw_readw(0xa4080020); /* IPRI */ 1178 sh7724_rstandby_state.iprj = __raw_readw(0xa4080024); /* IPRJ */ 1179 sh7724_rstandby_state.iprk = __raw_readw(0xa4080028); /* IPRK */ 1180 sh7724_rstandby_state.iprl = __raw_readw(0xa408002c); /* IPRL */ 1181 sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */ 1182 sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */ 1183 sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */ 1184 sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */ 1185 sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */ 1186 sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */ 1187 sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */ 1188 sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */ 1189 sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */ 1190 sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */ 1191 sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */ 1192 sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */ 1193 sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */ 1194 1195 /* RWDT */ 1196 sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */ 1197 sh7724_rstandby_state.rwtcnt |= 0x5a00; 1198 sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */ 1199 sh7724_rstandby_state.rwtcsr |= 0xa500; 1200 __raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004); 1201 1202 /* CPG */ 1203 sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */ 1204 sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */ 1205 1206 return NOTIFY_DONE; 1207 } 1208 1209 static int sh7724_post_sleep_notifier_call(struct notifier_block *nb, 1210 unsigned long flags, void *unused) 1211 { 1212 if (!(flags & SUSP_SH_RSTANDBY)) 1213 return NOTIFY_DONE; 1214 1215 /* BCR */ 1216 __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */ 1217 __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */ 1218 __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */ 1219 __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */ 1220 __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */ 1221 __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */ 1222 __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */ 1223 __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */ 1224 __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */ 1225 __raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */ 1226 __raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */ 1227 __raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */ 1228 1229 /* INTC */ 1230 __raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */ 1231 __raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */ 1232 __raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */ 1233 __raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */ 1234 __raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */ 1235 __raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */ 1236 __raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */ 1237 __raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */ 1238 __raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */ 1239 __raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */ 1240 __raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */ 1241 __raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */ 1242 __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */ 1243 __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */ 1244 __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */ 1245 __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */ 1246 __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */ 1247 __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */ 1248 __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */ 1249 __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */ 1250 __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */ 1251 __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */ 1252 __raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8); /* IMR10 */ 1253 __raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac); /* IMR11 */ 1254 __raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0); /* IMR12 */ 1255 1256 /* RWDT */ 1257 __raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */ 1258 __raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */ 1259 1260 /* CPG */ 1261 __raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018); /* IRDACLKCR */ 1262 __raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c); /* SPUCLKCR */ 1263 1264 return NOTIFY_DONE; 1265 } 1266 1267 static struct notifier_block sh7724_pre_sleep_notifier = { 1268 .notifier_call = sh7724_pre_sleep_notifier_call, 1269 .priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU), 1270 }; 1271 1272 static struct notifier_block sh7724_post_sleep_notifier = { 1273 .notifier_call = sh7724_post_sleep_notifier_call, 1274 .priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU), 1275 }; 1276 1277 static int __init sh7724_sleep_setup(void) 1278 { 1279 atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list, 1280 &sh7724_pre_sleep_notifier); 1281 1282 atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list, 1283 &sh7724_post_sleep_notifier); 1284 return 0; 1285 } 1286 arch_initcall(sh7724_sleep_setup); 1287 1288