1 /* 2 * SH7723 Setup 3 * 4 * Copyright (C) 2008 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/mm.h> 14 #include <linux/serial_sci.h> 15 #include <linux/uio_driver.h> 16 #include <linux/sh_cmt.h> 17 #include <asm/clock.h> 18 #include <asm/mmzone.h> 19 20 static struct uio_info vpu_platform_data = { 21 .name = "VPU5", 22 .version = "0", 23 .irq = 60, 24 }; 25 26 static struct resource vpu_resources[] = { 27 [0] = { 28 .name = "VPU", 29 .start = 0xfe900000, 30 .end = 0xfe902807, 31 .flags = IORESOURCE_MEM, 32 }, 33 [1] = { 34 /* place holder for contiguous memory */ 35 }, 36 }; 37 38 static struct platform_device vpu_device = { 39 .name = "uio_pdrv_genirq", 40 .id = 0, 41 .dev = { 42 .platform_data = &vpu_platform_data, 43 }, 44 .resource = vpu_resources, 45 .num_resources = ARRAY_SIZE(vpu_resources), 46 }; 47 48 static struct uio_info veu0_platform_data = { 49 .name = "VEU2H", 50 .version = "0", 51 .irq = 54, 52 }; 53 54 static struct resource veu0_resources[] = { 55 [0] = { 56 .name = "VEU2H0", 57 .start = 0xfe920000, 58 .end = 0xfe92027b, 59 .flags = IORESOURCE_MEM, 60 }, 61 [1] = { 62 /* place holder for contiguous memory */ 63 }, 64 }; 65 66 static struct platform_device veu0_device = { 67 .name = "uio_pdrv_genirq", 68 .id = 1, 69 .dev = { 70 .platform_data = &veu0_platform_data, 71 }, 72 .resource = veu0_resources, 73 .num_resources = ARRAY_SIZE(veu0_resources), 74 }; 75 76 static struct uio_info veu1_platform_data = { 77 .name = "VEU2H", 78 .version = "0", 79 .irq = 27, 80 }; 81 82 static struct resource veu1_resources[] = { 83 [0] = { 84 .name = "VEU2H1", 85 .start = 0xfe924000, 86 .end = 0xfe92427b, 87 .flags = IORESOURCE_MEM, 88 }, 89 [1] = { 90 /* place holder for contiguous memory */ 91 }, 92 }; 93 94 static struct platform_device veu1_device = { 95 .name = "uio_pdrv_genirq", 96 .id = 2, 97 .dev = { 98 .platform_data = &veu1_platform_data, 99 }, 100 .resource = veu1_resources, 101 .num_resources = ARRAY_SIZE(veu1_resources), 102 }; 103 104 static struct sh_cmt_config cmt_platform_data = { 105 .name = "CMT", 106 .channel_offset = 0x60, 107 .timer_bit = 5, 108 .clk = "cmt0", 109 .clockevent_rating = 125, 110 .clocksource_rating = 200, 111 }; 112 113 static struct resource cmt_resources[] = { 114 [0] = { 115 .name = "CMT", 116 .start = 0x044a0060, 117 .end = 0x044a006b, 118 .flags = IORESOURCE_MEM, 119 }, 120 [1] = { 121 .start = 104, 122 .flags = IORESOURCE_IRQ, 123 }, 124 }; 125 126 static struct platform_device cmt_device = { 127 .name = "sh_cmt", 128 .id = 0, 129 .dev = { 130 .platform_data = &cmt_platform_data, 131 }, 132 .resource = cmt_resources, 133 .num_resources = ARRAY_SIZE(cmt_resources), 134 }; 135 136 static struct plat_sci_port sci_platform_data[] = { 137 { 138 .mapbase = 0xffe00000, 139 .flags = UPF_BOOT_AUTOCONF, 140 .type = PORT_SCIF, 141 .irqs = { 80, 80, 80, 80 }, 142 },{ 143 .mapbase = 0xffe10000, 144 .flags = UPF_BOOT_AUTOCONF, 145 .type = PORT_SCIF, 146 .irqs = { 81, 81, 81, 81 }, 147 },{ 148 .mapbase = 0xffe20000, 149 .flags = UPF_BOOT_AUTOCONF, 150 .type = PORT_SCIF, 151 .irqs = { 82, 82, 82, 82 }, 152 },{ 153 .mapbase = 0xa4e30000, 154 .flags = UPF_BOOT_AUTOCONF, 155 .type = PORT_SCIFA, 156 .irqs = { 56, 56, 56, 56 }, 157 },{ 158 .mapbase = 0xa4e40000, 159 .flags = UPF_BOOT_AUTOCONF, 160 .type = PORT_SCIFA, 161 .irqs = { 88, 88, 88, 88 }, 162 },{ 163 .mapbase = 0xa4e50000, 164 .flags = UPF_BOOT_AUTOCONF, 165 .type = PORT_SCIFA, 166 .irqs = { 109, 109, 109, 109 }, 167 }, { 168 .flags = 0, 169 } 170 }; 171 172 static struct platform_device sci_device = { 173 .name = "sh-sci", 174 .id = -1, 175 .dev = { 176 .platform_data = sci_platform_data, 177 }, 178 }; 179 180 static struct resource rtc_resources[] = { 181 [0] = { 182 .start = 0xa465fec0, 183 .end = 0xa465fec0 + 0x58 - 1, 184 .flags = IORESOURCE_IO, 185 }, 186 [1] = { 187 /* Period IRQ */ 188 .start = 69, 189 .flags = IORESOURCE_IRQ, 190 }, 191 [2] = { 192 /* Carry IRQ */ 193 .start = 70, 194 .flags = IORESOURCE_IRQ, 195 }, 196 [3] = { 197 /* Alarm IRQ */ 198 .start = 68, 199 .flags = IORESOURCE_IRQ, 200 }, 201 }; 202 203 static struct platform_device rtc_device = { 204 .name = "sh-rtc", 205 .id = -1, 206 .num_resources = ARRAY_SIZE(rtc_resources), 207 .resource = rtc_resources, 208 }; 209 210 static struct resource sh7723_usb_host_resources[] = { 211 [0] = { 212 .name = "r8a66597_hcd", 213 .start = 0xa4d80000, 214 .end = 0xa4d800ff, 215 .flags = IORESOURCE_MEM, 216 }, 217 [1] = { 218 .start = 65, 219 .end = 65, 220 .flags = IORESOURCE_IRQ, 221 }, 222 }; 223 224 static struct platform_device sh7723_usb_host_device = { 225 .name = "r8a66597_hcd", 226 .id = 0, 227 .dev = { 228 .dma_mask = NULL, /* not use dma */ 229 .coherent_dma_mask = 0xffffffff, 230 }, 231 .num_resources = ARRAY_SIZE(sh7723_usb_host_resources), 232 .resource = sh7723_usb_host_resources, 233 }; 234 235 static struct resource iic_resources[] = { 236 [0] = { 237 .name = "IIC", 238 .start = 0x04470000, 239 .end = 0x04470017, 240 .flags = IORESOURCE_MEM, 241 }, 242 [1] = { 243 .start = 96, 244 .end = 99, 245 .flags = IORESOURCE_IRQ, 246 }, 247 }; 248 249 static struct platform_device iic_device = { 250 .name = "i2c-sh_mobile", 251 .id = 0, /* "i2c0" clock */ 252 .num_resources = ARRAY_SIZE(iic_resources), 253 .resource = iic_resources, 254 }; 255 256 static struct platform_device *sh7723_devices[] __initdata = { 257 &cmt_device, 258 &sci_device, 259 &rtc_device, 260 &iic_device, 261 &sh7723_usb_host_device, 262 &vpu_device, 263 &veu0_device, 264 &veu1_device, 265 }; 266 267 static int __init sh7723_devices_setup(void) 268 { 269 clk_always_enable("meram0"); /* MERAM */ 270 clk_always_enable("rtc0"); /* RTC */ 271 clk_always_enable("veu1"); /* VEU2H1 */ 272 clk_always_enable("veu0"); /* VEU2H0 */ 273 clk_always_enable("vpu0"); /* VPU */ 274 275 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 276 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 277 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 278 279 return platform_add_devices(sh7723_devices, 280 ARRAY_SIZE(sh7723_devices)); 281 } 282 __initcall(sh7723_devices_setup); 283 284 enum { 285 UNUSED=0, 286 287 /* interrupt sources */ 288 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 289 HUDI, 290 DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3, 291 _2DG_TRI,_2DG_INI,_2DG_CEI, 292 DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3, 293 VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI, 294 SCIFA_SCIFA0, 295 VPU_VPUI, 296 TPU_TPUI, 297 ADC_ADI, 298 USB_USI0, 299 RTC_ATI,RTC_PRI,RTC_CUI, 300 DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR, 301 DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR, 302 KEYSC_KEYI, 303 SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2, 304 MSIOF_MSIOFI0,MSIOF_MSIOFI1, 305 SCIFA_SCIFA1, 306 FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I, 307 I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI, 308 SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2, 309 CMT_CMTI, 310 TSIF_TSIFI, 311 SIU_SIUI, 312 SCIFA_SCIFA2, 313 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, 314 IRDA_IRDAI, 315 ATAPI_ATAPII, 316 SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2, 317 VEU2H1_VEU2HI, 318 LCDC_LCDCI, 319 TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2, 320 321 /* interrupt groups */ 322 DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG, 323 SDHI1, RTC, DMAC1B, SDHI0, 324 }; 325 326 static struct intc_vect vectors[] __initdata = { 327 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 328 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 329 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 330 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 331 332 INTC_VECT(DMAC1A_DEI0,0x700), 333 INTC_VECT(DMAC1A_DEI1,0x720), 334 INTC_VECT(DMAC1A_DEI2,0x740), 335 INTC_VECT(DMAC1A_DEI3,0x760), 336 337 INTC_VECT(_2DG_TRI, 0x780), 338 INTC_VECT(_2DG_INI, 0x7A0), 339 INTC_VECT(_2DG_CEI, 0x7C0), 340 341 INTC_VECT(DMAC0A_DEI0,0x800), 342 INTC_VECT(DMAC0A_DEI1,0x820), 343 INTC_VECT(DMAC0A_DEI2,0x840), 344 INTC_VECT(DMAC0A_DEI3,0x860), 345 346 INTC_VECT(VIO_CEUI,0x880), 347 INTC_VECT(VIO_BEUI,0x8A0), 348 INTC_VECT(VIO_VEU2HI,0x8C0), 349 INTC_VECT(VIO_VOUI,0x8E0), 350 351 INTC_VECT(SCIFA_SCIFA0,0x900), 352 INTC_VECT(VPU_VPUI,0x980), 353 INTC_VECT(TPU_TPUI,0x9A0), 354 INTC_VECT(ADC_ADI,0x9E0), 355 INTC_VECT(USB_USI0,0xA20), 356 357 INTC_VECT(RTC_ATI,0xA80), 358 INTC_VECT(RTC_PRI,0xAA0), 359 INTC_VECT(RTC_CUI,0xAC0), 360 361 INTC_VECT(DMAC1B_DEI4,0xB00), 362 INTC_VECT(DMAC1B_DEI5,0xB20), 363 INTC_VECT(DMAC1B_DADERR,0xB40), 364 365 INTC_VECT(DMAC0B_DEI4,0xB80), 366 INTC_VECT(DMAC0B_DEI5,0xBA0), 367 INTC_VECT(DMAC0B_DADERR,0xBC0), 368 369 INTC_VECT(KEYSC_KEYI,0xBE0), 370 INTC_VECT(SCIF_SCIF0,0xC00), 371 INTC_VECT(SCIF_SCIF1,0xC20), 372 INTC_VECT(SCIF_SCIF2,0xC40), 373 INTC_VECT(MSIOF_MSIOFI0,0xC80), 374 INTC_VECT(MSIOF_MSIOFI1,0xCA0), 375 INTC_VECT(SCIFA_SCIFA1,0xD00), 376 377 INTC_VECT(FLCTL_FLSTEI,0xD80), 378 INTC_VECT(FLCTL_FLTENDI,0xDA0), 379 INTC_VECT(FLCTL_FLTREQ0I,0xDC0), 380 INTC_VECT(FLCTL_FLTREQ1I,0xDE0), 381 382 INTC_VECT(I2C_ALI,0xE00), 383 INTC_VECT(I2C_TACKI,0xE20), 384 INTC_VECT(I2C_WAITI,0xE40), 385 INTC_VECT(I2C_DTEI,0xE60), 386 387 INTC_VECT(SDHI0_SDHII0,0xE80), 388 INTC_VECT(SDHI0_SDHII1,0xEA0), 389 INTC_VECT(SDHI0_SDHII2,0xEC0), 390 391 INTC_VECT(CMT_CMTI,0xF00), 392 INTC_VECT(TSIF_TSIFI,0xF20), 393 INTC_VECT(SIU_SIUI,0xF80), 394 INTC_VECT(SCIFA_SCIFA2,0xFA0), 395 396 INTC_VECT(TMU0_TUNI0,0x400), 397 INTC_VECT(TMU0_TUNI1,0x420), 398 INTC_VECT(TMU0_TUNI2,0x440), 399 400 INTC_VECT(IRDA_IRDAI,0x480), 401 INTC_VECT(ATAPI_ATAPII,0x4A0), 402 403 INTC_VECT(SDHI1_SDHII0,0x4E0), 404 INTC_VECT(SDHI1_SDHII1,0x500), 405 INTC_VECT(SDHI1_SDHII2,0x520), 406 407 INTC_VECT(VEU2H1_VEU2HI,0x560), 408 INTC_VECT(LCDC_LCDCI,0x580), 409 410 INTC_VECT(TMU1_TUNI0,0x920), 411 INTC_VECT(TMU1_TUNI1,0x940), 412 INTC_VECT(TMU1_TUNI2,0x960), 413 414 }; 415 416 static struct intc_group groups[] __initdata = { 417 INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3), 418 INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3), 419 INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI), 420 INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR), 421 INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I), 422 INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI), 423 INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI), 424 INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2), 425 INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI), 426 INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR), 427 INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2), 428 }; 429 430 static struct intc_mask_reg mask_registers[] __initdata = { 431 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 432 { 0, TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} }, 433 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 434 { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } }, 435 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 436 { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } }, 437 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 438 { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } }, 439 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 440 { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } }, 441 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 442 { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } }, 443 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 444 { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } }, 445 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 446 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 447 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, 448 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 449 { 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } }, 450 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 451 { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } }, 452 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 453 { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } }, 454 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 455 { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } }, 456 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */ 457 { 0,0,0,0,0,0,0,ATAPI_ATAPII } }, 458 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 459 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 460 }; 461 462 static struct intc_prio_reg prio_registers[] __initdata = { 463 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } }, 464 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} }, 465 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} }, 466 { 0xa408000c, 0, 16, 4, /* IPRD */ { } }, 467 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } }, 468 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } }, 469 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } }, 470 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } }, 471 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } }, 472 { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } }, 473 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } }, 474 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } }, 475 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 476 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 477 }; 478 479 static struct intc_sense_reg sense_registers[] __initdata = { 480 { 0xa414001c, 16, 2, /* ICR1 */ 481 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 482 }; 483 484 static struct intc_mask_reg ack_registers[] __initdata = { 485 { 0xa4140024, 0, 8, /* INTREQ00 */ 486 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 487 }; 488 489 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7723", vectors, groups, 490 mask_registers, prio_registers, sense_registers, 491 ack_registers); 492 493 void __init plat_irq_setup(void) 494 { 495 register_intc_controller(&intc_desc); 496 } 497