1 /*
2  * SH7723 Setup
3  *
4  *  Copyright (C) 2008  Paul Mundt
5  *
6  * This file is subject to the terms and conditions of the GNU General Public
7  * License.  See the file "COPYING" in the main directory of this archive
8  * for more details.
9  */
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/mm.h>
14 #include <linux/serial_sci.h>
15 #include <linux/uio_driver.h>
16 #include <linux/usb/r8a66597.h>
17 #include <linux/sh_timer.h>
18 #include <linux/io.h>
19 #include <asm/clock.h>
20 #include <asm/mmzone.h>
21 #include <cpu/sh7723.h>
22 
23 /* Serial */
24 static struct plat_sci_port scif0_platform_data = {
25 	.mapbase        = 0xffe00000,
26 	.port_reg	= 0xa4050160,
27 	.flags          = UPF_BOOT_AUTOCONF,
28 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
29 	.scbrr_algo_id	= SCBRR_ALGO_2,
30 	.type           = PORT_SCIF,
31 	.irqs           = { 80, 80, 80, 80 },
32 	.regtype	= SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
33 };
34 
35 static struct platform_device scif0_device = {
36 	.name		= "sh-sci",
37 	.id		= 0,
38 	.dev		= {
39 		.platform_data	= &scif0_platform_data,
40 	},
41 };
42 
43 static struct plat_sci_port scif1_platform_data = {
44 	.mapbase        = 0xffe10000,
45 	.port_reg	= SCIx_NOT_SUPPORTED,
46 	.flags          = UPF_BOOT_AUTOCONF,
47 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
48 	.scbrr_algo_id	= SCBRR_ALGO_2,
49 	.type           = PORT_SCIF,
50 	.irqs           = { 81, 81, 81, 81 },
51 	.regtype	= SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
52 };
53 
54 static struct platform_device scif1_device = {
55 	.name		= "sh-sci",
56 	.id		= 1,
57 	.dev		= {
58 		.platform_data	= &scif1_platform_data,
59 	},
60 };
61 
62 static struct plat_sci_port scif2_platform_data = {
63 	.mapbase        = 0xffe20000,
64 	.port_reg	= SCIx_NOT_SUPPORTED,
65 	.flags          = UPF_BOOT_AUTOCONF,
66 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
67 	.scbrr_algo_id	= SCBRR_ALGO_2,
68 	.type           = PORT_SCIF,
69 	.irqs           = { 82, 82, 82, 82 },
70 	.regtype	= SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
71 };
72 
73 static struct platform_device scif2_device = {
74 	.name		= "sh-sci",
75 	.id		= 2,
76 	.dev		= {
77 		.platform_data	= &scif2_platform_data,
78 	},
79 };
80 
81 static struct plat_sci_port scif3_platform_data = {
82 	.mapbase        = 0xa4e30000,
83 	.flags          = UPF_BOOT_AUTOCONF,
84 	.port_reg	= SCIx_NOT_SUPPORTED,
85 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
86 	.scbrr_algo_id	= SCBRR_ALGO_3,
87 	.type           = PORT_SCIFA,
88 	.irqs           = { 56, 56, 56, 56 },
89 };
90 
91 static struct platform_device scif3_device = {
92 	.name		= "sh-sci",
93 	.id		= 3,
94 	.dev		= {
95 		.platform_data	= &scif3_platform_data,
96 	},
97 };
98 
99 static struct plat_sci_port scif4_platform_data = {
100 	.mapbase        = 0xa4e40000,
101 	.port_reg	= SCIx_NOT_SUPPORTED,
102 	.flags          = UPF_BOOT_AUTOCONF,
103 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
104 	.scbrr_algo_id	= SCBRR_ALGO_3,
105 	.type           = PORT_SCIFA,
106 	.irqs           = { 88, 88, 88, 88 },
107 };
108 
109 static struct platform_device scif4_device = {
110 	.name		= "sh-sci",
111 	.id		= 4,
112 	.dev		= {
113 		.platform_data	= &scif4_platform_data,
114 	},
115 };
116 
117 static struct plat_sci_port scif5_platform_data = {
118 	.mapbase        = 0xa4e50000,
119 	.port_reg	= SCIx_NOT_SUPPORTED,
120 	.flags          = UPF_BOOT_AUTOCONF,
121 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
122 	.scbrr_algo_id	= SCBRR_ALGO_3,
123 	.type           = PORT_SCIFA,
124 	.irqs           = { 109, 109, 109, 109 },
125 };
126 
127 static struct platform_device scif5_device = {
128 	.name		= "sh-sci",
129 	.id		= 5,
130 	.dev		= {
131 		.platform_data	= &scif5_platform_data,
132 	},
133 };
134 
135 static struct uio_info vpu_platform_data = {
136 	.name = "VPU5",
137 	.version = "0",
138 	.irq = 60,
139 };
140 
141 static struct resource vpu_resources[] = {
142 	[0] = {
143 		.name	= "VPU",
144 		.start	= 0xfe900000,
145 		.end	= 0xfe902807,
146 		.flags	= IORESOURCE_MEM,
147 	},
148 	[1] = {
149 		/* place holder for contiguous memory */
150 	},
151 };
152 
153 static struct platform_device vpu_device = {
154 	.name		= "uio_pdrv_genirq",
155 	.id		= 0,
156 	.dev = {
157 		.platform_data	= &vpu_platform_data,
158 	},
159 	.resource	= vpu_resources,
160 	.num_resources	= ARRAY_SIZE(vpu_resources),
161 	.archdata = {
162 		.hwblk_id = HWBLK_VPU,
163 	},
164 };
165 
166 static struct uio_info veu0_platform_data = {
167 	.name = "VEU2H",
168 	.version = "0",
169 	.irq = 54,
170 };
171 
172 static struct resource veu0_resources[] = {
173 	[0] = {
174 		.name	= "VEU2H0",
175 		.start	= 0xfe920000,
176 		.end	= 0xfe92027b,
177 		.flags	= IORESOURCE_MEM,
178 	},
179 	[1] = {
180 		/* place holder for contiguous memory */
181 	},
182 };
183 
184 static struct platform_device veu0_device = {
185 	.name		= "uio_pdrv_genirq",
186 	.id		= 1,
187 	.dev = {
188 		.platform_data	= &veu0_platform_data,
189 	},
190 	.resource	= veu0_resources,
191 	.num_resources	= ARRAY_SIZE(veu0_resources),
192 	.archdata = {
193 		.hwblk_id = HWBLK_VEU2H0,
194 	},
195 };
196 
197 static struct uio_info veu1_platform_data = {
198 	.name = "VEU2H",
199 	.version = "0",
200 	.irq = 27,
201 };
202 
203 static struct resource veu1_resources[] = {
204 	[0] = {
205 		.name	= "VEU2H1",
206 		.start	= 0xfe924000,
207 		.end	= 0xfe92427b,
208 		.flags	= IORESOURCE_MEM,
209 	},
210 	[1] = {
211 		/* place holder for contiguous memory */
212 	},
213 };
214 
215 static struct platform_device veu1_device = {
216 	.name		= "uio_pdrv_genirq",
217 	.id		= 2,
218 	.dev = {
219 		.platform_data	= &veu1_platform_data,
220 	},
221 	.resource	= veu1_resources,
222 	.num_resources	= ARRAY_SIZE(veu1_resources),
223 	.archdata = {
224 		.hwblk_id = HWBLK_VEU2H1,
225 	},
226 };
227 
228 static struct sh_timer_config cmt_platform_data = {
229 	.channel_offset = 0x60,
230 	.timer_bit = 5,
231 	.clockevent_rating = 125,
232 	.clocksource_rating = 125,
233 };
234 
235 static struct resource cmt_resources[] = {
236 	[0] = {
237 		.start	= 0x044a0060,
238 		.end	= 0x044a006b,
239 		.flags	= IORESOURCE_MEM,
240 	},
241 	[1] = {
242 		.start	= 104,
243 		.flags	= IORESOURCE_IRQ,
244 	},
245 };
246 
247 static struct platform_device cmt_device = {
248 	.name		= "sh_cmt",
249 	.id		= 0,
250 	.dev = {
251 		.platform_data	= &cmt_platform_data,
252 	},
253 	.resource	= cmt_resources,
254 	.num_resources	= ARRAY_SIZE(cmt_resources),
255 	.archdata = {
256 		.hwblk_id = HWBLK_CMT,
257 	},
258 };
259 
260 static struct sh_timer_config tmu0_platform_data = {
261 	.channel_offset = 0x04,
262 	.timer_bit = 0,
263 	.clockevent_rating = 200,
264 };
265 
266 static struct resource tmu0_resources[] = {
267 	[0] = {
268 		.start	= 0xffd80008,
269 		.end	= 0xffd80013,
270 		.flags	= IORESOURCE_MEM,
271 	},
272 	[1] = {
273 		.start	= 16,
274 		.flags	= IORESOURCE_IRQ,
275 	},
276 };
277 
278 static struct platform_device tmu0_device = {
279 	.name		= "sh_tmu",
280 	.id		= 0,
281 	.dev = {
282 		.platform_data	= &tmu0_platform_data,
283 	},
284 	.resource	= tmu0_resources,
285 	.num_resources	= ARRAY_SIZE(tmu0_resources),
286 	.archdata = {
287 		.hwblk_id = HWBLK_TMU0,
288 	},
289 };
290 
291 static struct sh_timer_config tmu1_platform_data = {
292 	.channel_offset = 0x10,
293 	.timer_bit = 1,
294 	.clocksource_rating = 200,
295 };
296 
297 static struct resource tmu1_resources[] = {
298 	[0] = {
299 		.start	= 0xffd80014,
300 		.end	= 0xffd8001f,
301 		.flags	= IORESOURCE_MEM,
302 	},
303 	[1] = {
304 		.start	= 17,
305 		.flags	= IORESOURCE_IRQ,
306 	},
307 };
308 
309 static struct platform_device tmu1_device = {
310 	.name		= "sh_tmu",
311 	.id		= 1,
312 	.dev = {
313 		.platform_data	= &tmu1_platform_data,
314 	},
315 	.resource	= tmu1_resources,
316 	.num_resources	= ARRAY_SIZE(tmu1_resources),
317 	.archdata = {
318 		.hwblk_id = HWBLK_TMU0,
319 	},
320 };
321 
322 static struct sh_timer_config tmu2_platform_data = {
323 	.channel_offset = 0x1c,
324 	.timer_bit = 2,
325 };
326 
327 static struct resource tmu2_resources[] = {
328 	[0] = {
329 		.start	= 0xffd80020,
330 		.end	= 0xffd8002b,
331 		.flags	= IORESOURCE_MEM,
332 	},
333 	[1] = {
334 		.start	= 18,
335 		.flags	= IORESOURCE_IRQ,
336 	},
337 };
338 
339 static struct platform_device tmu2_device = {
340 	.name		= "sh_tmu",
341 	.id		= 2,
342 	.dev = {
343 		.platform_data	= &tmu2_platform_data,
344 	},
345 	.resource	= tmu2_resources,
346 	.num_resources	= ARRAY_SIZE(tmu2_resources),
347 	.archdata = {
348 		.hwblk_id = HWBLK_TMU0,
349 	},
350 };
351 
352 static struct sh_timer_config tmu3_platform_data = {
353 	.channel_offset = 0x04,
354 	.timer_bit = 0,
355 };
356 
357 static struct resource tmu3_resources[] = {
358 	[0] = {
359 		.start	= 0xffd90008,
360 		.end	= 0xffd90013,
361 		.flags	= IORESOURCE_MEM,
362 	},
363 	[1] = {
364 		.start	= 57,
365 		.flags	= IORESOURCE_IRQ,
366 	},
367 };
368 
369 static struct platform_device tmu3_device = {
370 	.name		= "sh_tmu",
371 	.id		= 3,
372 	.dev = {
373 		.platform_data	= &tmu3_platform_data,
374 	},
375 	.resource	= tmu3_resources,
376 	.num_resources	= ARRAY_SIZE(tmu3_resources),
377 	.archdata = {
378 		.hwblk_id = HWBLK_TMU1,
379 	},
380 };
381 
382 static struct sh_timer_config tmu4_platform_data = {
383 	.channel_offset = 0x10,
384 	.timer_bit = 1,
385 };
386 
387 static struct resource tmu4_resources[] = {
388 	[0] = {
389 		.start	= 0xffd90014,
390 		.end	= 0xffd9001f,
391 		.flags	= IORESOURCE_MEM,
392 	},
393 	[1] = {
394 		.start	= 58,
395 		.flags	= IORESOURCE_IRQ,
396 	},
397 };
398 
399 static struct platform_device tmu4_device = {
400 	.name		= "sh_tmu",
401 	.id		= 4,
402 	.dev = {
403 		.platform_data	= &tmu4_platform_data,
404 	},
405 	.resource	= tmu4_resources,
406 	.num_resources	= ARRAY_SIZE(tmu4_resources),
407 	.archdata = {
408 		.hwblk_id = HWBLK_TMU1,
409 	},
410 };
411 
412 static struct sh_timer_config tmu5_platform_data = {
413 	.channel_offset = 0x1c,
414 	.timer_bit = 2,
415 };
416 
417 static struct resource tmu5_resources[] = {
418 	[0] = {
419 		.start	= 0xffd90020,
420 		.end	= 0xffd9002b,
421 		.flags	= IORESOURCE_MEM,
422 	},
423 	[1] = {
424 		.start	= 57,
425 		.flags	= IORESOURCE_IRQ,
426 	},
427 };
428 
429 static struct platform_device tmu5_device = {
430 	.name		= "sh_tmu",
431 	.id		= 5,
432 	.dev = {
433 		.platform_data	= &tmu5_platform_data,
434 	},
435 	.resource	= tmu5_resources,
436 	.num_resources	= ARRAY_SIZE(tmu5_resources),
437 	.archdata = {
438 		.hwblk_id = HWBLK_TMU1,
439 	},
440 };
441 
442 static struct resource rtc_resources[] = {
443 	[0] = {
444 		.start	= 0xa465fec0,
445 		.end	= 0xa465fec0 + 0x58 - 1,
446 		.flags	= IORESOURCE_IO,
447 	},
448 	[1] = {
449 		/* Period IRQ */
450 		.start	= 69,
451 		.flags	= IORESOURCE_IRQ,
452 	},
453 	[2] = {
454 		/* Carry IRQ */
455 		.start	= 70,
456 		.flags	= IORESOURCE_IRQ,
457 	},
458 	[3] = {
459 		/* Alarm IRQ */
460 		.start	= 68,
461 		.flags	= IORESOURCE_IRQ,
462 	},
463 };
464 
465 static struct platform_device rtc_device = {
466 	.name		= "sh-rtc",
467 	.id		= -1,
468 	.num_resources	= ARRAY_SIZE(rtc_resources),
469 	.resource	= rtc_resources,
470 	.archdata = {
471 		.hwblk_id = HWBLK_RTC,
472 	},
473 };
474 
475 static struct r8a66597_platdata r8a66597_data = {
476 	.on_chip = 1,
477 };
478 
479 static struct resource sh7723_usb_host_resources[] = {
480 	[0] = {
481 		.start	= 0xa4d80000,
482 		.end	= 0xa4d800ff,
483 		.flags	= IORESOURCE_MEM,
484 	},
485 	[1] = {
486 		.start	= 65,
487 		.end	= 65,
488 		.flags	= IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
489 	},
490 };
491 
492 static struct platform_device sh7723_usb_host_device = {
493 	.name		= "r8a66597_hcd",
494 	.id		= 0,
495 	.dev = {
496 		.dma_mask		= NULL,         /*  not use dma */
497 		.coherent_dma_mask	= 0xffffffff,
498 		.platform_data		= &r8a66597_data,
499 	},
500 	.num_resources	= ARRAY_SIZE(sh7723_usb_host_resources),
501 	.resource	= sh7723_usb_host_resources,
502 	.archdata = {
503 		.hwblk_id = HWBLK_USB,
504 	},
505 };
506 
507 static struct resource iic_resources[] = {
508 	[0] = {
509 		.name	= "IIC",
510 		.start  = 0x04470000,
511 		.end    = 0x04470017,
512 		.flags  = IORESOURCE_MEM,
513 	},
514 	[1] = {
515 		.start  = 96,
516 		.end    = 99,
517 		.flags  = IORESOURCE_IRQ,
518        },
519 };
520 
521 static struct platform_device iic_device = {
522 	.name           = "i2c-sh_mobile",
523 	.id             = 0, /* "i2c0" clock */
524 	.num_resources  = ARRAY_SIZE(iic_resources),
525 	.resource       = iic_resources,
526 	.archdata = {
527 		.hwblk_id = HWBLK_IIC,
528 	},
529 };
530 
531 static struct platform_device *sh7723_devices[] __initdata = {
532 	&scif0_device,
533 	&scif1_device,
534 	&scif2_device,
535 	&scif3_device,
536 	&scif4_device,
537 	&scif5_device,
538 	&cmt_device,
539 	&tmu0_device,
540 	&tmu1_device,
541 	&tmu2_device,
542 	&tmu3_device,
543 	&tmu4_device,
544 	&tmu5_device,
545 	&rtc_device,
546 	&iic_device,
547 	&sh7723_usb_host_device,
548 	&vpu_device,
549 	&veu0_device,
550 	&veu1_device,
551 };
552 
553 static int __init sh7723_devices_setup(void)
554 {
555 	platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
556 	platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
557 	platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
558 
559 	return platform_add_devices(sh7723_devices,
560 				    ARRAY_SIZE(sh7723_devices));
561 }
562 arch_initcall(sh7723_devices_setup);
563 
564 static struct platform_device *sh7723_early_devices[] __initdata = {
565 	&scif0_device,
566 	&scif1_device,
567 	&scif2_device,
568 	&scif3_device,
569 	&scif4_device,
570 	&scif5_device,
571 	&cmt_device,
572 	&tmu0_device,
573 	&tmu1_device,
574 	&tmu2_device,
575 	&tmu3_device,
576 	&tmu4_device,
577 	&tmu5_device,
578 };
579 
580 void __init plat_early_device_setup(void)
581 {
582 	early_platform_add_devices(sh7723_early_devices,
583 				   ARRAY_SIZE(sh7723_early_devices));
584 }
585 
586 #define RAMCR_CACHE_L2FC	0x0002
587 #define RAMCR_CACHE_L2E		0x0001
588 #define L2_CACHE_ENABLE		(RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
589 
590 void l2_cache_init(void)
591 {
592 	/* Enable L2 cache */
593 	__raw_writel(L2_CACHE_ENABLE, RAMCR);
594 }
595 
596 enum {
597 	UNUSED=0,
598 	ENABLED,
599 	DISABLED,
600 
601 	/* interrupt sources */
602 	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
603 	HUDI,
604 	DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3,
605 	_2DG_TRI,_2DG_INI,_2DG_CEI,
606 	DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3,
607 	VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI,
608 	SCIFA_SCIFA0,
609 	VPU_VPUI,
610 	TPU_TPUI,
611 	ADC_ADI,
612 	USB_USI0,
613 	RTC_ATI,RTC_PRI,RTC_CUI,
614 	DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR,
615 	DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR,
616 	KEYSC_KEYI,
617 	SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2,
618 	MSIOF_MSIOFI0,MSIOF_MSIOFI1,
619 	SCIFA_SCIFA1,
620 	FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
621 	I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
622 	CMT_CMTI,
623 	TSIF_TSIFI,
624 	SIU_SIUI,
625 	SCIFA_SCIFA2,
626 	TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
627 	IRDA_IRDAI,
628 	ATAPI_ATAPII,
629 	VEU2H1_VEU2HI,
630 	LCDC_LCDCI,
631 	TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
632 
633 	/* interrupt groups */
634 	DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG,
635 	SDHI1, RTC, DMAC1B, SDHI0,
636 };
637 
638 static struct intc_vect vectors[] __initdata = {
639 	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
640 	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
641 	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
642 	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
643 
644 	INTC_VECT(DMAC1A_DEI0,0x700),
645 	INTC_VECT(DMAC1A_DEI1,0x720),
646 	INTC_VECT(DMAC1A_DEI2,0x740),
647 	INTC_VECT(DMAC1A_DEI3,0x760),
648 
649 	INTC_VECT(_2DG_TRI, 0x780),
650 	INTC_VECT(_2DG_INI, 0x7A0),
651 	INTC_VECT(_2DG_CEI, 0x7C0),
652 
653 	INTC_VECT(DMAC0A_DEI0,0x800),
654 	INTC_VECT(DMAC0A_DEI1,0x820),
655 	INTC_VECT(DMAC0A_DEI2,0x840),
656 	INTC_VECT(DMAC0A_DEI3,0x860),
657 
658 	INTC_VECT(VIO_CEUI,0x880),
659 	INTC_VECT(VIO_BEUI,0x8A0),
660 	INTC_VECT(VIO_VEU2HI,0x8C0),
661 	INTC_VECT(VIO_VOUI,0x8E0),
662 
663 	INTC_VECT(SCIFA_SCIFA0,0x900),
664 	INTC_VECT(VPU_VPUI,0x980),
665 	INTC_VECT(TPU_TPUI,0x9A0),
666 	INTC_VECT(ADC_ADI,0x9E0),
667 	INTC_VECT(USB_USI0,0xA20),
668 
669 	INTC_VECT(RTC_ATI,0xA80),
670 	INTC_VECT(RTC_PRI,0xAA0),
671 	INTC_VECT(RTC_CUI,0xAC0),
672 
673 	INTC_VECT(DMAC1B_DEI4,0xB00),
674 	INTC_VECT(DMAC1B_DEI5,0xB20),
675 	INTC_VECT(DMAC1B_DADERR,0xB40),
676 
677 	INTC_VECT(DMAC0B_DEI4,0xB80),
678 	INTC_VECT(DMAC0B_DEI5,0xBA0),
679 	INTC_VECT(DMAC0B_DADERR,0xBC0),
680 
681 	INTC_VECT(KEYSC_KEYI,0xBE0),
682 	INTC_VECT(SCIF_SCIF0,0xC00),
683 	INTC_VECT(SCIF_SCIF1,0xC20),
684 	INTC_VECT(SCIF_SCIF2,0xC40),
685 	INTC_VECT(MSIOF_MSIOFI0,0xC80),
686 	INTC_VECT(MSIOF_MSIOFI1,0xCA0),
687 	INTC_VECT(SCIFA_SCIFA1,0xD00),
688 
689 	INTC_VECT(FLCTL_FLSTEI,0xD80),
690 	INTC_VECT(FLCTL_FLTENDI,0xDA0),
691 	INTC_VECT(FLCTL_FLTREQ0I,0xDC0),
692 	INTC_VECT(FLCTL_FLTREQ1I,0xDE0),
693 
694 	INTC_VECT(I2C_ALI,0xE00),
695 	INTC_VECT(I2C_TACKI,0xE20),
696 	INTC_VECT(I2C_WAITI,0xE40),
697 	INTC_VECT(I2C_DTEI,0xE60),
698 
699 	INTC_VECT(SDHI0, 0xE80),
700 	INTC_VECT(SDHI0, 0xEA0),
701 	INTC_VECT(SDHI0, 0xEC0),
702 
703 	INTC_VECT(CMT_CMTI,0xF00),
704 	INTC_VECT(TSIF_TSIFI,0xF20),
705 	INTC_VECT(SIU_SIUI,0xF80),
706 	INTC_VECT(SCIFA_SCIFA2,0xFA0),
707 
708 	INTC_VECT(TMU0_TUNI0,0x400),
709 	INTC_VECT(TMU0_TUNI1,0x420),
710 	INTC_VECT(TMU0_TUNI2,0x440),
711 
712 	INTC_VECT(IRDA_IRDAI,0x480),
713 	INTC_VECT(ATAPI_ATAPII,0x4A0),
714 
715 	INTC_VECT(SDHI1, 0x4E0),
716 	INTC_VECT(SDHI1, 0x500),
717 	INTC_VECT(SDHI1, 0x520),
718 
719 	INTC_VECT(VEU2H1_VEU2HI,0x560),
720 	INTC_VECT(LCDC_LCDCI,0x580),
721 
722 	INTC_VECT(TMU1_TUNI0,0x920),
723 	INTC_VECT(TMU1_TUNI1,0x940),
724 	INTC_VECT(TMU1_TUNI2,0x960),
725 
726 };
727 
728 static struct intc_group groups[] __initdata = {
729 	INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3),
730 	INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3),
731 	INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI),
732 	INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR),
733 	INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
734 	INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
735 	INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
736 	INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
737 	INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
738 };
739 
740 static struct intc_mask_reg mask_registers[] __initdata = {
741 	{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
742 	  { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
743 	    0, ENABLED, ENABLED, ENABLED } },
744 	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
745 	  { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
746 	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
747 	  { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } },
748 	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
749 	  { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } },
750 	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
751 	  { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } },
752 	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
753 	  { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } },
754 	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
755 	  { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } },
756 	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
757 	  { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
758 	    FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
759 	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
760 	  { 0, ENABLED, ENABLED, ENABLED,
761 	    0, 0, SCIFA_SCIFA2, SIU_SIUI } },
762 	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
763 	  { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
764 	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
765 	  { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } },
766 	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
767 	  { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } },
768 	{ 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
769 	  { 0,0,0,0,0,0,0,ATAPI_ATAPII } },
770 	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
771 	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
772 };
773 
774 static struct intc_prio_reg prio_registers[] __initdata = {
775 	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } },
776 	{ 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} },
777 	{ 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} },
778 	{ 0xa408000c, 0, 16, 4, /* IPRD */ { } },
779 	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } },
780 	{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } },
781 	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } },
782 	{ 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } },
783 	{ 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } },
784 	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } },
785 	{ 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } },
786 	{ 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } },
787 	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
788 	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
789 };
790 
791 static struct intc_sense_reg sense_registers[] __initdata = {
792 	{ 0xa414001c, 16, 2, /* ICR1 */
793 	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
794 };
795 
796 static struct intc_mask_reg ack_registers[] __initdata = {
797 	{ 0xa4140024, 0, 8, /* INTREQ00 */
798 	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
799 };
800 
801 static struct intc_desc intc_desc __initdata = {
802 	.name = "sh7723",
803 	.force_enable = ENABLED,
804 	.force_disable = DISABLED,
805 	.hw = INTC_HW_DESC(vectors, groups, mask_registers,
806 			   prio_registers, sense_registers, ack_registers),
807 };
808 
809 void __init plat_irq_setup(void)
810 {
811 	register_intc_controller(&intc_desc);
812 }
813