1 /* 2 * SH7723 Setup 3 * 4 * Copyright (C) 2008 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/mm.h> 14 #include <linux/serial_sci.h> 15 #include <linux/uio_driver.h> 16 #include <linux/usb/r8a66597.h> 17 #include <linux/sh_timer.h> 18 #include <linux/sh_intc.h> 19 #include <linux/io.h> 20 #include <asm/clock.h> 21 #include <asm/mmzone.h> 22 #include <cpu/sh7723.h> 23 24 /* Serial */ 25 static struct plat_sci_port scif0_platform_data = { 26 .mapbase = 0xffe00000, 27 .port_reg = 0xa4050160, 28 .flags = UPF_BOOT_AUTOCONF, 29 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 30 .scbrr_algo_id = SCBRR_ALGO_2, 31 .type = PORT_SCIF, 32 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), 33 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 34 }; 35 36 static struct platform_device scif0_device = { 37 .name = "sh-sci", 38 .id = 0, 39 .dev = { 40 .platform_data = &scif0_platform_data, 41 }, 42 }; 43 44 static struct plat_sci_port scif1_platform_data = { 45 .mapbase = 0xffe10000, 46 .port_reg = SCIx_NOT_SUPPORTED, 47 .flags = UPF_BOOT_AUTOCONF, 48 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 49 .scbrr_algo_id = SCBRR_ALGO_2, 50 .type = PORT_SCIF, 51 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), 52 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 53 }; 54 55 static struct platform_device scif1_device = { 56 .name = "sh-sci", 57 .id = 1, 58 .dev = { 59 .platform_data = &scif1_platform_data, 60 }, 61 }; 62 63 static struct plat_sci_port scif2_platform_data = { 64 .mapbase = 0xffe20000, 65 .port_reg = SCIx_NOT_SUPPORTED, 66 .flags = UPF_BOOT_AUTOCONF, 67 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 68 .scbrr_algo_id = SCBRR_ALGO_2, 69 .type = PORT_SCIF, 70 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)), 71 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 72 }; 73 74 static struct platform_device scif2_device = { 75 .name = "sh-sci", 76 .id = 2, 77 .dev = { 78 .platform_data = &scif2_platform_data, 79 }, 80 }; 81 82 static struct plat_sci_port scif3_platform_data = { 83 .mapbase = 0xa4e30000, 84 .flags = UPF_BOOT_AUTOCONF, 85 .port_reg = SCIx_NOT_SUPPORTED, 86 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 87 .scbrr_algo_id = SCBRR_ALGO_3, 88 .type = PORT_SCIFA, 89 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), 90 }; 91 92 static struct platform_device scif3_device = { 93 .name = "sh-sci", 94 .id = 3, 95 .dev = { 96 .platform_data = &scif3_platform_data, 97 }, 98 }; 99 100 static struct plat_sci_port scif4_platform_data = { 101 .mapbase = 0xa4e40000, 102 .port_reg = SCIx_NOT_SUPPORTED, 103 .flags = UPF_BOOT_AUTOCONF, 104 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 105 .scbrr_algo_id = SCBRR_ALGO_3, 106 .type = PORT_SCIFA, 107 .irqs = SCIx_IRQ_MUXED(evt2irq(0xd00)), 108 }; 109 110 static struct platform_device scif4_device = { 111 .name = "sh-sci", 112 .id = 4, 113 .dev = { 114 .platform_data = &scif4_platform_data, 115 }, 116 }; 117 118 static struct plat_sci_port scif5_platform_data = { 119 .mapbase = 0xa4e50000, 120 .port_reg = SCIx_NOT_SUPPORTED, 121 .flags = UPF_BOOT_AUTOCONF, 122 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 123 .scbrr_algo_id = SCBRR_ALGO_3, 124 .type = PORT_SCIFA, 125 .irqs = SCIx_IRQ_MUXED(evt2irq(0xfa0)), 126 }; 127 128 static struct platform_device scif5_device = { 129 .name = "sh-sci", 130 .id = 5, 131 .dev = { 132 .platform_data = &scif5_platform_data, 133 }, 134 }; 135 136 static struct uio_info vpu_platform_data = { 137 .name = "VPU5", 138 .version = "0", 139 .irq = evt2irq(0x980), 140 }; 141 142 static struct resource vpu_resources[] = { 143 [0] = { 144 .name = "VPU", 145 .start = 0xfe900000, 146 .end = 0xfe902807, 147 .flags = IORESOURCE_MEM, 148 }, 149 [1] = { 150 /* place holder for contiguous memory */ 151 }, 152 }; 153 154 static struct platform_device vpu_device = { 155 .name = "uio_pdrv_genirq", 156 .id = 0, 157 .dev = { 158 .platform_data = &vpu_platform_data, 159 }, 160 .resource = vpu_resources, 161 .num_resources = ARRAY_SIZE(vpu_resources), 162 }; 163 164 static struct uio_info veu0_platform_data = { 165 .name = "VEU2H", 166 .version = "0", 167 .irq = evt2irq(0x8c0), 168 }; 169 170 static struct resource veu0_resources[] = { 171 [0] = { 172 .name = "VEU2H0", 173 .start = 0xfe920000, 174 .end = 0xfe92027b, 175 .flags = IORESOURCE_MEM, 176 }, 177 [1] = { 178 /* place holder for contiguous memory */ 179 }, 180 }; 181 182 static struct platform_device veu0_device = { 183 .name = "uio_pdrv_genirq", 184 .id = 1, 185 .dev = { 186 .platform_data = &veu0_platform_data, 187 }, 188 .resource = veu0_resources, 189 .num_resources = ARRAY_SIZE(veu0_resources), 190 }; 191 192 static struct uio_info veu1_platform_data = { 193 .name = "VEU2H", 194 .version = "0", 195 .irq = evt2irq(0x560), 196 }; 197 198 static struct resource veu1_resources[] = { 199 [0] = { 200 .name = "VEU2H1", 201 .start = 0xfe924000, 202 .end = 0xfe92427b, 203 .flags = IORESOURCE_MEM, 204 }, 205 [1] = { 206 /* place holder for contiguous memory */ 207 }, 208 }; 209 210 static struct platform_device veu1_device = { 211 .name = "uio_pdrv_genirq", 212 .id = 2, 213 .dev = { 214 .platform_data = &veu1_platform_data, 215 }, 216 .resource = veu1_resources, 217 .num_resources = ARRAY_SIZE(veu1_resources), 218 }; 219 220 static struct sh_timer_config cmt_platform_data = { 221 .channel_offset = 0x60, 222 .timer_bit = 5, 223 .clockevent_rating = 125, 224 .clocksource_rating = 125, 225 }; 226 227 static struct resource cmt_resources[] = { 228 [0] = { 229 .start = 0x044a0060, 230 .end = 0x044a006b, 231 .flags = IORESOURCE_MEM, 232 }, 233 [1] = { 234 .start = evt2irq(0xf00), 235 .flags = IORESOURCE_IRQ, 236 }, 237 }; 238 239 static struct platform_device cmt_device = { 240 .name = "sh_cmt", 241 .id = 0, 242 .dev = { 243 .platform_data = &cmt_platform_data, 244 }, 245 .resource = cmt_resources, 246 .num_resources = ARRAY_SIZE(cmt_resources), 247 }; 248 249 static struct sh_timer_config tmu0_platform_data = { 250 .channel_offset = 0x04, 251 .timer_bit = 0, 252 .clockevent_rating = 200, 253 }; 254 255 static struct resource tmu0_resources[] = { 256 [0] = { 257 .start = 0xffd80008, 258 .end = 0xffd80013, 259 .flags = IORESOURCE_MEM, 260 }, 261 [1] = { 262 .start = evt2irq(0x400), 263 .flags = IORESOURCE_IRQ, 264 }, 265 }; 266 267 static struct platform_device tmu0_device = { 268 .name = "sh_tmu", 269 .id = 0, 270 .dev = { 271 .platform_data = &tmu0_platform_data, 272 }, 273 .resource = tmu0_resources, 274 .num_resources = ARRAY_SIZE(tmu0_resources), 275 }; 276 277 static struct sh_timer_config tmu1_platform_data = { 278 .channel_offset = 0x10, 279 .timer_bit = 1, 280 .clocksource_rating = 200, 281 }; 282 283 static struct resource tmu1_resources[] = { 284 [0] = { 285 .start = 0xffd80014, 286 .end = 0xffd8001f, 287 .flags = IORESOURCE_MEM, 288 }, 289 [1] = { 290 .start = evt2irq(0x420), 291 .flags = IORESOURCE_IRQ, 292 }, 293 }; 294 295 static struct platform_device tmu1_device = { 296 .name = "sh_tmu", 297 .id = 1, 298 .dev = { 299 .platform_data = &tmu1_platform_data, 300 }, 301 .resource = tmu1_resources, 302 .num_resources = ARRAY_SIZE(tmu1_resources), 303 }; 304 305 static struct sh_timer_config tmu2_platform_data = { 306 .channel_offset = 0x1c, 307 .timer_bit = 2, 308 }; 309 310 static struct resource tmu2_resources[] = { 311 [0] = { 312 .start = 0xffd80020, 313 .end = 0xffd8002b, 314 .flags = IORESOURCE_MEM, 315 }, 316 [1] = { 317 .start = evt2irq(0x440), 318 .flags = IORESOURCE_IRQ, 319 }, 320 }; 321 322 static struct platform_device tmu2_device = { 323 .name = "sh_tmu", 324 .id = 2, 325 .dev = { 326 .platform_data = &tmu2_platform_data, 327 }, 328 .resource = tmu2_resources, 329 .num_resources = ARRAY_SIZE(tmu2_resources), 330 }; 331 332 static struct sh_timer_config tmu3_platform_data = { 333 .channel_offset = 0x04, 334 .timer_bit = 0, 335 }; 336 337 static struct resource tmu3_resources[] = { 338 [0] = { 339 .start = 0xffd90008, 340 .end = 0xffd90013, 341 .flags = IORESOURCE_MEM, 342 }, 343 [1] = { 344 .start = evt2irq(0x920), 345 .flags = IORESOURCE_IRQ, 346 }, 347 }; 348 349 static struct platform_device tmu3_device = { 350 .name = "sh_tmu", 351 .id = 3, 352 .dev = { 353 .platform_data = &tmu3_platform_data, 354 }, 355 .resource = tmu3_resources, 356 .num_resources = ARRAY_SIZE(tmu3_resources), 357 }; 358 359 static struct sh_timer_config tmu4_platform_data = { 360 .channel_offset = 0x10, 361 .timer_bit = 1, 362 }; 363 364 static struct resource tmu4_resources[] = { 365 [0] = { 366 .start = 0xffd90014, 367 .end = 0xffd9001f, 368 .flags = IORESOURCE_MEM, 369 }, 370 [1] = { 371 .start = evt2irq(0x940), 372 .flags = IORESOURCE_IRQ, 373 }, 374 }; 375 376 static struct platform_device tmu4_device = { 377 .name = "sh_tmu", 378 .id = 4, 379 .dev = { 380 .platform_data = &tmu4_platform_data, 381 }, 382 .resource = tmu4_resources, 383 .num_resources = ARRAY_SIZE(tmu4_resources), 384 }; 385 386 static struct sh_timer_config tmu5_platform_data = { 387 .channel_offset = 0x1c, 388 .timer_bit = 2, 389 }; 390 391 static struct resource tmu5_resources[] = { 392 [0] = { 393 .start = 0xffd90020, 394 .end = 0xffd9002b, 395 .flags = IORESOURCE_MEM, 396 }, 397 [1] = { 398 .start = evt2irq(0x920), 399 .flags = IORESOURCE_IRQ, 400 }, 401 }; 402 403 static struct platform_device tmu5_device = { 404 .name = "sh_tmu", 405 .id = 5, 406 .dev = { 407 .platform_data = &tmu5_platform_data, 408 }, 409 .resource = tmu5_resources, 410 .num_resources = ARRAY_SIZE(tmu5_resources), 411 }; 412 413 static struct resource rtc_resources[] = { 414 [0] = { 415 .start = 0xa465fec0, 416 .end = 0xa465fec0 + 0x58 - 1, 417 .flags = IORESOURCE_IO, 418 }, 419 [1] = { 420 /* Period IRQ */ 421 .start = evt2irq(0xaa0), 422 .flags = IORESOURCE_IRQ, 423 }, 424 [2] = { 425 /* Carry IRQ */ 426 .start = evt2irq(0xac0), 427 .flags = IORESOURCE_IRQ, 428 }, 429 [3] = { 430 /* Alarm IRQ */ 431 .start = evt2irq(0xa80), 432 .flags = IORESOURCE_IRQ, 433 }, 434 }; 435 436 static struct platform_device rtc_device = { 437 .name = "sh-rtc", 438 .id = -1, 439 .num_resources = ARRAY_SIZE(rtc_resources), 440 .resource = rtc_resources, 441 }; 442 443 static struct r8a66597_platdata r8a66597_data = { 444 .on_chip = 1, 445 }; 446 447 static struct resource sh7723_usb_host_resources[] = { 448 [0] = { 449 .start = 0xa4d80000, 450 .end = 0xa4d800ff, 451 .flags = IORESOURCE_MEM, 452 }, 453 [1] = { 454 .start = evt2irq(0xa20), 455 .end = evt2irq(0xa20), 456 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, 457 }, 458 }; 459 460 static struct platform_device sh7723_usb_host_device = { 461 .name = "r8a66597_hcd", 462 .id = 0, 463 .dev = { 464 .dma_mask = NULL, /* not use dma */ 465 .coherent_dma_mask = 0xffffffff, 466 .platform_data = &r8a66597_data, 467 }, 468 .num_resources = ARRAY_SIZE(sh7723_usb_host_resources), 469 .resource = sh7723_usb_host_resources, 470 }; 471 472 static struct resource iic_resources[] = { 473 [0] = { 474 .name = "IIC", 475 .start = 0x04470000, 476 .end = 0x04470017, 477 .flags = IORESOURCE_MEM, 478 }, 479 [1] = { 480 .start = evt2irq(0xe00), 481 .end = evt2irq(0xe60), 482 .flags = IORESOURCE_IRQ, 483 }, 484 }; 485 486 static struct platform_device iic_device = { 487 .name = "i2c-sh_mobile", 488 .id = 0, /* "i2c0" clock */ 489 .num_resources = ARRAY_SIZE(iic_resources), 490 .resource = iic_resources, 491 }; 492 493 static struct platform_device *sh7723_devices[] __initdata = { 494 &scif0_device, 495 &scif1_device, 496 &scif2_device, 497 &scif3_device, 498 &scif4_device, 499 &scif5_device, 500 &cmt_device, 501 &tmu0_device, 502 &tmu1_device, 503 &tmu2_device, 504 &tmu3_device, 505 &tmu4_device, 506 &tmu5_device, 507 &rtc_device, 508 &iic_device, 509 &sh7723_usb_host_device, 510 &vpu_device, 511 &veu0_device, 512 &veu1_device, 513 }; 514 515 static int __init sh7723_devices_setup(void) 516 { 517 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 518 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 519 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 520 521 return platform_add_devices(sh7723_devices, 522 ARRAY_SIZE(sh7723_devices)); 523 } 524 arch_initcall(sh7723_devices_setup); 525 526 static struct platform_device *sh7723_early_devices[] __initdata = { 527 &scif0_device, 528 &scif1_device, 529 &scif2_device, 530 &scif3_device, 531 &scif4_device, 532 &scif5_device, 533 &cmt_device, 534 &tmu0_device, 535 &tmu1_device, 536 &tmu2_device, 537 &tmu3_device, 538 &tmu4_device, 539 &tmu5_device, 540 }; 541 542 void __init plat_early_device_setup(void) 543 { 544 early_platform_add_devices(sh7723_early_devices, 545 ARRAY_SIZE(sh7723_early_devices)); 546 } 547 548 #define RAMCR_CACHE_L2FC 0x0002 549 #define RAMCR_CACHE_L2E 0x0001 550 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) 551 552 void l2_cache_init(void) 553 { 554 /* Enable L2 cache */ 555 __raw_writel(L2_CACHE_ENABLE, RAMCR); 556 } 557 558 enum { 559 UNUSED=0, 560 ENABLED, 561 DISABLED, 562 563 /* interrupt sources */ 564 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 565 HUDI, 566 DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3, 567 _2DG_TRI,_2DG_INI,_2DG_CEI, 568 DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3, 569 VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI, 570 SCIFA_SCIFA0, 571 VPU_VPUI, 572 TPU_TPUI, 573 ADC_ADI, 574 USB_USI0, 575 RTC_ATI,RTC_PRI,RTC_CUI, 576 DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR, 577 DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR, 578 KEYSC_KEYI, 579 SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2, 580 MSIOF_MSIOFI0,MSIOF_MSIOFI1, 581 SCIFA_SCIFA1, 582 FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I, 583 I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI, 584 CMT_CMTI, 585 TSIF_TSIFI, 586 SIU_SIUI, 587 SCIFA_SCIFA2, 588 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, 589 IRDA_IRDAI, 590 ATAPI_ATAPII, 591 VEU2H1_VEU2HI, 592 LCDC_LCDCI, 593 TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2, 594 595 /* interrupt groups */ 596 DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG, 597 SDHI1, RTC, DMAC1B, SDHI0, 598 }; 599 600 static struct intc_vect vectors[] __initdata = { 601 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 602 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 603 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 604 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 605 606 INTC_VECT(DMAC1A_DEI0,0x700), 607 INTC_VECT(DMAC1A_DEI1,0x720), 608 INTC_VECT(DMAC1A_DEI2,0x740), 609 INTC_VECT(DMAC1A_DEI3,0x760), 610 611 INTC_VECT(_2DG_TRI, 0x780), 612 INTC_VECT(_2DG_INI, 0x7A0), 613 INTC_VECT(_2DG_CEI, 0x7C0), 614 615 INTC_VECT(DMAC0A_DEI0,0x800), 616 INTC_VECT(DMAC0A_DEI1,0x820), 617 INTC_VECT(DMAC0A_DEI2,0x840), 618 INTC_VECT(DMAC0A_DEI3,0x860), 619 620 INTC_VECT(VIO_CEUI,0x880), 621 INTC_VECT(VIO_BEUI,0x8A0), 622 INTC_VECT(VIO_VEU2HI,0x8C0), 623 INTC_VECT(VIO_VOUI,0x8E0), 624 625 INTC_VECT(SCIFA_SCIFA0,0x900), 626 INTC_VECT(VPU_VPUI,0x980), 627 INTC_VECT(TPU_TPUI,0x9A0), 628 INTC_VECT(ADC_ADI,0x9E0), 629 INTC_VECT(USB_USI0,0xA20), 630 631 INTC_VECT(RTC_ATI,0xA80), 632 INTC_VECT(RTC_PRI,0xAA0), 633 INTC_VECT(RTC_CUI,0xAC0), 634 635 INTC_VECT(DMAC1B_DEI4,0xB00), 636 INTC_VECT(DMAC1B_DEI5,0xB20), 637 INTC_VECT(DMAC1B_DADERR,0xB40), 638 639 INTC_VECT(DMAC0B_DEI4,0xB80), 640 INTC_VECT(DMAC0B_DEI5,0xBA0), 641 INTC_VECT(DMAC0B_DADERR,0xBC0), 642 643 INTC_VECT(KEYSC_KEYI,0xBE0), 644 INTC_VECT(SCIF_SCIF0,0xC00), 645 INTC_VECT(SCIF_SCIF1,0xC20), 646 INTC_VECT(SCIF_SCIF2,0xC40), 647 INTC_VECT(MSIOF_MSIOFI0,0xC80), 648 INTC_VECT(MSIOF_MSIOFI1,0xCA0), 649 INTC_VECT(SCIFA_SCIFA1,0xD00), 650 651 INTC_VECT(FLCTL_FLSTEI,0xD80), 652 INTC_VECT(FLCTL_FLTENDI,0xDA0), 653 INTC_VECT(FLCTL_FLTREQ0I,0xDC0), 654 INTC_VECT(FLCTL_FLTREQ1I,0xDE0), 655 656 INTC_VECT(I2C_ALI,0xE00), 657 INTC_VECT(I2C_TACKI,0xE20), 658 INTC_VECT(I2C_WAITI,0xE40), 659 INTC_VECT(I2C_DTEI,0xE60), 660 661 INTC_VECT(SDHI0, 0xE80), 662 INTC_VECT(SDHI0, 0xEA0), 663 INTC_VECT(SDHI0, 0xEC0), 664 665 INTC_VECT(CMT_CMTI,0xF00), 666 INTC_VECT(TSIF_TSIFI,0xF20), 667 INTC_VECT(SIU_SIUI,0xF80), 668 INTC_VECT(SCIFA_SCIFA2,0xFA0), 669 670 INTC_VECT(TMU0_TUNI0,0x400), 671 INTC_VECT(TMU0_TUNI1,0x420), 672 INTC_VECT(TMU0_TUNI2,0x440), 673 674 INTC_VECT(IRDA_IRDAI,0x480), 675 INTC_VECT(ATAPI_ATAPII,0x4A0), 676 677 INTC_VECT(SDHI1, 0x4E0), 678 INTC_VECT(SDHI1, 0x500), 679 INTC_VECT(SDHI1, 0x520), 680 681 INTC_VECT(VEU2H1_VEU2HI,0x560), 682 INTC_VECT(LCDC_LCDCI,0x580), 683 684 INTC_VECT(TMU1_TUNI0,0x920), 685 INTC_VECT(TMU1_TUNI1,0x940), 686 INTC_VECT(TMU1_TUNI2,0x960), 687 688 }; 689 690 static struct intc_group groups[] __initdata = { 691 INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3), 692 INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3), 693 INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI), 694 INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR), 695 INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I), 696 INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI), 697 INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI), 698 INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI), 699 INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR), 700 }; 701 702 static struct intc_mask_reg mask_registers[] __initdata = { 703 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 704 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, 705 0, ENABLED, ENABLED, ENABLED } }, 706 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 707 { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } }, 708 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 709 { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } }, 710 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 711 { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } }, 712 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 713 { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } }, 714 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 715 { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } }, 716 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 717 { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } }, 718 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 719 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 720 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, 721 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 722 { 0, ENABLED, ENABLED, ENABLED, 723 0, 0, SCIFA_SCIFA2, SIU_SIUI } }, 724 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 725 { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } }, 726 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 727 { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } }, 728 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 729 { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } }, 730 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */ 731 { 0,0,0,0,0,0,0,ATAPI_ATAPII } }, 732 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 733 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 734 }; 735 736 static struct intc_prio_reg prio_registers[] __initdata = { 737 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } }, 738 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} }, 739 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} }, 740 { 0xa408000c, 0, 16, 4, /* IPRD */ { } }, 741 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } }, 742 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } }, 743 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } }, 744 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } }, 745 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } }, 746 { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } }, 747 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } }, 748 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } }, 749 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 750 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 751 }; 752 753 static struct intc_sense_reg sense_registers[] __initdata = { 754 { 0xa414001c, 16, 2, /* ICR1 */ 755 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 756 }; 757 758 static struct intc_mask_reg ack_registers[] __initdata = { 759 { 0xa4140024, 0, 8, /* INTREQ00 */ 760 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 761 }; 762 763 static struct intc_desc intc_desc __initdata = { 764 .name = "sh7723", 765 .force_enable = ENABLED, 766 .force_disable = DISABLED, 767 .hw = INTC_HW_DESC(vectors, groups, mask_registers, 768 prio_registers, sense_registers, ack_registers), 769 }; 770 771 void __init plat_irq_setup(void) 772 { 773 register_intc_controller(&intc_desc); 774 } 775