1 /* 2 * SH7723 Setup 3 * 4 * Copyright (C) 2008 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/mm.h> 14 #include <linux/serial_sci.h> 15 #include <linux/uio_driver.h> 16 #include <linux/usb/r8a66597.h> 17 #include <linux/sh_timer.h> 18 #include <linux/sh_intc.h> 19 #include <linux/io.h> 20 #include <asm/clock.h> 21 #include <asm/mmzone.h> 22 #include <cpu/sh7723.h> 23 24 /* Serial */ 25 static struct plat_sci_port scif0_platform_data = { 26 .port_reg = 0xa4050160, 27 .flags = UPF_BOOT_AUTOCONF, 28 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 29 .type = PORT_SCIF, 30 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 31 }; 32 33 static struct resource scif0_resources[] = { 34 DEFINE_RES_MEM(0xffe00000, 0x100), 35 DEFINE_RES_IRQ(evt2irq(0xc00)), 36 }; 37 38 static struct platform_device scif0_device = { 39 .name = "sh-sci", 40 .id = 0, 41 .resource = scif0_resources, 42 .num_resources = ARRAY_SIZE(scif0_resources), 43 .dev = { 44 .platform_data = &scif0_platform_data, 45 }, 46 }; 47 48 static struct plat_sci_port scif1_platform_data = { 49 .port_reg = SCIx_NOT_SUPPORTED, 50 .flags = UPF_BOOT_AUTOCONF, 51 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 52 .type = PORT_SCIF, 53 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 54 }; 55 56 static struct resource scif1_resources[] = { 57 DEFINE_RES_MEM(0xffe10000, 0x100), 58 DEFINE_RES_IRQ(evt2irq(0xc20)), 59 }; 60 61 static struct platform_device scif1_device = { 62 .name = "sh-sci", 63 .id = 1, 64 .resource = scif1_resources, 65 .num_resources = ARRAY_SIZE(scif1_resources), 66 .dev = { 67 .platform_data = &scif1_platform_data, 68 }, 69 }; 70 71 static struct plat_sci_port scif2_platform_data = { 72 .port_reg = SCIx_NOT_SUPPORTED, 73 .flags = UPF_BOOT_AUTOCONF, 74 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 75 .type = PORT_SCIF, 76 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 77 }; 78 79 static struct resource scif2_resources[] = { 80 DEFINE_RES_MEM(0xffe20000, 0x100), 81 DEFINE_RES_IRQ(evt2irq(0xc40)), 82 }; 83 84 static struct platform_device scif2_device = { 85 .name = "sh-sci", 86 .id = 2, 87 .resource = scif2_resources, 88 .num_resources = ARRAY_SIZE(scif2_resources), 89 .dev = { 90 .platform_data = &scif2_platform_data, 91 }, 92 }; 93 94 static struct plat_sci_port scif3_platform_data = { 95 .flags = UPF_BOOT_AUTOCONF, 96 .port_reg = SCIx_NOT_SUPPORTED, 97 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 98 .sampling_rate = 8, 99 .type = PORT_SCIFA, 100 }; 101 102 static struct resource scif3_resources[] = { 103 DEFINE_RES_MEM(0xa4e30000, 0x100), 104 DEFINE_RES_IRQ(evt2irq(0x900)), 105 }; 106 107 static struct platform_device scif3_device = { 108 .name = "sh-sci", 109 .id = 3, 110 .resource = scif3_resources, 111 .num_resources = ARRAY_SIZE(scif3_resources), 112 .dev = { 113 .platform_data = &scif3_platform_data, 114 }, 115 }; 116 117 static struct plat_sci_port scif4_platform_data = { 118 .port_reg = SCIx_NOT_SUPPORTED, 119 .flags = UPF_BOOT_AUTOCONF, 120 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 121 .sampling_rate = 8, 122 .type = PORT_SCIFA, 123 }; 124 125 static struct resource scif4_resources[] = { 126 DEFINE_RES_MEM(0xa4e40000, 0x100), 127 DEFINE_RES_IRQ(evt2irq(0xd00)), 128 }; 129 130 static struct platform_device scif4_device = { 131 .name = "sh-sci", 132 .id = 4, 133 .resource = scif4_resources, 134 .num_resources = ARRAY_SIZE(scif4_resources), 135 .dev = { 136 .platform_data = &scif4_platform_data, 137 }, 138 }; 139 140 static struct plat_sci_port scif5_platform_data = { 141 .port_reg = SCIx_NOT_SUPPORTED, 142 .flags = UPF_BOOT_AUTOCONF, 143 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 144 .sampling_rate = 8, 145 .type = PORT_SCIFA, 146 }; 147 148 static struct resource scif5_resources[] = { 149 DEFINE_RES_MEM(0xa4e50000, 0x100), 150 DEFINE_RES_IRQ(evt2irq(0xfa0)), 151 }; 152 153 static struct platform_device scif5_device = { 154 .name = "sh-sci", 155 .id = 5, 156 .resource = scif5_resources, 157 .num_resources = ARRAY_SIZE(scif5_resources), 158 .dev = { 159 .platform_data = &scif5_platform_data, 160 }, 161 }; 162 163 static struct uio_info vpu_platform_data = { 164 .name = "VPU5", 165 .version = "0", 166 .irq = evt2irq(0x980), 167 }; 168 169 static struct resource vpu_resources[] = { 170 [0] = { 171 .name = "VPU", 172 .start = 0xfe900000, 173 .end = 0xfe902807, 174 .flags = IORESOURCE_MEM, 175 }, 176 [1] = { 177 /* place holder for contiguous memory */ 178 }, 179 }; 180 181 static struct platform_device vpu_device = { 182 .name = "uio_pdrv_genirq", 183 .id = 0, 184 .dev = { 185 .platform_data = &vpu_platform_data, 186 }, 187 .resource = vpu_resources, 188 .num_resources = ARRAY_SIZE(vpu_resources), 189 }; 190 191 static struct uio_info veu0_platform_data = { 192 .name = "VEU2H", 193 .version = "0", 194 .irq = evt2irq(0x8c0), 195 }; 196 197 static struct resource veu0_resources[] = { 198 [0] = { 199 .name = "VEU2H0", 200 .start = 0xfe920000, 201 .end = 0xfe92027b, 202 .flags = IORESOURCE_MEM, 203 }, 204 [1] = { 205 /* place holder for contiguous memory */ 206 }, 207 }; 208 209 static struct platform_device veu0_device = { 210 .name = "uio_pdrv_genirq", 211 .id = 1, 212 .dev = { 213 .platform_data = &veu0_platform_data, 214 }, 215 .resource = veu0_resources, 216 .num_resources = ARRAY_SIZE(veu0_resources), 217 }; 218 219 static struct uio_info veu1_platform_data = { 220 .name = "VEU2H", 221 .version = "0", 222 .irq = evt2irq(0x560), 223 }; 224 225 static struct resource veu1_resources[] = { 226 [0] = { 227 .name = "VEU2H1", 228 .start = 0xfe924000, 229 .end = 0xfe92427b, 230 .flags = IORESOURCE_MEM, 231 }, 232 [1] = { 233 /* place holder for contiguous memory */ 234 }, 235 }; 236 237 static struct platform_device veu1_device = { 238 .name = "uio_pdrv_genirq", 239 .id = 2, 240 .dev = { 241 .platform_data = &veu1_platform_data, 242 }, 243 .resource = veu1_resources, 244 .num_resources = ARRAY_SIZE(veu1_resources), 245 }; 246 247 static struct sh_timer_config cmt_platform_data = { 248 .channel_offset = 0x60, 249 .timer_bit = 5, 250 .clockevent_rating = 125, 251 .clocksource_rating = 125, 252 }; 253 254 static struct resource cmt_resources[] = { 255 [0] = { 256 .start = 0x044a0060, 257 .end = 0x044a006b, 258 .flags = IORESOURCE_MEM, 259 }, 260 [1] = { 261 .start = evt2irq(0xf00), 262 .flags = IORESOURCE_IRQ, 263 }, 264 }; 265 266 static struct platform_device cmt_device = { 267 .name = "sh_cmt", 268 .id = 0, 269 .dev = { 270 .platform_data = &cmt_platform_data, 271 }, 272 .resource = cmt_resources, 273 .num_resources = ARRAY_SIZE(cmt_resources), 274 }; 275 276 static struct sh_timer_config tmu0_platform_data = { 277 .channel_offset = 0x04, 278 .timer_bit = 0, 279 .clockevent_rating = 200, 280 }; 281 282 static struct resource tmu0_resources[] = { 283 [0] = { 284 .start = 0xffd80008, 285 .end = 0xffd80013, 286 .flags = IORESOURCE_MEM, 287 }, 288 [1] = { 289 .start = evt2irq(0x400), 290 .flags = IORESOURCE_IRQ, 291 }, 292 }; 293 294 static struct platform_device tmu0_device = { 295 .name = "sh_tmu", 296 .id = 0, 297 .dev = { 298 .platform_data = &tmu0_platform_data, 299 }, 300 .resource = tmu0_resources, 301 .num_resources = ARRAY_SIZE(tmu0_resources), 302 }; 303 304 static struct sh_timer_config tmu1_platform_data = { 305 .channel_offset = 0x10, 306 .timer_bit = 1, 307 .clocksource_rating = 200, 308 }; 309 310 static struct resource tmu1_resources[] = { 311 [0] = { 312 .start = 0xffd80014, 313 .end = 0xffd8001f, 314 .flags = IORESOURCE_MEM, 315 }, 316 [1] = { 317 .start = evt2irq(0x420), 318 .flags = IORESOURCE_IRQ, 319 }, 320 }; 321 322 static struct platform_device tmu1_device = { 323 .name = "sh_tmu", 324 .id = 1, 325 .dev = { 326 .platform_data = &tmu1_platform_data, 327 }, 328 .resource = tmu1_resources, 329 .num_resources = ARRAY_SIZE(tmu1_resources), 330 }; 331 332 static struct sh_timer_config tmu2_platform_data = { 333 .channel_offset = 0x1c, 334 .timer_bit = 2, 335 }; 336 337 static struct resource tmu2_resources[] = { 338 [0] = { 339 .start = 0xffd80020, 340 .end = 0xffd8002b, 341 .flags = IORESOURCE_MEM, 342 }, 343 [1] = { 344 .start = evt2irq(0x440), 345 .flags = IORESOURCE_IRQ, 346 }, 347 }; 348 349 static struct platform_device tmu2_device = { 350 .name = "sh_tmu", 351 .id = 2, 352 .dev = { 353 .platform_data = &tmu2_platform_data, 354 }, 355 .resource = tmu2_resources, 356 .num_resources = ARRAY_SIZE(tmu2_resources), 357 }; 358 359 static struct sh_timer_config tmu3_platform_data = { 360 .channel_offset = 0x04, 361 .timer_bit = 0, 362 }; 363 364 static struct resource tmu3_resources[] = { 365 [0] = { 366 .start = 0xffd90008, 367 .end = 0xffd90013, 368 .flags = IORESOURCE_MEM, 369 }, 370 [1] = { 371 .start = evt2irq(0x920), 372 .flags = IORESOURCE_IRQ, 373 }, 374 }; 375 376 static struct platform_device tmu3_device = { 377 .name = "sh_tmu", 378 .id = 3, 379 .dev = { 380 .platform_data = &tmu3_platform_data, 381 }, 382 .resource = tmu3_resources, 383 .num_resources = ARRAY_SIZE(tmu3_resources), 384 }; 385 386 static struct sh_timer_config tmu4_platform_data = { 387 .channel_offset = 0x10, 388 .timer_bit = 1, 389 }; 390 391 static struct resource tmu4_resources[] = { 392 [0] = { 393 .start = 0xffd90014, 394 .end = 0xffd9001f, 395 .flags = IORESOURCE_MEM, 396 }, 397 [1] = { 398 .start = evt2irq(0x940), 399 .flags = IORESOURCE_IRQ, 400 }, 401 }; 402 403 static struct platform_device tmu4_device = { 404 .name = "sh_tmu", 405 .id = 4, 406 .dev = { 407 .platform_data = &tmu4_platform_data, 408 }, 409 .resource = tmu4_resources, 410 .num_resources = ARRAY_SIZE(tmu4_resources), 411 }; 412 413 static struct sh_timer_config tmu5_platform_data = { 414 .channel_offset = 0x1c, 415 .timer_bit = 2, 416 }; 417 418 static struct resource tmu5_resources[] = { 419 [0] = { 420 .start = 0xffd90020, 421 .end = 0xffd9002b, 422 .flags = IORESOURCE_MEM, 423 }, 424 [1] = { 425 .start = evt2irq(0x920), 426 .flags = IORESOURCE_IRQ, 427 }, 428 }; 429 430 static struct platform_device tmu5_device = { 431 .name = "sh_tmu", 432 .id = 5, 433 .dev = { 434 .platform_data = &tmu5_platform_data, 435 }, 436 .resource = tmu5_resources, 437 .num_resources = ARRAY_SIZE(tmu5_resources), 438 }; 439 440 static struct resource rtc_resources[] = { 441 [0] = { 442 .start = 0xa465fec0, 443 .end = 0xa465fec0 + 0x58 - 1, 444 .flags = IORESOURCE_IO, 445 }, 446 [1] = { 447 /* Period IRQ */ 448 .start = evt2irq(0xaa0), 449 .flags = IORESOURCE_IRQ, 450 }, 451 [2] = { 452 /* Carry IRQ */ 453 .start = evt2irq(0xac0), 454 .flags = IORESOURCE_IRQ, 455 }, 456 [3] = { 457 /* Alarm IRQ */ 458 .start = evt2irq(0xa80), 459 .flags = IORESOURCE_IRQ, 460 }, 461 }; 462 463 static struct platform_device rtc_device = { 464 .name = "sh-rtc", 465 .id = -1, 466 .num_resources = ARRAY_SIZE(rtc_resources), 467 .resource = rtc_resources, 468 }; 469 470 static struct r8a66597_platdata r8a66597_data = { 471 .on_chip = 1, 472 }; 473 474 static struct resource sh7723_usb_host_resources[] = { 475 [0] = { 476 .start = 0xa4d80000, 477 .end = 0xa4d800ff, 478 .flags = IORESOURCE_MEM, 479 }, 480 [1] = { 481 .start = evt2irq(0xa20), 482 .end = evt2irq(0xa20), 483 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, 484 }, 485 }; 486 487 static struct platform_device sh7723_usb_host_device = { 488 .name = "r8a66597_hcd", 489 .id = 0, 490 .dev = { 491 .dma_mask = NULL, /* not use dma */ 492 .coherent_dma_mask = 0xffffffff, 493 .platform_data = &r8a66597_data, 494 }, 495 .num_resources = ARRAY_SIZE(sh7723_usb_host_resources), 496 .resource = sh7723_usb_host_resources, 497 }; 498 499 static struct resource iic_resources[] = { 500 [0] = { 501 .name = "IIC", 502 .start = 0x04470000, 503 .end = 0x04470017, 504 .flags = IORESOURCE_MEM, 505 }, 506 [1] = { 507 .start = evt2irq(0xe00), 508 .end = evt2irq(0xe60), 509 .flags = IORESOURCE_IRQ, 510 }, 511 }; 512 513 static struct platform_device iic_device = { 514 .name = "i2c-sh_mobile", 515 .id = 0, /* "i2c0" clock */ 516 .num_resources = ARRAY_SIZE(iic_resources), 517 .resource = iic_resources, 518 }; 519 520 static struct platform_device *sh7723_devices[] __initdata = { 521 &scif0_device, 522 &scif1_device, 523 &scif2_device, 524 &scif3_device, 525 &scif4_device, 526 &scif5_device, 527 &cmt_device, 528 &tmu0_device, 529 &tmu1_device, 530 &tmu2_device, 531 &tmu3_device, 532 &tmu4_device, 533 &tmu5_device, 534 &rtc_device, 535 &iic_device, 536 &sh7723_usb_host_device, 537 &vpu_device, 538 &veu0_device, 539 &veu1_device, 540 }; 541 542 static int __init sh7723_devices_setup(void) 543 { 544 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 545 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 546 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 547 548 return platform_add_devices(sh7723_devices, 549 ARRAY_SIZE(sh7723_devices)); 550 } 551 arch_initcall(sh7723_devices_setup); 552 553 static struct platform_device *sh7723_early_devices[] __initdata = { 554 &scif0_device, 555 &scif1_device, 556 &scif2_device, 557 &scif3_device, 558 &scif4_device, 559 &scif5_device, 560 &cmt_device, 561 &tmu0_device, 562 &tmu1_device, 563 &tmu2_device, 564 &tmu3_device, 565 &tmu4_device, 566 &tmu5_device, 567 }; 568 569 void __init plat_early_device_setup(void) 570 { 571 early_platform_add_devices(sh7723_early_devices, 572 ARRAY_SIZE(sh7723_early_devices)); 573 } 574 575 #define RAMCR_CACHE_L2FC 0x0002 576 #define RAMCR_CACHE_L2E 0x0001 577 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) 578 579 void l2_cache_init(void) 580 { 581 /* Enable L2 cache */ 582 __raw_writel(L2_CACHE_ENABLE, RAMCR); 583 } 584 585 enum { 586 UNUSED=0, 587 ENABLED, 588 DISABLED, 589 590 /* interrupt sources */ 591 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 592 HUDI, 593 DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3, 594 _2DG_TRI,_2DG_INI,_2DG_CEI, 595 DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3, 596 VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI, 597 SCIFA_SCIFA0, 598 VPU_VPUI, 599 TPU_TPUI, 600 ADC_ADI, 601 USB_USI0, 602 RTC_ATI,RTC_PRI,RTC_CUI, 603 DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR, 604 DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR, 605 KEYSC_KEYI, 606 SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2, 607 MSIOF_MSIOFI0,MSIOF_MSIOFI1, 608 SCIFA_SCIFA1, 609 FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I, 610 I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI, 611 CMT_CMTI, 612 TSIF_TSIFI, 613 SIU_SIUI, 614 SCIFA_SCIFA2, 615 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, 616 IRDA_IRDAI, 617 ATAPI_ATAPII, 618 VEU2H1_VEU2HI, 619 LCDC_LCDCI, 620 TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2, 621 622 /* interrupt groups */ 623 DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG, 624 SDHI1, RTC, DMAC1B, SDHI0, 625 }; 626 627 static struct intc_vect vectors[] __initdata = { 628 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 629 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 630 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 631 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 632 633 INTC_VECT(DMAC1A_DEI0,0x700), 634 INTC_VECT(DMAC1A_DEI1,0x720), 635 INTC_VECT(DMAC1A_DEI2,0x740), 636 INTC_VECT(DMAC1A_DEI3,0x760), 637 638 INTC_VECT(_2DG_TRI, 0x780), 639 INTC_VECT(_2DG_INI, 0x7A0), 640 INTC_VECT(_2DG_CEI, 0x7C0), 641 642 INTC_VECT(DMAC0A_DEI0,0x800), 643 INTC_VECT(DMAC0A_DEI1,0x820), 644 INTC_VECT(DMAC0A_DEI2,0x840), 645 INTC_VECT(DMAC0A_DEI3,0x860), 646 647 INTC_VECT(VIO_CEUI,0x880), 648 INTC_VECT(VIO_BEUI,0x8A0), 649 INTC_VECT(VIO_VEU2HI,0x8C0), 650 INTC_VECT(VIO_VOUI,0x8E0), 651 652 INTC_VECT(SCIFA_SCIFA0,0x900), 653 INTC_VECT(VPU_VPUI,0x980), 654 INTC_VECT(TPU_TPUI,0x9A0), 655 INTC_VECT(ADC_ADI,0x9E0), 656 INTC_VECT(USB_USI0,0xA20), 657 658 INTC_VECT(RTC_ATI,0xA80), 659 INTC_VECT(RTC_PRI,0xAA0), 660 INTC_VECT(RTC_CUI,0xAC0), 661 662 INTC_VECT(DMAC1B_DEI4,0xB00), 663 INTC_VECT(DMAC1B_DEI5,0xB20), 664 INTC_VECT(DMAC1B_DADERR,0xB40), 665 666 INTC_VECT(DMAC0B_DEI4,0xB80), 667 INTC_VECT(DMAC0B_DEI5,0xBA0), 668 INTC_VECT(DMAC0B_DADERR,0xBC0), 669 670 INTC_VECT(KEYSC_KEYI,0xBE0), 671 INTC_VECT(SCIF_SCIF0,0xC00), 672 INTC_VECT(SCIF_SCIF1,0xC20), 673 INTC_VECT(SCIF_SCIF2,0xC40), 674 INTC_VECT(MSIOF_MSIOFI0,0xC80), 675 INTC_VECT(MSIOF_MSIOFI1,0xCA0), 676 INTC_VECT(SCIFA_SCIFA1,0xD00), 677 678 INTC_VECT(FLCTL_FLSTEI,0xD80), 679 INTC_VECT(FLCTL_FLTENDI,0xDA0), 680 INTC_VECT(FLCTL_FLTREQ0I,0xDC0), 681 INTC_VECT(FLCTL_FLTREQ1I,0xDE0), 682 683 INTC_VECT(I2C_ALI,0xE00), 684 INTC_VECT(I2C_TACKI,0xE20), 685 INTC_VECT(I2C_WAITI,0xE40), 686 INTC_VECT(I2C_DTEI,0xE60), 687 688 INTC_VECT(SDHI0, 0xE80), 689 INTC_VECT(SDHI0, 0xEA0), 690 INTC_VECT(SDHI0, 0xEC0), 691 692 INTC_VECT(CMT_CMTI,0xF00), 693 INTC_VECT(TSIF_TSIFI,0xF20), 694 INTC_VECT(SIU_SIUI,0xF80), 695 INTC_VECT(SCIFA_SCIFA2,0xFA0), 696 697 INTC_VECT(TMU0_TUNI0,0x400), 698 INTC_VECT(TMU0_TUNI1,0x420), 699 INTC_VECT(TMU0_TUNI2,0x440), 700 701 INTC_VECT(IRDA_IRDAI,0x480), 702 INTC_VECT(ATAPI_ATAPII,0x4A0), 703 704 INTC_VECT(SDHI1, 0x4E0), 705 INTC_VECT(SDHI1, 0x500), 706 INTC_VECT(SDHI1, 0x520), 707 708 INTC_VECT(VEU2H1_VEU2HI,0x560), 709 INTC_VECT(LCDC_LCDCI,0x580), 710 711 INTC_VECT(TMU1_TUNI0,0x920), 712 INTC_VECT(TMU1_TUNI1,0x940), 713 INTC_VECT(TMU1_TUNI2,0x960), 714 715 }; 716 717 static struct intc_group groups[] __initdata = { 718 INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3), 719 INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3), 720 INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI), 721 INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR), 722 INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I), 723 INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI), 724 INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI), 725 INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI), 726 INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR), 727 }; 728 729 static struct intc_mask_reg mask_registers[] __initdata = { 730 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 731 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, 732 0, ENABLED, ENABLED, ENABLED } }, 733 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 734 { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } }, 735 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 736 { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } }, 737 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 738 { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } }, 739 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 740 { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } }, 741 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 742 { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } }, 743 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 744 { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } }, 745 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 746 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 747 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, 748 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 749 { 0, ENABLED, ENABLED, ENABLED, 750 0, 0, SCIFA_SCIFA2, SIU_SIUI } }, 751 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 752 { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } }, 753 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 754 { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } }, 755 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 756 { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } }, 757 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */ 758 { 0,0,0,0,0,0,0,ATAPI_ATAPII } }, 759 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 760 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 761 }; 762 763 static struct intc_prio_reg prio_registers[] __initdata = { 764 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } }, 765 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} }, 766 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} }, 767 { 0xa408000c, 0, 16, 4, /* IPRD */ { } }, 768 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } }, 769 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } }, 770 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } }, 771 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } }, 772 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } }, 773 { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } }, 774 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } }, 775 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } }, 776 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 777 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 778 }; 779 780 static struct intc_sense_reg sense_registers[] __initdata = { 781 { 0xa414001c, 16, 2, /* ICR1 */ 782 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 783 }; 784 785 static struct intc_mask_reg ack_registers[] __initdata = { 786 { 0xa4140024, 0, 8, /* INTREQ00 */ 787 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 788 }; 789 790 static struct intc_desc intc_desc __initdata = { 791 .name = "sh7723", 792 .force_enable = ENABLED, 793 .force_disable = DISABLED, 794 .hw = INTC_HW_DESC(vectors, groups, mask_registers, 795 prio_registers, sense_registers, ack_registers), 796 }; 797 798 void __init plat_irq_setup(void) 799 { 800 register_intc_controller(&intc_desc); 801 } 802