1 /* 2 * SH7723 Setup 3 * 4 * Copyright (C) 2008 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/mm.h> 14 #include <linux/serial_sci.h> 15 #include <linux/uio_driver.h> 16 #include <linux/usb/r8a66597.h> 17 #include <linux/sh_timer.h> 18 #include <linux/io.h> 19 #include <asm/clock.h> 20 #include <asm/mmzone.h> 21 #include <cpu/sh7723.h> 22 23 /* Serial */ 24 static struct plat_sci_port scif0_platform_data = { 25 .mapbase = 0xffe00000, 26 .flags = UPF_BOOT_AUTOCONF, 27 .type = PORT_SCIF, 28 .irqs = { 80, 80, 80, 80 }, 29 }; 30 31 static struct platform_device scif0_device = { 32 .name = "sh-sci", 33 .id = 0, 34 .dev = { 35 .platform_data = &scif0_platform_data, 36 }, 37 }; 38 39 static struct plat_sci_port scif1_platform_data = { 40 .mapbase = 0xffe10000, 41 .flags = UPF_BOOT_AUTOCONF, 42 .type = PORT_SCIF, 43 .irqs = { 81, 81, 81, 81 }, 44 }; 45 46 static struct platform_device scif1_device = { 47 .name = "sh-sci", 48 .id = 1, 49 .dev = { 50 .platform_data = &scif1_platform_data, 51 }, 52 }; 53 54 static struct plat_sci_port scif2_platform_data = { 55 .mapbase = 0xffe20000, 56 .flags = UPF_BOOT_AUTOCONF, 57 .type = PORT_SCIF, 58 .irqs = { 82, 82, 82, 82 }, 59 }; 60 61 static struct platform_device scif2_device = { 62 .name = "sh-sci", 63 .id = 2, 64 .dev = { 65 .platform_data = &scif2_platform_data, 66 }, 67 }; 68 69 static struct plat_sci_port scif3_platform_data = { 70 .mapbase = 0xa4e30000, 71 .flags = UPF_BOOT_AUTOCONF, 72 .type = PORT_SCIFA, 73 .irqs = { 56, 56, 56, 56 }, 74 }; 75 76 static struct platform_device scif3_device = { 77 .name = "sh-sci", 78 .id = 3, 79 .dev = { 80 .platform_data = &scif3_platform_data, 81 }, 82 }; 83 84 static struct plat_sci_port scif4_platform_data = { 85 .mapbase = 0xa4e40000, 86 .flags = UPF_BOOT_AUTOCONF, 87 .type = PORT_SCIFA, 88 .irqs = { 88, 88, 88, 88 }, 89 }; 90 91 static struct platform_device scif4_device = { 92 .name = "sh-sci", 93 .id = 4, 94 .dev = { 95 .platform_data = &scif4_platform_data, 96 }, 97 }; 98 99 static struct plat_sci_port scif5_platform_data = { 100 .mapbase = 0xa4e50000, 101 .flags = UPF_BOOT_AUTOCONF, 102 .type = PORT_SCIFA, 103 .irqs = { 109, 109, 109, 109 }, 104 }; 105 106 static struct platform_device scif5_device = { 107 .name = "sh-sci", 108 .id = 5, 109 .dev = { 110 .platform_data = &scif5_platform_data, 111 }, 112 }; 113 114 static struct uio_info vpu_platform_data = { 115 .name = "VPU5", 116 .version = "0", 117 .irq = 60, 118 }; 119 120 static struct resource vpu_resources[] = { 121 [0] = { 122 .name = "VPU", 123 .start = 0xfe900000, 124 .end = 0xfe902807, 125 .flags = IORESOURCE_MEM, 126 }, 127 [1] = { 128 /* place holder for contiguous memory */ 129 }, 130 }; 131 132 static struct platform_device vpu_device = { 133 .name = "uio_pdrv_genirq", 134 .id = 0, 135 .dev = { 136 .platform_data = &vpu_platform_data, 137 }, 138 .resource = vpu_resources, 139 .num_resources = ARRAY_SIZE(vpu_resources), 140 .archdata = { 141 .hwblk_id = HWBLK_VPU, 142 }, 143 }; 144 145 static struct uio_info veu0_platform_data = { 146 .name = "VEU2H", 147 .version = "0", 148 .irq = 54, 149 }; 150 151 static struct resource veu0_resources[] = { 152 [0] = { 153 .name = "VEU2H0", 154 .start = 0xfe920000, 155 .end = 0xfe92027b, 156 .flags = IORESOURCE_MEM, 157 }, 158 [1] = { 159 /* place holder for contiguous memory */ 160 }, 161 }; 162 163 static struct platform_device veu0_device = { 164 .name = "uio_pdrv_genirq", 165 .id = 1, 166 .dev = { 167 .platform_data = &veu0_platform_data, 168 }, 169 .resource = veu0_resources, 170 .num_resources = ARRAY_SIZE(veu0_resources), 171 .archdata = { 172 .hwblk_id = HWBLK_VEU2H0, 173 }, 174 }; 175 176 static struct uio_info veu1_platform_data = { 177 .name = "VEU2H", 178 .version = "0", 179 .irq = 27, 180 }; 181 182 static struct resource veu1_resources[] = { 183 [0] = { 184 .name = "VEU2H1", 185 .start = 0xfe924000, 186 .end = 0xfe92427b, 187 .flags = IORESOURCE_MEM, 188 }, 189 [1] = { 190 /* place holder for contiguous memory */ 191 }, 192 }; 193 194 static struct platform_device veu1_device = { 195 .name = "uio_pdrv_genirq", 196 .id = 2, 197 .dev = { 198 .platform_data = &veu1_platform_data, 199 }, 200 .resource = veu1_resources, 201 .num_resources = ARRAY_SIZE(veu1_resources), 202 .archdata = { 203 .hwblk_id = HWBLK_VEU2H1, 204 }, 205 }; 206 207 static struct sh_timer_config cmt_platform_data = { 208 .channel_offset = 0x60, 209 .timer_bit = 5, 210 .clockevent_rating = 125, 211 .clocksource_rating = 125, 212 }; 213 214 static struct resource cmt_resources[] = { 215 [0] = { 216 .start = 0x044a0060, 217 .end = 0x044a006b, 218 .flags = IORESOURCE_MEM, 219 }, 220 [1] = { 221 .start = 104, 222 .flags = IORESOURCE_IRQ, 223 }, 224 }; 225 226 static struct platform_device cmt_device = { 227 .name = "sh_cmt", 228 .id = 0, 229 .dev = { 230 .platform_data = &cmt_platform_data, 231 }, 232 .resource = cmt_resources, 233 .num_resources = ARRAY_SIZE(cmt_resources), 234 .archdata = { 235 .hwblk_id = HWBLK_CMT, 236 }, 237 }; 238 239 static struct sh_timer_config tmu0_platform_data = { 240 .channel_offset = 0x04, 241 .timer_bit = 0, 242 .clockevent_rating = 200, 243 }; 244 245 static struct resource tmu0_resources[] = { 246 [0] = { 247 .start = 0xffd80008, 248 .end = 0xffd80013, 249 .flags = IORESOURCE_MEM, 250 }, 251 [1] = { 252 .start = 16, 253 .flags = IORESOURCE_IRQ, 254 }, 255 }; 256 257 static struct platform_device tmu0_device = { 258 .name = "sh_tmu", 259 .id = 0, 260 .dev = { 261 .platform_data = &tmu0_platform_data, 262 }, 263 .resource = tmu0_resources, 264 .num_resources = ARRAY_SIZE(tmu0_resources), 265 .archdata = { 266 .hwblk_id = HWBLK_TMU0, 267 }, 268 }; 269 270 static struct sh_timer_config tmu1_platform_data = { 271 .channel_offset = 0x10, 272 .timer_bit = 1, 273 .clocksource_rating = 200, 274 }; 275 276 static struct resource tmu1_resources[] = { 277 [0] = { 278 .start = 0xffd80014, 279 .end = 0xffd8001f, 280 .flags = IORESOURCE_MEM, 281 }, 282 [1] = { 283 .start = 17, 284 .flags = IORESOURCE_IRQ, 285 }, 286 }; 287 288 static struct platform_device tmu1_device = { 289 .name = "sh_tmu", 290 .id = 1, 291 .dev = { 292 .platform_data = &tmu1_platform_data, 293 }, 294 .resource = tmu1_resources, 295 .num_resources = ARRAY_SIZE(tmu1_resources), 296 .archdata = { 297 .hwblk_id = HWBLK_TMU0, 298 }, 299 }; 300 301 static struct sh_timer_config tmu2_platform_data = { 302 .channel_offset = 0x1c, 303 .timer_bit = 2, 304 }; 305 306 static struct resource tmu2_resources[] = { 307 [0] = { 308 .start = 0xffd80020, 309 .end = 0xffd8002b, 310 .flags = IORESOURCE_MEM, 311 }, 312 [1] = { 313 .start = 18, 314 .flags = IORESOURCE_IRQ, 315 }, 316 }; 317 318 static struct platform_device tmu2_device = { 319 .name = "sh_tmu", 320 .id = 2, 321 .dev = { 322 .platform_data = &tmu2_platform_data, 323 }, 324 .resource = tmu2_resources, 325 .num_resources = ARRAY_SIZE(tmu2_resources), 326 .archdata = { 327 .hwblk_id = HWBLK_TMU0, 328 }, 329 }; 330 331 static struct sh_timer_config tmu3_platform_data = { 332 .channel_offset = 0x04, 333 .timer_bit = 0, 334 }; 335 336 static struct resource tmu3_resources[] = { 337 [0] = { 338 .start = 0xffd90008, 339 .end = 0xffd90013, 340 .flags = IORESOURCE_MEM, 341 }, 342 [1] = { 343 .start = 57, 344 .flags = IORESOURCE_IRQ, 345 }, 346 }; 347 348 static struct platform_device tmu3_device = { 349 .name = "sh_tmu", 350 .id = 3, 351 .dev = { 352 .platform_data = &tmu3_platform_data, 353 }, 354 .resource = tmu3_resources, 355 .num_resources = ARRAY_SIZE(tmu3_resources), 356 .archdata = { 357 .hwblk_id = HWBLK_TMU1, 358 }, 359 }; 360 361 static struct sh_timer_config tmu4_platform_data = { 362 .channel_offset = 0x10, 363 .timer_bit = 1, 364 }; 365 366 static struct resource tmu4_resources[] = { 367 [0] = { 368 .start = 0xffd90014, 369 .end = 0xffd9001f, 370 .flags = IORESOURCE_MEM, 371 }, 372 [1] = { 373 .start = 58, 374 .flags = IORESOURCE_IRQ, 375 }, 376 }; 377 378 static struct platform_device tmu4_device = { 379 .name = "sh_tmu", 380 .id = 4, 381 .dev = { 382 .platform_data = &tmu4_platform_data, 383 }, 384 .resource = tmu4_resources, 385 .num_resources = ARRAY_SIZE(tmu4_resources), 386 .archdata = { 387 .hwblk_id = HWBLK_TMU1, 388 }, 389 }; 390 391 static struct sh_timer_config tmu5_platform_data = { 392 .channel_offset = 0x1c, 393 .timer_bit = 2, 394 }; 395 396 static struct resource tmu5_resources[] = { 397 [0] = { 398 .start = 0xffd90020, 399 .end = 0xffd9002b, 400 .flags = IORESOURCE_MEM, 401 }, 402 [1] = { 403 .start = 57, 404 .flags = IORESOURCE_IRQ, 405 }, 406 }; 407 408 static struct platform_device tmu5_device = { 409 .name = "sh_tmu", 410 .id = 5, 411 .dev = { 412 .platform_data = &tmu5_platform_data, 413 }, 414 .resource = tmu5_resources, 415 .num_resources = ARRAY_SIZE(tmu5_resources), 416 .archdata = { 417 .hwblk_id = HWBLK_TMU1, 418 }, 419 }; 420 421 static struct resource rtc_resources[] = { 422 [0] = { 423 .start = 0xa465fec0, 424 .end = 0xa465fec0 + 0x58 - 1, 425 .flags = IORESOURCE_IO, 426 }, 427 [1] = { 428 /* Period IRQ */ 429 .start = 69, 430 .flags = IORESOURCE_IRQ, 431 }, 432 [2] = { 433 /* Carry IRQ */ 434 .start = 70, 435 .flags = IORESOURCE_IRQ, 436 }, 437 [3] = { 438 /* Alarm IRQ */ 439 .start = 68, 440 .flags = IORESOURCE_IRQ, 441 }, 442 }; 443 444 static struct platform_device rtc_device = { 445 .name = "sh-rtc", 446 .id = -1, 447 .num_resources = ARRAY_SIZE(rtc_resources), 448 .resource = rtc_resources, 449 .archdata = { 450 .hwblk_id = HWBLK_RTC, 451 }, 452 }; 453 454 static struct r8a66597_platdata r8a66597_data = { 455 .on_chip = 1, 456 }; 457 458 static struct resource sh7723_usb_host_resources[] = { 459 [0] = { 460 .start = 0xa4d80000, 461 .end = 0xa4d800ff, 462 .flags = IORESOURCE_MEM, 463 }, 464 [1] = { 465 .start = 65, 466 .end = 65, 467 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, 468 }, 469 }; 470 471 static struct platform_device sh7723_usb_host_device = { 472 .name = "r8a66597_hcd", 473 .id = 0, 474 .dev = { 475 .dma_mask = NULL, /* not use dma */ 476 .coherent_dma_mask = 0xffffffff, 477 .platform_data = &r8a66597_data, 478 }, 479 .num_resources = ARRAY_SIZE(sh7723_usb_host_resources), 480 .resource = sh7723_usb_host_resources, 481 .archdata = { 482 .hwblk_id = HWBLK_USB, 483 }, 484 }; 485 486 static struct resource iic_resources[] = { 487 [0] = { 488 .name = "IIC", 489 .start = 0x04470000, 490 .end = 0x04470017, 491 .flags = IORESOURCE_MEM, 492 }, 493 [1] = { 494 .start = 96, 495 .end = 99, 496 .flags = IORESOURCE_IRQ, 497 }, 498 }; 499 500 static struct platform_device iic_device = { 501 .name = "i2c-sh_mobile", 502 .id = 0, /* "i2c0" clock */ 503 .num_resources = ARRAY_SIZE(iic_resources), 504 .resource = iic_resources, 505 .archdata = { 506 .hwblk_id = HWBLK_IIC, 507 }, 508 }; 509 510 static struct platform_device *sh7723_devices[] __initdata = { 511 &scif0_device, 512 &scif1_device, 513 &scif2_device, 514 &scif3_device, 515 &scif4_device, 516 &scif5_device, 517 &cmt_device, 518 &tmu0_device, 519 &tmu1_device, 520 &tmu2_device, 521 &tmu3_device, 522 &tmu4_device, 523 &tmu5_device, 524 &rtc_device, 525 &iic_device, 526 &sh7723_usb_host_device, 527 &vpu_device, 528 &veu0_device, 529 &veu1_device, 530 }; 531 532 static int __init sh7723_devices_setup(void) 533 { 534 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 535 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 536 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 537 538 return platform_add_devices(sh7723_devices, 539 ARRAY_SIZE(sh7723_devices)); 540 } 541 arch_initcall(sh7723_devices_setup); 542 543 static struct platform_device *sh7723_early_devices[] __initdata = { 544 &scif0_device, 545 &scif1_device, 546 &scif2_device, 547 &scif3_device, 548 &scif4_device, 549 &scif5_device, 550 &cmt_device, 551 &tmu0_device, 552 &tmu1_device, 553 &tmu2_device, 554 &tmu3_device, 555 &tmu4_device, 556 &tmu5_device, 557 }; 558 559 void __init plat_early_device_setup(void) 560 { 561 early_platform_add_devices(sh7723_early_devices, 562 ARRAY_SIZE(sh7723_early_devices)); 563 } 564 565 #define RAMCR_CACHE_L2FC 0x0002 566 #define RAMCR_CACHE_L2E 0x0001 567 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) 568 569 void l2_cache_init(void) 570 { 571 /* Enable L2 cache */ 572 __raw_writel(L2_CACHE_ENABLE, RAMCR); 573 } 574 575 enum { 576 UNUSED=0, 577 ENABLED, 578 DISABLED, 579 580 /* interrupt sources */ 581 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 582 HUDI, 583 DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3, 584 _2DG_TRI,_2DG_INI,_2DG_CEI, 585 DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3, 586 VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI, 587 SCIFA_SCIFA0, 588 VPU_VPUI, 589 TPU_TPUI, 590 ADC_ADI, 591 USB_USI0, 592 RTC_ATI,RTC_PRI,RTC_CUI, 593 DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR, 594 DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR, 595 KEYSC_KEYI, 596 SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2, 597 MSIOF_MSIOFI0,MSIOF_MSIOFI1, 598 SCIFA_SCIFA1, 599 FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I, 600 I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI, 601 CMT_CMTI, 602 TSIF_TSIFI, 603 SIU_SIUI, 604 SCIFA_SCIFA2, 605 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, 606 IRDA_IRDAI, 607 ATAPI_ATAPII, 608 VEU2H1_VEU2HI, 609 LCDC_LCDCI, 610 TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2, 611 612 /* interrupt groups */ 613 DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG, 614 SDHI1, RTC, DMAC1B, SDHI0, 615 }; 616 617 static struct intc_vect vectors[] __initdata = { 618 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 619 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 620 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 621 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 622 623 INTC_VECT(DMAC1A_DEI0,0x700), 624 INTC_VECT(DMAC1A_DEI1,0x720), 625 INTC_VECT(DMAC1A_DEI2,0x740), 626 INTC_VECT(DMAC1A_DEI3,0x760), 627 628 INTC_VECT(_2DG_TRI, 0x780), 629 INTC_VECT(_2DG_INI, 0x7A0), 630 INTC_VECT(_2DG_CEI, 0x7C0), 631 632 INTC_VECT(DMAC0A_DEI0,0x800), 633 INTC_VECT(DMAC0A_DEI1,0x820), 634 INTC_VECT(DMAC0A_DEI2,0x840), 635 INTC_VECT(DMAC0A_DEI3,0x860), 636 637 INTC_VECT(VIO_CEUI,0x880), 638 INTC_VECT(VIO_BEUI,0x8A0), 639 INTC_VECT(VIO_VEU2HI,0x8C0), 640 INTC_VECT(VIO_VOUI,0x8E0), 641 642 INTC_VECT(SCIFA_SCIFA0,0x900), 643 INTC_VECT(VPU_VPUI,0x980), 644 INTC_VECT(TPU_TPUI,0x9A0), 645 INTC_VECT(ADC_ADI,0x9E0), 646 INTC_VECT(USB_USI0,0xA20), 647 648 INTC_VECT(RTC_ATI,0xA80), 649 INTC_VECT(RTC_PRI,0xAA0), 650 INTC_VECT(RTC_CUI,0xAC0), 651 652 INTC_VECT(DMAC1B_DEI4,0xB00), 653 INTC_VECT(DMAC1B_DEI5,0xB20), 654 INTC_VECT(DMAC1B_DADERR,0xB40), 655 656 INTC_VECT(DMAC0B_DEI4,0xB80), 657 INTC_VECT(DMAC0B_DEI5,0xBA0), 658 INTC_VECT(DMAC0B_DADERR,0xBC0), 659 660 INTC_VECT(KEYSC_KEYI,0xBE0), 661 INTC_VECT(SCIF_SCIF0,0xC00), 662 INTC_VECT(SCIF_SCIF1,0xC20), 663 INTC_VECT(SCIF_SCIF2,0xC40), 664 INTC_VECT(MSIOF_MSIOFI0,0xC80), 665 INTC_VECT(MSIOF_MSIOFI1,0xCA0), 666 INTC_VECT(SCIFA_SCIFA1,0xD00), 667 668 INTC_VECT(FLCTL_FLSTEI,0xD80), 669 INTC_VECT(FLCTL_FLTENDI,0xDA0), 670 INTC_VECT(FLCTL_FLTREQ0I,0xDC0), 671 INTC_VECT(FLCTL_FLTREQ1I,0xDE0), 672 673 INTC_VECT(I2C_ALI,0xE00), 674 INTC_VECT(I2C_TACKI,0xE20), 675 INTC_VECT(I2C_WAITI,0xE40), 676 INTC_VECT(I2C_DTEI,0xE60), 677 678 INTC_VECT(SDHI0, 0xE80), 679 INTC_VECT(SDHI0, 0xEA0), 680 INTC_VECT(SDHI0, 0xEC0), 681 682 INTC_VECT(CMT_CMTI,0xF00), 683 INTC_VECT(TSIF_TSIFI,0xF20), 684 INTC_VECT(SIU_SIUI,0xF80), 685 INTC_VECT(SCIFA_SCIFA2,0xFA0), 686 687 INTC_VECT(TMU0_TUNI0,0x400), 688 INTC_VECT(TMU0_TUNI1,0x420), 689 INTC_VECT(TMU0_TUNI2,0x440), 690 691 INTC_VECT(IRDA_IRDAI,0x480), 692 INTC_VECT(ATAPI_ATAPII,0x4A0), 693 694 INTC_VECT(SDHI1, 0x4E0), 695 INTC_VECT(SDHI1, 0x500), 696 INTC_VECT(SDHI1, 0x520), 697 698 INTC_VECT(VEU2H1_VEU2HI,0x560), 699 INTC_VECT(LCDC_LCDCI,0x580), 700 701 INTC_VECT(TMU1_TUNI0,0x920), 702 INTC_VECT(TMU1_TUNI1,0x940), 703 INTC_VECT(TMU1_TUNI2,0x960), 704 705 }; 706 707 static struct intc_group groups[] __initdata = { 708 INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3), 709 INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3), 710 INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI), 711 INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR), 712 INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I), 713 INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI), 714 INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI), 715 INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI), 716 INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR), 717 }; 718 719 static struct intc_mask_reg mask_registers[] __initdata = { 720 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 721 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, 722 0, DISABLED, ENABLED, ENABLED } }, 723 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 724 { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } }, 725 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 726 { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } }, 727 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 728 { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } }, 729 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 730 { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } }, 731 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 732 { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } }, 733 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 734 { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } }, 735 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 736 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 737 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, 738 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 739 { 0, DISABLED, ENABLED, ENABLED, 740 0, 0, SCIFA_SCIFA2, SIU_SIUI } }, 741 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 742 { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } }, 743 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 744 { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } }, 745 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 746 { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } }, 747 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */ 748 { 0,0,0,0,0,0,0,ATAPI_ATAPII } }, 749 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 750 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 751 }; 752 753 static struct intc_prio_reg prio_registers[] __initdata = { 754 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } }, 755 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} }, 756 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} }, 757 { 0xa408000c, 0, 16, 4, /* IPRD */ { } }, 758 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } }, 759 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } }, 760 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } }, 761 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } }, 762 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } }, 763 { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } }, 764 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } }, 765 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } }, 766 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 767 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 768 }; 769 770 static struct intc_sense_reg sense_registers[] __initdata = { 771 { 0xa414001c, 16, 2, /* ICR1 */ 772 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 773 }; 774 775 static struct intc_mask_reg ack_registers[] __initdata = { 776 { 0xa4140024, 0, 8, /* INTREQ00 */ 777 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 778 }; 779 780 static struct intc_desc intc_desc __initdata = { 781 .name = "sh7723", 782 .force_enable = ENABLED, 783 .force_disable = DISABLED, 784 .hw = INTC_HW_DESC(vectors, groups, mask_registers, 785 prio_registers, sense_registers, ack_registers), 786 }; 787 788 void __init plat_irq_setup(void) 789 { 790 register_intc_controller(&intc_desc); 791 } 792