1 /* 2 * SH7723 Setup 3 * 4 * Copyright (C) 2008 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/mm.h> 14 #include <linux/serial_sci.h> 15 #include <asm/mmzone.h> 16 17 static struct plat_sci_port sci_platform_data[] = { 18 { 19 .mapbase = 0xffe00000, 20 .flags = UPF_BOOT_AUTOCONF, 21 .type = PORT_SCIF, 22 .irqs = { 80, 80, 80, 80 }, 23 },{ 24 .mapbase = 0xffe10000, 25 .flags = UPF_BOOT_AUTOCONF, 26 .type = PORT_SCIF, 27 .irqs = { 81, 81, 81, 81 }, 28 },{ 29 .mapbase = 0xffe20000, 30 .flags = UPF_BOOT_AUTOCONF, 31 .type = PORT_SCIF, 32 .irqs = { 82, 82, 82, 82 }, 33 },{ 34 .mapbase = 0xa4e30000, 35 .flags = UPF_BOOT_AUTOCONF, 36 .type = PORT_SCI, 37 .irqs = { 56, 56, 56, 56 }, 38 },{ 39 .mapbase = 0xa4e40000, 40 .flags = UPF_BOOT_AUTOCONF, 41 .type = PORT_SCI, 42 .irqs = { 88, 88, 88, 88 }, 43 },{ 44 .mapbase = 0xa4e50000, 45 .flags = UPF_BOOT_AUTOCONF, 46 .type = PORT_SCI, 47 .irqs = { 109, 109, 109, 109 }, 48 }, { 49 .flags = 0, 50 } 51 }; 52 53 static struct platform_device sci_device = { 54 .name = "sh-sci", 55 .id = -1, 56 .dev = { 57 .platform_data = sci_platform_data, 58 }, 59 }; 60 61 static struct resource rtc_resources[] = { 62 [0] = { 63 .start = 0xa465fec0, 64 .end = 0xa465fec0 + 0x58 - 1, 65 .flags = IORESOURCE_IO, 66 }, 67 [1] = { 68 /* Period IRQ */ 69 .start = 69, 70 .flags = IORESOURCE_IRQ, 71 }, 72 [2] = { 73 /* Carry IRQ */ 74 .start = 70, 75 .flags = IORESOURCE_IRQ, 76 }, 77 [3] = { 78 /* Alarm IRQ */ 79 .start = 68, 80 .flags = IORESOURCE_IRQ, 81 }, 82 }; 83 84 static struct platform_device rtc_device = { 85 .name = "sh-rtc", 86 .id = -1, 87 .num_resources = ARRAY_SIZE(rtc_resources), 88 .resource = rtc_resources, 89 }; 90 91 static struct resource sh7723_usb_host_resources[] = { 92 [0] = { 93 .name = "r8a66597_hcd", 94 .start = 0xa4d80000, 95 .end = 0xa4d800ff, 96 .flags = IORESOURCE_MEM, 97 }, 98 [1] = { 99 .start = 65, 100 .end = 65, 101 .flags = IORESOURCE_IRQ, 102 }, 103 }; 104 105 static struct platform_device sh7723_usb_host_device = { 106 .name = "r8a66597_hcd", 107 .id = 0, 108 .dev = { 109 .dma_mask = NULL, /* not use dma */ 110 .coherent_dma_mask = 0xffffffff, 111 }, 112 .num_resources = ARRAY_SIZE(sh7723_usb_host_resources), 113 .resource = sh7723_usb_host_resources, 114 }; 115 116 static struct platform_device *sh7723_devices[] __initdata = { 117 &sci_device, 118 &rtc_device, 119 &sh7723_usb_host_device, 120 }; 121 122 static int __init sh7723_devices_setup(void) 123 { 124 return platform_add_devices(sh7723_devices, 125 ARRAY_SIZE(sh7723_devices)); 126 } 127 __initcall(sh7723_devices_setup); 128 129 enum { 130 UNUSED=0, 131 132 /* interrupt sources */ 133 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 134 HUDI, 135 DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3, 136 _2DG_TRI,_2DG_INI,_2DG_CEI, 137 DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3, 138 VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI, 139 SCIFA_SCIFA0, 140 VPU_VPUI, 141 TPU_TPUI, 142 ADC_ADI, 143 USB_USI0, 144 RTC_ATI,RTC_PRI,RTC_CUI, 145 DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR, 146 DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR, 147 KEYSC_KEYI, 148 SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2, 149 MSIOF_MSIOFI0,MSIOF_MSIOFI1, 150 SCIFA_SCIFA1, 151 FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I, 152 I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI, 153 SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2, 154 CMT_CMTI, 155 TSIF_TSIFI, 156 SIU_SIUI, 157 SCIFA_SCIFA2, 158 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, 159 IRDA_IRDAI, 160 ATAPI_ATAPII, 161 SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2, 162 VEU2H1_VEU2HI, 163 LCDC_LCDCI, 164 TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2, 165 166 /* interrupt groups */ 167 DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG, 168 SDHI1, RTC, DMAC1B, SDHI0, 169 }; 170 171 static struct intc_vect vectors[] __initdata = { 172 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 173 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 174 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 175 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 176 177 INTC_VECT(DMAC1A_DEI0,0x700), 178 INTC_VECT(DMAC1A_DEI1,0x720), 179 INTC_VECT(DMAC1A_DEI2,0x740), 180 INTC_VECT(DMAC1A_DEI3,0x760), 181 182 INTC_VECT(_2DG_TRI, 0x780), 183 INTC_VECT(_2DG_INI, 0x7A0), 184 INTC_VECT(_2DG_CEI, 0x7C0), 185 186 INTC_VECT(DMAC0A_DEI0,0x800), 187 INTC_VECT(DMAC0A_DEI1,0x820), 188 INTC_VECT(DMAC0A_DEI2,0x840), 189 INTC_VECT(DMAC0A_DEI3,0x860), 190 191 INTC_VECT(VIO_CEUI,0x880), 192 INTC_VECT(VIO_BEUI,0x8A0), 193 INTC_VECT(VIO_VEU2HI,0x8C0), 194 INTC_VECT(VIO_VOUI,0x8E0), 195 196 INTC_VECT(SCIFA_SCIFA0,0x900), 197 INTC_VECT(VPU_VPUI,0x980), 198 INTC_VECT(TPU_TPUI,0x9A0), 199 INTC_VECT(ADC_ADI,0x9E0), 200 INTC_VECT(USB_USI0,0xA20), 201 202 INTC_VECT(RTC_ATI,0xA80), 203 INTC_VECT(RTC_PRI,0xAA0), 204 INTC_VECT(RTC_CUI,0xAC0), 205 206 INTC_VECT(DMAC1B_DEI4,0xB00), 207 INTC_VECT(DMAC1B_DEI5,0xB20), 208 INTC_VECT(DMAC1B_DADERR,0xB40), 209 210 INTC_VECT(DMAC0B_DEI4,0xB80), 211 INTC_VECT(DMAC0B_DEI5,0xBA0), 212 INTC_VECT(DMAC0B_DADERR,0xBC0), 213 214 INTC_VECT(KEYSC_KEYI,0xBE0), 215 INTC_VECT(SCIF_SCIF0,0xC00), 216 INTC_VECT(SCIF_SCIF1,0xC20), 217 INTC_VECT(SCIF_SCIF2,0xC40), 218 INTC_VECT(MSIOF_MSIOFI0,0xC80), 219 INTC_VECT(MSIOF_MSIOFI1,0xCA0), 220 INTC_VECT(SCIFA_SCIFA1,0xD00), 221 222 INTC_VECT(FLCTL_FLSTEI,0xD80), 223 INTC_VECT(FLCTL_FLTENDI,0xDA0), 224 INTC_VECT(FLCTL_FLTREQ0I,0xDC0), 225 INTC_VECT(FLCTL_FLTREQ1I,0xDE0), 226 227 INTC_VECT(I2C_ALI,0xE00), 228 INTC_VECT(I2C_TACKI,0xE20), 229 INTC_VECT(I2C_WAITI,0xE40), 230 INTC_VECT(I2C_DTEI,0xE60), 231 232 INTC_VECT(SDHI0_SDHII0,0xE80), 233 INTC_VECT(SDHI0_SDHII1,0xEA0), 234 INTC_VECT(SDHI0_SDHII2,0xEC0), 235 236 INTC_VECT(CMT_CMTI,0xF00), 237 INTC_VECT(TSIF_TSIFI,0xF20), 238 INTC_VECT(SIU_SIUI,0xF80), 239 INTC_VECT(SCIFA_SCIFA2,0xFA0), 240 241 INTC_VECT(TMU0_TUNI0,0x400), 242 INTC_VECT(TMU0_TUNI1,0x420), 243 INTC_VECT(TMU0_TUNI2,0x440), 244 245 INTC_VECT(IRDA_IRDAI,0x480), 246 INTC_VECT(ATAPI_ATAPII,0x4A0), 247 248 INTC_VECT(SDHI1_SDHII0,0x4E0), 249 INTC_VECT(SDHI1_SDHII1,0x500), 250 INTC_VECT(SDHI1_SDHII2,0x520), 251 252 INTC_VECT(VEU2H1_VEU2HI,0x560), 253 INTC_VECT(LCDC_LCDCI,0x580), 254 255 INTC_VECT(TMU1_TUNI0,0x920), 256 INTC_VECT(TMU1_TUNI1,0x940), 257 INTC_VECT(TMU1_TUNI2,0x960), 258 259 }; 260 261 static struct intc_group groups[] __initdata = { 262 INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3), 263 INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3), 264 INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI), 265 INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR), 266 INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I), 267 INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI), 268 INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI), 269 INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2), 270 INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI), 271 INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR), 272 INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2), 273 }; 274 275 static struct intc_mask_reg mask_registers[] __initdata = { 276 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 277 { 0, TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} }, 278 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 279 { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } }, 280 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 281 { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } }, 282 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 283 { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } }, 284 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 285 { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } }, 286 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 287 { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } }, 288 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 289 { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } }, 290 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 291 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 292 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, 293 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 294 { 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } }, 295 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 296 { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } }, 297 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 298 { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } }, 299 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 300 { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } }, 301 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */ 302 { 0,0,0,0,0,0,0,ATAPI_ATAPII } }, 303 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 304 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 305 }; 306 307 static struct intc_prio_reg prio_registers[] __initdata = { 308 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } }, 309 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} }, 310 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} }, 311 { 0xa408000c, 0, 16, 4, /* IPRD */ { } }, 312 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } }, 313 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } }, 314 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } }, 315 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } }, 316 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } }, 317 { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } }, 318 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } }, 319 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } }, 320 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 321 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 322 }; 323 324 static struct intc_sense_reg sense_registers[] __initdata = { 325 { 0xa414001c, 16, 2, /* ICR1 */ 326 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 327 }; 328 329 static DECLARE_INTC_DESC(intc_desc, "sh7723", vectors, groups, 330 mask_registers, prio_registers, sense_registers); 331 332 void __init plat_irq_setup(void) 333 { 334 register_intc_controller(&intc_desc); 335 } 336