1 /*
2  * SH7722 Setup
3  *
4  *  Copyright (C) 2006 - 2008  Paul Mundt
5  *
6  * This file is subject to the terms and conditions of the GNU General Public
7  * License.  See the file "COPYING" in the main directory of this archive
8  * for more details.
9  */
10 #include <linux/init.h>
11 #include <linux/mm.h>
12 #include <linux/platform_device.h>
13 #include <linux/serial.h>
14 #include <linux/serial_sci.h>
15 #include <linux/sh_timer.h>
16 #include <linux/uio_driver.h>
17 #include <linux/usb/m66592.h>
18 
19 #include <asm/clock.h>
20 #include <asm/mmzone.h>
21 #include <asm/siu.h>
22 
23 #include <cpu/dma-register.h>
24 #include <cpu/sh7722.h>
25 #include <cpu/serial.h>
26 
27 static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
28 	{
29 		.slave_id	= SHDMA_SLAVE_SCIF0_TX,
30 		.addr		= 0xffe0000c,
31 		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
32 		.mid_rid	= 0x21,
33 	}, {
34 		.slave_id	= SHDMA_SLAVE_SCIF0_RX,
35 		.addr		= 0xffe00014,
36 		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
37 		.mid_rid	= 0x22,
38 	}, {
39 		.slave_id	= SHDMA_SLAVE_SCIF1_TX,
40 		.addr		= 0xffe1000c,
41 		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
42 		.mid_rid	= 0x25,
43 	}, {
44 		.slave_id	= SHDMA_SLAVE_SCIF1_RX,
45 		.addr		= 0xffe10014,
46 		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
47 		.mid_rid	= 0x26,
48 	}, {
49 		.slave_id	= SHDMA_SLAVE_SCIF2_TX,
50 		.addr		= 0xffe2000c,
51 		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
52 		.mid_rid	= 0x29,
53 	}, {
54 		.slave_id	= SHDMA_SLAVE_SCIF2_RX,
55 		.addr		= 0xffe20014,
56 		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
57 		.mid_rid	= 0x2a,
58 	}, {
59 		.slave_id	= SHDMA_SLAVE_SIUA_TX,
60 		.addr		= 0xa454c098,
61 		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
62 		.mid_rid	= 0xb1,
63 	}, {
64 		.slave_id	= SHDMA_SLAVE_SIUA_RX,
65 		.addr		= 0xa454c090,
66 		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
67 		.mid_rid	= 0xb2,
68 	}, {
69 		.slave_id	= SHDMA_SLAVE_SIUB_TX,
70 		.addr		= 0xa454c09c,
71 		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
72 		.mid_rid	= 0xb5,
73 	}, {
74 		.slave_id	= SHDMA_SLAVE_SIUB_RX,
75 		.addr		= 0xa454c094,
76 		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
77 		.mid_rid	= 0xb6,
78 	}, {
79 		.slave_id	= SHDMA_SLAVE_SDHI0_TX,
80 		.addr		= 0x04ce0030,
81 		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
82 		.mid_rid	= 0xc1,
83 	}, {
84 		.slave_id	= SHDMA_SLAVE_SDHI0_RX,
85 		.addr		= 0x04ce0030,
86 		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
87 		.mid_rid	= 0xc2,
88 	},
89 };
90 
91 static const struct sh_dmae_channel sh7722_dmae_channels[] = {
92 	{
93 		.offset = 0,
94 		.dmars = 0,
95 		.dmars_bit = 0,
96 	}, {
97 		.offset = 0x10,
98 		.dmars = 0,
99 		.dmars_bit = 8,
100 	}, {
101 		.offset = 0x20,
102 		.dmars = 4,
103 		.dmars_bit = 0,
104 	}, {
105 		.offset = 0x30,
106 		.dmars = 4,
107 		.dmars_bit = 8,
108 	}, {
109 		.offset = 0x50,
110 		.dmars = 8,
111 		.dmars_bit = 0,
112 	}, {
113 		.offset = 0x60,
114 		.dmars = 8,
115 		.dmars_bit = 8,
116 	}
117 };
118 
119 static const unsigned int ts_shift[] = TS_SHIFT;
120 
121 static struct sh_dmae_pdata dma_platform_data = {
122 	.slave		= sh7722_dmae_slaves,
123 	.slave_num	= ARRAY_SIZE(sh7722_dmae_slaves),
124 	.channel	= sh7722_dmae_channels,
125 	.channel_num	= ARRAY_SIZE(sh7722_dmae_channels),
126 	.ts_low_shift	= CHCR_TS_LOW_SHIFT,
127 	.ts_low_mask	= CHCR_TS_LOW_MASK,
128 	.ts_high_shift	= CHCR_TS_HIGH_SHIFT,
129 	.ts_high_mask	= CHCR_TS_HIGH_MASK,
130 	.ts_shift	= ts_shift,
131 	.ts_shift_num	= ARRAY_SIZE(ts_shift),
132 	.dmaor_init	= DMAOR_INIT,
133 };
134 
135 static struct resource sh7722_dmae_resources[] = {
136 	[0] = {
137 		/* Channel registers and DMAOR */
138 		.start	= 0xfe008020,
139 		.end	= 0xfe00808f,
140 		.flags	= IORESOURCE_MEM,
141 	},
142 	[1] = {
143 		/* DMARSx */
144 		.start	= 0xfe009000,
145 		.end	= 0xfe00900b,
146 		.flags	= IORESOURCE_MEM,
147 	},
148 	{
149 		/* DMA error IRQ */
150 		.start	= 78,
151 		.end	= 78,
152 		.flags	= IORESOURCE_IRQ,
153 	},
154 	{
155 		/* IRQ for channels 0-3 */
156 		.start	= 48,
157 		.end	= 51,
158 		.flags	= IORESOURCE_IRQ,
159 	},
160 	{
161 		/* IRQ for channels 4-5 */
162 		.start	= 76,
163 		.end	= 77,
164 		.flags	= IORESOURCE_IRQ,
165 	},
166 };
167 
168 struct platform_device dma_device = {
169 	.name		= "sh-dma-engine",
170 	.id		= -1,
171 	.resource	= sh7722_dmae_resources,
172 	.num_resources	= ARRAY_SIZE(sh7722_dmae_resources),
173 	.dev		= {
174 		.platform_data	= &dma_platform_data,
175 	},
176 	.archdata = {
177 		.hwblk_id = HWBLK_DMAC,
178 	},
179 };
180 
181 /* Serial */
182 static struct plat_sci_port scif0_platform_data = {
183 	.mapbase        = 0xffe00000,
184 	.flags          = UPF_BOOT_AUTOCONF,
185 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
186 	.scbrr_algo_id	= SCBRR_ALGO_2,
187 	.type           = PORT_SCIF,
188 	.irqs           = { 80, 80, 80, 80 },
189 	.ops		= &sh7722_sci_port_ops,
190 	.regtype	= SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
191 };
192 
193 static struct platform_device scif0_device = {
194 	.name		= "sh-sci",
195 	.id		= 0,
196 	.dev		= {
197 		.platform_data	= &scif0_platform_data,
198 	},
199 };
200 
201 static struct plat_sci_port scif1_platform_data = {
202 	.mapbase        = 0xffe10000,
203 	.flags          = UPF_BOOT_AUTOCONF,
204 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
205 	.scbrr_algo_id	= SCBRR_ALGO_2,
206 	.type           = PORT_SCIF,
207 	.irqs           = { 81, 81, 81, 81 },
208 	.ops		= &sh7722_sci_port_ops,
209 	.regtype	= SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
210 };
211 
212 static struct platform_device scif1_device = {
213 	.name		= "sh-sci",
214 	.id		= 1,
215 	.dev		= {
216 		.platform_data	= &scif1_platform_data,
217 	},
218 };
219 
220 static struct plat_sci_port scif2_platform_data = {
221 	.mapbase        = 0xffe20000,
222 	.flags          = UPF_BOOT_AUTOCONF,
223 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
224 	.scbrr_algo_id	= SCBRR_ALGO_2,
225 	.type           = PORT_SCIF,
226 	.irqs           = { 82, 82, 82, 82 },
227 	.ops		= &sh7722_sci_port_ops,
228 	.regtype	= SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
229 };
230 
231 static struct platform_device scif2_device = {
232 	.name		= "sh-sci",
233 	.id		= 2,
234 	.dev		= {
235 		.platform_data	= &scif2_platform_data,
236 	},
237 };
238 
239 static struct resource rtc_resources[] = {
240 	[0] = {
241 		.start	= 0xa465fec0,
242 		.end	= 0xa465fec0 + 0x58 - 1,
243 		.flags	= IORESOURCE_IO,
244 	},
245 	[1] = {
246 		/* Period IRQ */
247 		.start	= 45,
248 		.flags	= IORESOURCE_IRQ,
249 	},
250 	[2] = {
251 		/* Carry IRQ */
252 		.start	= 46,
253 		.flags	= IORESOURCE_IRQ,
254 	},
255 	[3] = {
256 		/* Alarm IRQ */
257 		.start	= 44,
258 		.flags	= IORESOURCE_IRQ,
259 	},
260 };
261 
262 static struct platform_device rtc_device = {
263 	.name		= "sh-rtc",
264 	.id		= -1,
265 	.num_resources	= ARRAY_SIZE(rtc_resources),
266 	.resource	= rtc_resources,
267 	.archdata = {
268 		.hwblk_id = HWBLK_RTC,
269 	},
270 };
271 
272 static struct m66592_platdata usbf_platdata = {
273 	.on_chip = 1,
274 };
275 
276 static struct resource usbf_resources[] = {
277 	[0] = {
278 		.name	= "USBF",
279 		.start	= 0x04480000,
280 		.end	= 0x044800FF,
281 		.flags	= IORESOURCE_MEM,
282 	},
283 	[1] = {
284 		.start	= 65,
285 		.end	= 65,
286 		.flags	= IORESOURCE_IRQ,
287 	},
288 };
289 
290 static struct platform_device usbf_device = {
291 	.name		= "m66592_udc",
292 	.id             = 0, /* "usbf0" clock */
293 	.dev = {
294 		.dma_mask		= NULL,
295 		.coherent_dma_mask	= 0xffffffff,
296 		.platform_data		= &usbf_platdata,
297 	},
298 	.num_resources	= ARRAY_SIZE(usbf_resources),
299 	.resource	= usbf_resources,
300 	.archdata = {
301 		.hwblk_id = HWBLK_USBF,
302 	},
303 };
304 
305 static struct resource iic_resources[] = {
306 	[0] = {
307 		.name	= "IIC",
308 		.start  = 0x04470000,
309 		.end    = 0x04470017,
310 		.flags  = IORESOURCE_MEM,
311 	},
312 	[1] = {
313 		.start  = 96,
314 		.end    = 99,
315 		.flags  = IORESOURCE_IRQ,
316        },
317 };
318 
319 static struct platform_device iic_device = {
320 	.name           = "i2c-sh_mobile",
321 	.id             = 0, /* "i2c0" clock */
322 	.num_resources  = ARRAY_SIZE(iic_resources),
323 	.resource       = iic_resources,
324 	.archdata = {
325 		.hwblk_id = HWBLK_IIC,
326 	},
327 };
328 
329 static struct uio_info vpu_platform_data = {
330 	.name = "VPU4",
331 	.version = "0",
332 	.irq = 60,
333 };
334 
335 static struct resource vpu_resources[] = {
336 	[0] = {
337 		.name	= "VPU",
338 		.start	= 0xfe900000,
339 		.end	= 0xfe9022eb,
340 		.flags	= IORESOURCE_MEM,
341 	},
342 	[1] = {
343 		/* place holder for contiguous memory */
344 	},
345 };
346 
347 static struct platform_device vpu_device = {
348 	.name		= "uio_pdrv_genirq",
349 	.id		= 0,
350 	.dev = {
351 		.platform_data	= &vpu_platform_data,
352 	},
353 	.resource	= vpu_resources,
354 	.num_resources	= ARRAY_SIZE(vpu_resources),
355 	.archdata = {
356 		.hwblk_id = HWBLK_VPU,
357 	},
358 };
359 
360 static struct uio_info veu_platform_data = {
361 	.name = "VEU",
362 	.version = "0",
363 	.irq = 54,
364 };
365 
366 static struct resource veu_resources[] = {
367 	[0] = {
368 		.name	= "VEU",
369 		.start	= 0xfe920000,
370 		.end	= 0xfe9200b7,
371 		.flags	= IORESOURCE_MEM,
372 	},
373 	[1] = {
374 		/* place holder for contiguous memory */
375 	},
376 };
377 
378 static struct platform_device veu_device = {
379 	.name		= "uio_pdrv_genirq",
380 	.id		= 1,
381 	.dev = {
382 		.platform_data	= &veu_platform_data,
383 	},
384 	.resource	= veu_resources,
385 	.num_resources	= ARRAY_SIZE(veu_resources),
386 	.archdata = {
387 		.hwblk_id = HWBLK_VEU,
388 	},
389 };
390 
391 static struct uio_info jpu_platform_data = {
392 	.name = "JPU",
393 	.version = "0",
394 	.irq = 27,
395 };
396 
397 static struct resource jpu_resources[] = {
398 	[0] = {
399 		.name	= "JPU",
400 		.start	= 0xfea00000,
401 		.end	= 0xfea102d3,
402 		.flags	= IORESOURCE_MEM,
403 	},
404 	[1] = {
405 		/* place holder for contiguous memory */
406 	},
407 };
408 
409 static struct platform_device jpu_device = {
410 	.name		= "uio_pdrv_genirq",
411 	.id		= 2,
412 	.dev = {
413 		.platform_data	= &jpu_platform_data,
414 	},
415 	.resource	= jpu_resources,
416 	.num_resources	= ARRAY_SIZE(jpu_resources),
417 	.archdata = {
418 		.hwblk_id = HWBLK_JPU,
419 	},
420 };
421 
422 static struct sh_timer_config cmt_platform_data = {
423 	.channel_offset = 0x60,
424 	.timer_bit = 5,
425 	.clockevent_rating = 125,
426 	.clocksource_rating = 125,
427 };
428 
429 static struct resource cmt_resources[] = {
430 	[0] = {
431 		.start	= 0x044a0060,
432 		.end	= 0x044a006b,
433 		.flags	= IORESOURCE_MEM,
434 	},
435 	[1] = {
436 		.start	= 104,
437 		.flags	= IORESOURCE_IRQ,
438 	},
439 };
440 
441 static struct platform_device cmt_device = {
442 	.name		= "sh_cmt",
443 	.id		= 0,
444 	.dev = {
445 		.platform_data	= &cmt_platform_data,
446 	},
447 	.resource	= cmt_resources,
448 	.num_resources	= ARRAY_SIZE(cmt_resources),
449 	.archdata = {
450 		.hwblk_id = HWBLK_CMT,
451 	},
452 };
453 
454 static struct sh_timer_config tmu0_platform_data = {
455 	.channel_offset = 0x04,
456 	.timer_bit = 0,
457 	.clockevent_rating = 200,
458 };
459 
460 static struct resource tmu0_resources[] = {
461 	[0] = {
462 		.start	= 0xffd80008,
463 		.end	= 0xffd80013,
464 		.flags	= IORESOURCE_MEM,
465 	},
466 	[1] = {
467 		.start	= 16,
468 		.flags	= IORESOURCE_IRQ,
469 	},
470 };
471 
472 static struct platform_device tmu0_device = {
473 	.name		= "sh_tmu",
474 	.id		= 0,
475 	.dev = {
476 		.platform_data	= &tmu0_platform_data,
477 	},
478 	.resource	= tmu0_resources,
479 	.num_resources	= ARRAY_SIZE(tmu0_resources),
480 	.archdata = {
481 		.hwblk_id = HWBLK_TMU,
482 	},
483 };
484 
485 static struct sh_timer_config tmu1_platform_data = {
486 	.channel_offset = 0x10,
487 	.timer_bit = 1,
488 	.clocksource_rating = 200,
489 };
490 
491 static struct resource tmu1_resources[] = {
492 	[0] = {
493 		.start	= 0xffd80014,
494 		.end	= 0xffd8001f,
495 		.flags	= IORESOURCE_MEM,
496 	},
497 	[1] = {
498 		.start	= 17,
499 		.flags	= IORESOURCE_IRQ,
500 	},
501 };
502 
503 static struct platform_device tmu1_device = {
504 	.name		= "sh_tmu",
505 	.id		= 1,
506 	.dev = {
507 		.platform_data	= &tmu1_platform_data,
508 	},
509 	.resource	= tmu1_resources,
510 	.num_resources	= ARRAY_SIZE(tmu1_resources),
511 	.archdata = {
512 		.hwblk_id = HWBLK_TMU,
513 	},
514 };
515 
516 static struct sh_timer_config tmu2_platform_data = {
517 	.channel_offset = 0x1c,
518 	.timer_bit = 2,
519 };
520 
521 static struct resource tmu2_resources[] = {
522 	[0] = {
523 		.start	= 0xffd80020,
524 		.end	= 0xffd8002b,
525 		.flags	= IORESOURCE_MEM,
526 	},
527 	[1] = {
528 		.start	= 18,
529 		.flags	= IORESOURCE_IRQ,
530 	},
531 };
532 
533 static struct platform_device tmu2_device = {
534 	.name		= "sh_tmu",
535 	.id		= 2,
536 	.dev = {
537 		.platform_data	= &tmu2_platform_data,
538 	},
539 	.resource	= tmu2_resources,
540 	.num_resources	= ARRAY_SIZE(tmu2_resources),
541 	.archdata = {
542 		.hwblk_id = HWBLK_TMU,
543 	},
544 };
545 
546 static struct siu_platform siu_platform_data = {
547 	.dma_dev	= &dma_device.dev,
548 	.dma_slave_tx_a	= SHDMA_SLAVE_SIUA_TX,
549 	.dma_slave_rx_a	= SHDMA_SLAVE_SIUA_RX,
550 	.dma_slave_tx_b	= SHDMA_SLAVE_SIUB_TX,
551 	.dma_slave_rx_b	= SHDMA_SLAVE_SIUB_RX,
552 };
553 
554 static struct resource siu_resources[] = {
555 	[0] = {
556 		.start	= 0xa4540000,
557 		.end	= 0xa454c10f,
558 		.flags	= IORESOURCE_MEM,
559 	},
560 	[1] = {
561 		.start	= 108,
562 		.flags	= IORESOURCE_IRQ,
563 	},
564 };
565 
566 static struct platform_device siu_device = {
567 	.name		= "siu-pcm-audio",
568 	.id		= -1,
569 	.dev = {
570 		.platform_data	= &siu_platform_data,
571 	},
572 	.resource	= siu_resources,
573 	.num_resources	= ARRAY_SIZE(siu_resources),
574 	.archdata = {
575 		.hwblk_id = HWBLK_SIU,
576 	},
577 };
578 
579 static struct platform_device *sh7722_devices[] __initdata = {
580 	&scif0_device,
581 	&scif1_device,
582 	&scif2_device,
583 	&cmt_device,
584 	&tmu0_device,
585 	&tmu1_device,
586 	&tmu2_device,
587 	&rtc_device,
588 	&usbf_device,
589 	&iic_device,
590 	&vpu_device,
591 	&veu_device,
592 	&jpu_device,
593 	&siu_device,
594 	&dma_device,
595 };
596 
597 static int __init sh7722_devices_setup(void)
598 {
599 	platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
600 	platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
601 	platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
602 
603 	return platform_add_devices(sh7722_devices,
604 				    ARRAY_SIZE(sh7722_devices));
605 }
606 arch_initcall(sh7722_devices_setup);
607 
608 static struct platform_device *sh7722_early_devices[] __initdata = {
609 	&scif0_device,
610 	&scif1_device,
611 	&scif2_device,
612 	&cmt_device,
613 	&tmu0_device,
614 	&tmu1_device,
615 	&tmu2_device,
616 };
617 
618 void __init plat_early_device_setup(void)
619 {
620 	early_platform_add_devices(sh7722_early_devices,
621 				   ARRAY_SIZE(sh7722_early_devices));
622 }
623 
624 enum {
625 	UNUSED=0,
626 	ENABLED,
627 	DISABLED,
628 
629 	/* interrupt sources */
630 	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
631 	HUDI,
632 	SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
633 	RTC_ATI, RTC_PRI, RTC_CUI,
634 	DMAC0, DMAC1, DMAC2, DMAC3,
635 	VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
636 	VPU, TPU,
637 	USB_USBI0, USB_USBI1,
638 	DMAC4, DMAC5, DMAC_DADERR,
639 	KEYSC,
640 	SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
641 	FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
642 	I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
643 	CMT, TSIF, SIU, TWODG,
644 	TMU0, TMU1, TMU2,
645 	IRDA, JPU, LCDC,
646 
647 	/* interrupt groups */
648 	SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
649 };
650 
651 static struct intc_vect vectors[] __initdata = {
652 	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
653 	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
654 	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
655 	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
656 	INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
657 	INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
658 	INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
659 	INTC_VECT(RTC_CUI, 0x7c0),
660 	INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
661 	INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
662 	INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
663 	INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
664 	INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
665 	INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
666 	INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
667 	INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
668 	INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
669 	INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
670 	INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
671 	INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
672 	INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
673 	INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
674 	INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
675 	INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
676 	INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
677 	INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
678 	INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
679 	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
680 	INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
681 	INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
682 };
683 
684 static struct intc_group groups[] __initdata = {
685 	INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
686 	INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
687 	INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
688 	INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
689 	INTC_GROUP(USB, USB_USBI0, USB_USBI1),
690 	INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
691 	INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
692 		   FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
693 	INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
694 };
695 
696 static struct intc_mask_reg mask_registers[] __initdata = {
697 	{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
698 	  { } },
699 	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
700 	  { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
701 	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
702 	  { 0, 0, 0, VPU, } },
703 	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
704 	  { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
705 	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
706 	  { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
707 	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
708 	  { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
709 	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
710 	  { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
711 	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
712 	  { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
713 	    FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
714 	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
715 	  { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
716 	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
717 	  { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
718 	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
719 	  { } },
720 	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
721 	  { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
722 	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
723 	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
724 };
725 
726 static struct intc_prio_reg prio_registers[] __initdata = {
727 	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
728 	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
729 	{ 0xa4080008, 0, 16, 4, /* IPRC */ { } },
730 	{ 0xa408000c, 0, 16, 4, /* IPRD */ { } },
731 	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
732 	{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
733 	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
734 	{ 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
735 	{ 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
736 	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
737 	{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
738 	{ 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
739 	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
740 	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
741 };
742 
743 static struct intc_sense_reg sense_registers[] __initdata = {
744 	{ 0xa414001c, 16, 2, /* ICR1 */
745 	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
746 };
747 
748 static struct intc_mask_reg ack_registers[] __initdata = {
749 	{ 0xa4140024, 0, 8, /* INTREQ00 */
750 	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
751 };
752 
753 static struct intc_desc intc_desc __initdata = {
754 	.name = "sh7722",
755 	.force_enable = ENABLED,
756 	.force_disable = DISABLED,
757 	.hw = INTC_HW_DESC(vectors, groups, mask_registers,
758 			   prio_registers, sense_registers, ack_registers),
759 };
760 
761 void __init plat_irq_setup(void)
762 {
763 	register_intc_controller(&intc_desc);
764 }
765 
766 void __init plat_mem_setup(void)
767 {
768 	/* Register the URAM space as Node 1 */
769 	setup_bootmem_node(1, 0x055f0000, 0x05610000);
770 }
771