1 /* 2 * SH7722 Setup 3 * 4 * Copyright (C) 2006 - 2008 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/init.h> 11 #include <linux/mm.h> 12 #include <linux/platform_device.h> 13 #include <linux/serial.h> 14 #include <linux/serial_sci.h> 15 #include <linux/sh_timer.h> 16 #include <linux/uio_driver.h> 17 #include <linux/usb/m66592.h> 18 19 #include <asm/clock.h> 20 #include <asm/mmzone.h> 21 #include <asm/siu.h> 22 23 #include <cpu/dma-register.h> 24 #include <cpu/sh7722.h> 25 26 static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = { 27 { 28 .slave_id = SHDMA_SLAVE_SCIF0_TX, 29 .addr = 0xffe0000c, 30 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 31 .mid_rid = 0x21, 32 }, { 33 .slave_id = SHDMA_SLAVE_SCIF0_RX, 34 .addr = 0xffe00014, 35 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 36 .mid_rid = 0x22, 37 }, { 38 .slave_id = SHDMA_SLAVE_SCIF1_TX, 39 .addr = 0xffe1000c, 40 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 41 .mid_rid = 0x25, 42 }, { 43 .slave_id = SHDMA_SLAVE_SCIF1_RX, 44 .addr = 0xffe10014, 45 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 46 .mid_rid = 0x26, 47 }, { 48 .slave_id = SHDMA_SLAVE_SCIF2_TX, 49 .addr = 0xffe2000c, 50 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 51 .mid_rid = 0x29, 52 }, { 53 .slave_id = SHDMA_SLAVE_SCIF2_RX, 54 .addr = 0xffe20014, 55 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 56 .mid_rid = 0x2a, 57 }, { 58 .slave_id = SHDMA_SLAVE_SIUA_TX, 59 .addr = 0xa454c098, 60 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 61 .mid_rid = 0xb1, 62 }, { 63 .slave_id = SHDMA_SLAVE_SIUA_RX, 64 .addr = 0xa454c090, 65 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 66 .mid_rid = 0xb2, 67 }, { 68 .slave_id = SHDMA_SLAVE_SIUB_TX, 69 .addr = 0xa454c09c, 70 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 71 .mid_rid = 0xb5, 72 }, { 73 .slave_id = SHDMA_SLAVE_SIUB_RX, 74 .addr = 0xa454c094, 75 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 76 .mid_rid = 0xb6, 77 }, { 78 .slave_id = SHDMA_SLAVE_SDHI0_TX, 79 .addr = 0x04ce0030, 80 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 81 .mid_rid = 0xc1, 82 }, { 83 .slave_id = SHDMA_SLAVE_SDHI0_RX, 84 .addr = 0x04ce0030, 85 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 86 .mid_rid = 0xc2, 87 }, 88 }; 89 90 static const struct sh_dmae_channel sh7722_dmae_channels[] = { 91 { 92 .offset = 0, 93 .dmars = 0, 94 .dmars_bit = 0, 95 }, { 96 .offset = 0x10, 97 .dmars = 0, 98 .dmars_bit = 8, 99 }, { 100 .offset = 0x20, 101 .dmars = 4, 102 .dmars_bit = 0, 103 }, { 104 .offset = 0x30, 105 .dmars = 4, 106 .dmars_bit = 8, 107 }, { 108 .offset = 0x50, 109 .dmars = 8, 110 .dmars_bit = 0, 111 }, { 112 .offset = 0x60, 113 .dmars = 8, 114 .dmars_bit = 8, 115 } 116 }; 117 118 static const unsigned int ts_shift[] = TS_SHIFT; 119 120 static struct sh_dmae_pdata dma_platform_data = { 121 .slave = sh7722_dmae_slaves, 122 .slave_num = ARRAY_SIZE(sh7722_dmae_slaves), 123 .channel = sh7722_dmae_channels, 124 .channel_num = ARRAY_SIZE(sh7722_dmae_channels), 125 .ts_low_shift = CHCR_TS_LOW_SHIFT, 126 .ts_low_mask = CHCR_TS_LOW_MASK, 127 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 128 .ts_high_mask = CHCR_TS_HIGH_MASK, 129 .ts_shift = ts_shift, 130 .ts_shift_num = ARRAY_SIZE(ts_shift), 131 .dmaor_init = DMAOR_INIT, 132 }; 133 134 static struct resource sh7722_dmae_resources[] = { 135 [0] = { 136 /* Channel registers and DMAOR */ 137 .start = 0xfe008020, 138 .end = 0xfe00808f, 139 .flags = IORESOURCE_MEM, 140 }, 141 [1] = { 142 /* DMARSx */ 143 .start = 0xfe009000, 144 .end = 0xfe00900b, 145 .flags = IORESOURCE_MEM, 146 }, 147 { 148 /* DMA error IRQ */ 149 .start = 78, 150 .end = 78, 151 .flags = IORESOURCE_IRQ, 152 }, 153 { 154 /* IRQ for channels 0-3 */ 155 .start = 48, 156 .end = 51, 157 .flags = IORESOURCE_IRQ, 158 }, 159 { 160 /* IRQ for channels 4-5 */ 161 .start = 76, 162 .end = 77, 163 .flags = IORESOURCE_IRQ, 164 }, 165 }; 166 167 struct platform_device dma_device = { 168 .name = "sh-dma-engine", 169 .id = -1, 170 .resource = sh7722_dmae_resources, 171 .num_resources = ARRAY_SIZE(sh7722_dmae_resources), 172 .dev = { 173 .platform_data = &dma_platform_data, 174 }, 175 .archdata = { 176 .hwblk_id = HWBLK_DMAC, 177 }, 178 }; 179 180 /* Serial */ 181 static struct plat_sci_port scif0_platform_data = { 182 .mapbase = 0xffe00000, 183 .flags = UPF_BOOT_AUTOCONF, 184 .type = PORT_SCIF, 185 .irqs = { 80, 80, 80, 80 }, 186 }; 187 188 static struct platform_device scif0_device = { 189 .name = "sh-sci", 190 .id = 0, 191 .dev = { 192 .platform_data = &scif0_platform_data, 193 }, 194 }; 195 196 static struct plat_sci_port scif1_platform_data = { 197 .mapbase = 0xffe10000, 198 .flags = UPF_BOOT_AUTOCONF, 199 .type = PORT_SCIF, 200 .irqs = { 81, 81, 81, 81 }, 201 }; 202 203 static struct platform_device scif1_device = { 204 .name = "sh-sci", 205 .id = 1, 206 .dev = { 207 .platform_data = &scif1_platform_data, 208 }, 209 }; 210 211 static struct plat_sci_port scif2_platform_data = { 212 .mapbase = 0xffe20000, 213 .flags = UPF_BOOT_AUTOCONF, 214 .type = PORT_SCIF, 215 .irqs = { 82, 82, 82, 82 }, 216 }; 217 218 static struct platform_device scif2_device = { 219 .name = "sh-sci", 220 .id = 2, 221 .dev = { 222 .platform_data = &scif2_platform_data, 223 }, 224 }; 225 226 static struct resource rtc_resources[] = { 227 [0] = { 228 .start = 0xa465fec0, 229 .end = 0xa465fec0 + 0x58 - 1, 230 .flags = IORESOURCE_IO, 231 }, 232 [1] = { 233 /* Period IRQ */ 234 .start = 45, 235 .flags = IORESOURCE_IRQ, 236 }, 237 [2] = { 238 /* Carry IRQ */ 239 .start = 46, 240 .flags = IORESOURCE_IRQ, 241 }, 242 [3] = { 243 /* Alarm IRQ */ 244 .start = 44, 245 .flags = IORESOURCE_IRQ, 246 }, 247 }; 248 249 static struct platform_device rtc_device = { 250 .name = "sh-rtc", 251 .id = -1, 252 .num_resources = ARRAY_SIZE(rtc_resources), 253 .resource = rtc_resources, 254 .archdata = { 255 .hwblk_id = HWBLK_RTC, 256 }, 257 }; 258 259 static struct m66592_platdata usbf_platdata = { 260 .on_chip = 1, 261 }; 262 263 static struct resource usbf_resources[] = { 264 [0] = { 265 .name = "USBF", 266 .start = 0x04480000, 267 .end = 0x044800FF, 268 .flags = IORESOURCE_MEM, 269 }, 270 [1] = { 271 .start = 65, 272 .end = 65, 273 .flags = IORESOURCE_IRQ, 274 }, 275 }; 276 277 static struct platform_device usbf_device = { 278 .name = "m66592_udc", 279 .id = 0, /* "usbf0" clock */ 280 .dev = { 281 .dma_mask = NULL, 282 .coherent_dma_mask = 0xffffffff, 283 .platform_data = &usbf_platdata, 284 }, 285 .num_resources = ARRAY_SIZE(usbf_resources), 286 .resource = usbf_resources, 287 .archdata = { 288 .hwblk_id = HWBLK_USBF, 289 }, 290 }; 291 292 static struct resource iic_resources[] = { 293 [0] = { 294 .name = "IIC", 295 .start = 0x04470000, 296 .end = 0x04470017, 297 .flags = IORESOURCE_MEM, 298 }, 299 [1] = { 300 .start = 96, 301 .end = 99, 302 .flags = IORESOURCE_IRQ, 303 }, 304 }; 305 306 static struct platform_device iic_device = { 307 .name = "i2c-sh_mobile", 308 .id = 0, /* "i2c0" clock */ 309 .num_resources = ARRAY_SIZE(iic_resources), 310 .resource = iic_resources, 311 .archdata = { 312 .hwblk_id = HWBLK_IIC, 313 }, 314 }; 315 316 static struct uio_info vpu_platform_data = { 317 .name = "VPU4", 318 .version = "0", 319 .irq = 60, 320 }; 321 322 static struct resource vpu_resources[] = { 323 [0] = { 324 .name = "VPU", 325 .start = 0xfe900000, 326 .end = 0xfe9022eb, 327 .flags = IORESOURCE_MEM, 328 }, 329 [1] = { 330 /* place holder for contiguous memory */ 331 }, 332 }; 333 334 static struct platform_device vpu_device = { 335 .name = "uio_pdrv_genirq", 336 .id = 0, 337 .dev = { 338 .platform_data = &vpu_platform_data, 339 }, 340 .resource = vpu_resources, 341 .num_resources = ARRAY_SIZE(vpu_resources), 342 .archdata = { 343 .hwblk_id = HWBLK_VPU, 344 }, 345 }; 346 347 static struct uio_info veu_platform_data = { 348 .name = "VEU", 349 .version = "0", 350 .irq = 54, 351 }; 352 353 static struct resource veu_resources[] = { 354 [0] = { 355 .name = "VEU", 356 .start = 0xfe920000, 357 .end = 0xfe9200b7, 358 .flags = IORESOURCE_MEM, 359 }, 360 [1] = { 361 /* place holder for contiguous memory */ 362 }, 363 }; 364 365 static struct platform_device veu_device = { 366 .name = "uio_pdrv_genirq", 367 .id = 1, 368 .dev = { 369 .platform_data = &veu_platform_data, 370 }, 371 .resource = veu_resources, 372 .num_resources = ARRAY_SIZE(veu_resources), 373 .archdata = { 374 .hwblk_id = HWBLK_VEU, 375 }, 376 }; 377 378 static struct uio_info jpu_platform_data = { 379 .name = "JPU", 380 .version = "0", 381 .irq = 27, 382 }; 383 384 static struct resource jpu_resources[] = { 385 [0] = { 386 .name = "JPU", 387 .start = 0xfea00000, 388 .end = 0xfea102d3, 389 .flags = IORESOURCE_MEM, 390 }, 391 [1] = { 392 /* place holder for contiguous memory */ 393 }, 394 }; 395 396 static struct platform_device jpu_device = { 397 .name = "uio_pdrv_genirq", 398 .id = 2, 399 .dev = { 400 .platform_data = &jpu_platform_data, 401 }, 402 .resource = jpu_resources, 403 .num_resources = ARRAY_SIZE(jpu_resources), 404 .archdata = { 405 .hwblk_id = HWBLK_JPU, 406 }, 407 }; 408 409 static struct sh_timer_config cmt_platform_data = { 410 .channel_offset = 0x60, 411 .timer_bit = 5, 412 .clockevent_rating = 125, 413 .clocksource_rating = 125, 414 }; 415 416 static struct resource cmt_resources[] = { 417 [0] = { 418 .start = 0x044a0060, 419 .end = 0x044a006b, 420 .flags = IORESOURCE_MEM, 421 }, 422 [1] = { 423 .start = 104, 424 .flags = IORESOURCE_IRQ, 425 }, 426 }; 427 428 static struct platform_device cmt_device = { 429 .name = "sh_cmt", 430 .id = 0, 431 .dev = { 432 .platform_data = &cmt_platform_data, 433 }, 434 .resource = cmt_resources, 435 .num_resources = ARRAY_SIZE(cmt_resources), 436 .archdata = { 437 .hwblk_id = HWBLK_CMT, 438 }, 439 }; 440 441 static struct sh_timer_config tmu0_platform_data = { 442 .channel_offset = 0x04, 443 .timer_bit = 0, 444 .clockevent_rating = 200, 445 }; 446 447 static struct resource tmu0_resources[] = { 448 [0] = { 449 .start = 0xffd80008, 450 .end = 0xffd80013, 451 .flags = IORESOURCE_MEM, 452 }, 453 [1] = { 454 .start = 16, 455 .flags = IORESOURCE_IRQ, 456 }, 457 }; 458 459 static struct platform_device tmu0_device = { 460 .name = "sh_tmu", 461 .id = 0, 462 .dev = { 463 .platform_data = &tmu0_platform_data, 464 }, 465 .resource = tmu0_resources, 466 .num_resources = ARRAY_SIZE(tmu0_resources), 467 .archdata = { 468 .hwblk_id = HWBLK_TMU, 469 }, 470 }; 471 472 static struct sh_timer_config tmu1_platform_data = { 473 .channel_offset = 0x10, 474 .timer_bit = 1, 475 .clocksource_rating = 200, 476 }; 477 478 static struct resource tmu1_resources[] = { 479 [0] = { 480 .start = 0xffd80014, 481 .end = 0xffd8001f, 482 .flags = IORESOURCE_MEM, 483 }, 484 [1] = { 485 .start = 17, 486 .flags = IORESOURCE_IRQ, 487 }, 488 }; 489 490 static struct platform_device tmu1_device = { 491 .name = "sh_tmu", 492 .id = 1, 493 .dev = { 494 .platform_data = &tmu1_platform_data, 495 }, 496 .resource = tmu1_resources, 497 .num_resources = ARRAY_SIZE(tmu1_resources), 498 .archdata = { 499 .hwblk_id = HWBLK_TMU, 500 }, 501 }; 502 503 static struct sh_timer_config tmu2_platform_data = { 504 .channel_offset = 0x1c, 505 .timer_bit = 2, 506 }; 507 508 static struct resource tmu2_resources[] = { 509 [0] = { 510 .start = 0xffd80020, 511 .end = 0xffd8002b, 512 .flags = IORESOURCE_MEM, 513 }, 514 [1] = { 515 .start = 18, 516 .flags = IORESOURCE_IRQ, 517 }, 518 }; 519 520 static struct platform_device tmu2_device = { 521 .name = "sh_tmu", 522 .id = 2, 523 .dev = { 524 .platform_data = &tmu2_platform_data, 525 }, 526 .resource = tmu2_resources, 527 .num_resources = ARRAY_SIZE(tmu2_resources), 528 .archdata = { 529 .hwblk_id = HWBLK_TMU, 530 }, 531 }; 532 533 static struct siu_platform siu_platform_data = { 534 .dma_dev = &dma_device.dev, 535 .dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX, 536 .dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX, 537 .dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX, 538 .dma_slave_rx_b = SHDMA_SLAVE_SIUB_RX, 539 }; 540 541 static struct resource siu_resources[] = { 542 [0] = { 543 .start = 0xa4540000, 544 .end = 0xa454c10f, 545 .flags = IORESOURCE_MEM, 546 }, 547 [1] = { 548 .start = 108, 549 .flags = IORESOURCE_IRQ, 550 }, 551 }; 552 553 static struct platform_device siu_device = { 554 .name = "siu-pcm-audio", 555 .id = -1, 556 .dev = { 557 .platform_data = &siu_platform_data, 558 }, 559 .resource = siu_resources, 560 .num_resources = ARRAY_SIZE(siu_resources), 561 .archdata = { 562 .hwblk_id = HWBLK_SIU, 563 }, 564 }; 565 566 static struct platform_device *sh7722_devices[] __initdata = { 567 &scif0_device, 568 &scif1_device, 569 &scif2_device, 570 &cmt_device, 571 &tmu0_device, 572 &tmu1_device, 573 &tmu2_device, 574 &rtc_device, 575 &usbf_device, 576 &iic_device, 577 &vpu_device, 578 &veu_device, 579 &jpu_device, 580 &siu_device, 581 &dma_device, 582 }; 583 584 static int __init sh7722_devices_setup(void) 585 { 586 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20); 587 platform_resource_setup_memory(&veu_device, "veu", 2 << 20); 588 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); 589 590 return platform_add_devices(sh7722_devices, 591 ARRAY_SIZE(sh7722_devices)); 592 } 593 arch_initcall(sh7722_devices_setup); 594 595 static struct platform_device *sh7722_early_devices[] __initdata = { 596 &scif0_device, 597 &scif1_device, 598 &scif2_device, 599 &cmt_device, 600 &tmu0_device, 601 &tmu1_device, 602 &tmu2_device, 603 }; 604 605 void __init plat_early_device_setup(void) 606 { 607 early_platform_add_devices(sh7722_early_devices, 608 ARRAY_SIZE(sh7722_early_devices)); 609 } 610 611 enum { 612 UNUSED=0, 613 ENABLED, 614 DISABLED, 615 616 /* interrupt sources */ 617 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 618 HUDI, 619 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI, 620 RTC_ATI, RTC_PRI, RTC_CUI, 621 DMAC0, DMAC1, DMAC2, DMAC3, 622 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU, 623 VPU, TPU, 624 USB_USBI0, USB_USBI1, 625 DMAC4, DMAC5, DMAC_DADERR, 626 KEYSC, 627 SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO, 628 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 629 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI, 630 CMT, TSIF, SIU, TWODG, 631 TMU0, TMU1, TMU2, 632 IRDA, JPU, LCDC, 633 634 /* interrupt groups */ 635 SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI, 636 }; 637 638 static struct intc_vect vectors[] __initdata = { 639 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 640 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 641 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 642 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 643 INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720), 644 INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760), 645 INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0), 646 INTC_VECT(RTC_CUI, 0x7c0), 647 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820), 648 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860), 649 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0), 650 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0), 651 INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0), 652 INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40), 653 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0), 654 INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0), 655 INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20), 656 INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80), 657 INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00), 658 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0), 659 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), 660 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20), 661 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60), 662 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0), 663 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0), 664 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), 665 INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0), 666 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 667 INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480), 668 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580), 669 }; 670 671 static struct intc_group groups[] __initdata = { 672 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI), 673 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 674 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), 675 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU), 676 INTC_GROUP(USB, USB_USBI0, USB_USBI1), 677 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR), 678 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, 679 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 680 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI), 681 }; 682 683 static struct intc_mask_reg mask_registers[] __initdata = { 684 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 685 { } }, 686 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 687 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } }, 688 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 689 { 0, 0, 0, VPU, } }, 690 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 691 { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } }, 692 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 693 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } }, 694 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 695 { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } }, 696 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 697 { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } }, 698 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 699 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 700 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 701 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 702 { DISABLED, DISABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } }, 703 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 704 { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } }, 705 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 706 { } }, 707 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 708 { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } }, 709 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 710 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 711 }; 712 713 static struct intc_prio_reg prio_registers[] __initdata = { 714 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } }, 715 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } }, 716 { 0xa4080008, 0, 16, 4, /* IPRC */ { } }, 717 { 0xa408000c, 0, 16, 4, /* IPRD */ { } }, 718 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } }, 719 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } }, 720 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } }, 721 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } }, 722 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } }, 723 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } }, 724 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } }, 725 { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } }, 726 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 727 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 728 }; 729 730 static struct intc_sense_reg sense_registers[] __initdata = { 731 { 0xa414001c, 16, 2, /* ICR1 */ 732 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 733 }; 734 735 static struct intc_mask_reg ack_registers[] __initdata = { 736 { 0xa4140024, 0, 8, /* INTREQ00 */ 737 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 738 }; 739 740 static struct intc_desc intc_desc __initdata = { 741 .name = "sh7722", 742 .force_enable = ENABLED, 743 .force_disable = DISABLED, 744 .hw = INTC_HW_DESC(vectors, groups, mask_registers, 745 prio_registers, sense_registers, ack_registers), 746 }; 747 748 void __init plat_irq_setup(void) 749 { 750 register_intc_controller(&intc_desc); 751 } 752 753 void __init plat_mem_setup(void) 754 { 755 /* Register the URAM space as Node 1 */ 756 setup_bootmem_node(1, 0x055f0000, 0x05610000); 757 } 758