1 /* 2 * SH7722 Setup 3 * 4 * Copyright (C) 2006 - 2008 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/serial_sci.h> 14 #include <linux/mm.h> 15 #include <linux/uio_driver.h> 16 #include <linux/sh_timer.h> 17 #include <asm/clock.h> 18 #include <asm/mmzone.h> 19 20 static struct resource rtc_resources[] = { 21 [0] = { 22 .start = 0xa465fec0, 23 .end = 0xa465fec0 + 0x58 - 1, 24 .flags = IORESOURCE_IO, 25 }, 26 [1] = { 27 /* Period IRQ */ 28 .start = 45, 29 .flags = IORESOURCE_IRQ, 30 }, 31 [2] = { 32 /* Carry IRQ */ 33 .start = 46, 34 .flags = IORESOURCE_IRQ, 35 }, 36 [3] = { 37 /* Alarm IRQ */ 38 .start = 44, 39 .flags = IORESOURCE_IRQ, 40 }, 41 }; 42 43 static struct platform_device rtc_device = { 44 .name = "sh-rtc", 45 .id = -1, 46 .num_resources = ARRAY_SIZE(rtc_resources), 47 .resource = rtc_resources, 48 }; 49 50 static struct resource usbf_resources[] = { 51 [0] = { 52 .name = "m66592_udc", 53 .start = 0x04480000, 54 .end = 0x044800FF, 55 .flags = IORESOURCE_MEM, 56 }, 57 [1] = { 58 .start = 65, 59 .end = 65, 60 .flags = IORESOURCE_IRQ, 61 }, 62 }; 63 64 static struct platform_device usbf_device = { 65 .name = "m66592_udc", 66 .id = 0, /* "usbf0" clock */ 67 .dev = { 68 .dma_mask = NULL, 69 .coherent_dma_mask = 0xffffffff, 70 }, 71 .num_resources = ARRAY_SIZE(usbf_resources), 72 .resource = usbf_resources, 73 }; 74 75 static struct resource iic_resources[] = { 76 [0] = { 77 .name = "IIC", 78 .start = 0x04470000, 79 .end = 0x04470017, 80 .flags = IORESOURCE_MEM, 81 }, 82 [1] = { 83 .start = 96, 84 .end = 99, 85 .flags = IORESOURCE_IRQ, 86 }, 87 }; 88 89 static struct platform_device iic_device = { 90 .name = "i2c-sh_mobile", 91 .id = 0, /* "i2c0" clock */ 92 .num_resources = ARRAY_SIZE(iic_resources), 93 .resource = iic_resources, 94 }; 95 96 static struct uio_info vpu_platform_data = { 97 .name = "VPU4", 98 .version = "0", 99 .irq = 60, 100 }; 101 102 static struct resource vpu_resources[] = { 103 [0] = { 104 .name = "VPU", 105 .start = 0xfe900000, 106 .end = 0xfe9022eb, 107 .flags = IORESOURCE_MEM, 108 }, 109 [1] = { 110 /* place holder for contiguous memory */ 111 }, 112 }; 113 114 static struct platform_device vpu_device = { 115 .name = "uio_pdrv_genirq", 116 .id = 0, 117 .dev = { 118 .platform_data = &vpu_platform_data, 119 }, 120 .resource = vpu_resources, 121 .num_resources = ARRAY_SIZE(vpu_resources), 122 }; 123 124 static struct uio_info veu_platform_data = { 125 .name = "VEU", 126 .version = "0", 127 .irq = 54, 128 }; 129 130 static struct resource veu_resources[] = { 131 [0] = { 132 .name = "VEU", 133 .start = 0xfe920000, 134 .end = 0xfe9200b7, 135 .flags = IORESOURCE_MEM, 136 }, 137 [1] = { 138 /* place holder for contiguous memory */ 139 }, 140 }; 141 142 static struct platform_device veu_device = { 143 .name = "uio_pdrv_genirq", 144 .id = 1, 145 .dev = { 146 .platform_data = &veu_platform_data, 147 }, 148 .resource = veu_resources, 149 .num_resources = ARRAY_SIZE(veu_resources), 150 }; 151 152 static struct uio_info jpu_platform_data = { 153 .name = "JPU", 154 .version = "0", 155 .irq = 27, 156 }; 157 158 static struct resource jpu_resources[] = { 159 [0] = { 160 .name = "JPU", 161 .start = 0xfea00000, 162 .end = 0xfea102d3, 163 .flags = IORESOURCE_MEM, 164 }, 165 [1] = { 166 /* place holder for contiguous memory */ 167 }, 168 }; 169 170 static struct platform_device jpu_device = { 171 .name = "uio_pdrv_genirq", 172 .id = 2, 173 .dev = { 174 .platform_data = &jpu_platform_data, 175 }, 176 .resource = jpu_resources, 177 .num_resources = ARRAY_SIZE(jpu_resources), 178 }; 179 180 static struct sh_timer_config cmt_platform_data = { 181 .name = "CMT", 182 .channel_offset = 0x60, 183 .timer_bit = 5, 184 .clk = "cmt0", 185 .clockevent_rating = 125, 186 .clocksource_rating = 125, 187 }; 188 189 static struct resource cmt_resources[] = { 190 [0] = { 191 .name = "CMT", 192 .start = 0x044a0060, 193 .end = 0x044a006b, 194 .flags = IORESOURCE_MEM, 195 }, 196 [1] = { 197 .start = 104, 198 .flags = IORESOURCE_IRQ, 199 }, 200 }; 201 202 static struct platform_device cmt_device = { 203 .name = "sh_cmt", 204 .id = 0, 205 .dev = { 206 .platform_data = &cmt_platform_data, 207 }, 208 .resource = cmt_resources, 209 .num_resources = ARRAY_SIZE(cmt_resources), 210 }; 211 212 static struct sh_timer_config tmu0_platform_data = { 213 .name = "TMU0", 214 .channel_offset = 0x04, 215 .timer_bit = 0, 216 .clk = "tmu0", 217 .clockevent_rating = 200, 218 }; 219 220 static struct resource tmu0_resources[] = { 221 [0] = { 222 .name = "TMU0", 223 .start = 0xffd80008, 224 .end = 0xffd80013, 225 .flags = IORESOURCE_MEM, 226 }, 227 [1] = { 228 .start = 16, 229 .flags = IORESOURCE_IRQ, 230 }, 231 }; 232 233 static struct platform_device tmu0_device = { 234 .name = "sh_tmu", 235 .id = 0, 236 .dev = { 237 .platform_data = &tmu0_platform_data, 238 }, 239 .resource = tmu0_resources, 240 .num_resources = ARRAY_SIZE(tmu0_resources), 241 }; 242 243 static struct sh_timer_config tmu1_platform_data = { 244 .name = "TMU1", 245 .channel_offset = 0x10, 246 .timer_bit = 1, 247 .clk = "tmu0", 248 .clocksource_rating = 200, 249 }; 250 251 static struct resource tmu1_resources[] = { 252 [0] = { 253 .name = "TMU1", 254 .start = 0xffd80014, 255 .end = 0xffd8001f, 256 .flags = IORESOURCE_MEM, 257 }, 258 [1] = { 259 .start = 17, 260 .flags = IORESOURCE_IRQ, 261 }, 262 }; 263 264 static struct platform_device tmu1_device = { 265 .name = "sh_tmu", 266 .id = 1, 267 .dev = { 268 .platform_data = &tmu1_platform_data, 269 }, 270 .resource = tmu1_resources, 271 .num_resources = ARRAY_SIZE(tmu1_resources), 272 }; 273 274 static struct sh_timer_config tmu2_platform_data = { 275 .name = "TMU2", 276 .channel_offset = 0x1c, 277 .timer_bit = 2, 278 .clk = "tmu0", 279 }; 280 281 static struct resource tmu2_resources[] = { 282 [0] = { 283 .name = "TMU2", 284 .start = 0xffd80020, 285 .end = 0xffd8002b, 286 .flags = IORESOURCE_MEM, 287 }, 288 [1] = { 289 .start = 18, 290 .flags = IORESOURCE_IRQ, 291 }, 292 }; 293 294 static struct platform_device tmu2_device = { 295 .name = "sh_tmu", 296 .id = 2, 297 .dev = { 298 .platform_data = &tmu2_platform_data, 299 }, 300 .resource = tmu2_resources, 301 .num_resources = ARRAY_SIZE(tmu2_resources), 302 }; 303 304 static struct plat_sci_port sci_platform_data[] = { 305 { 306 .mapbase = 0xffe00000, 307 .flags = UPF_BOOT_AUTOCONF, 308 .type = PORT_SCIF, 309 .irqs = { 80, 80, 80, 80 }, 310 .clk = "scif0", 311 }, 312 { 313 .mapbase = 0xffe10000, 314 .flags = UPF_BOOT_AUTOCONF, 315 .type = PORT_SCIF, 316 .irqs = { 81, 81, 81, 81 }, 317 .clk = "scif1", 318 }, 319 { 320 .mapbase = 0xffe20000, 321 .flags = UPF_BOOT_AUTOCONF, 322 .type = PORT_SCIF, 323 .irqs = { 82, 82, 82, 82 }, 324 .clk = "scif2", 325 }, 326 { 327 .flags = 0, 328 } 329 }; 330 331 static struct platform_device sci_device = { 332 .name = "sh-sci", 333 .id = -1, 334 .dev = { 335 .platform_data = sci_platform_data, 336 }, 337 }; 338 339 static struct platform_device *sh7722_devices[] __initdata = { 340 &cmt_device, 341 &tmu0_device, 342 &tmu1_device, 343 &tmu2_device, 344 &rtc_device, 345 &usbf_device, 346 &iic_device, 347 &sci_device, 348 &vpu_device, 349 &veu_device, 350 &jpu_device, 351 }; 352 353 static int __init sh7722_devices_setup(void) 354 { 355 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20); 356 platform_resource_setup_memory(&veu_device, "veu", 2 << 20); 357 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); 358 359 return platform_add_devices(sh7722_devices, 360 ARRAY_SIZE(sh7722_devices)); 361 } 362 __initcall(sh7722_devices_setup); 363 364 static struct platform_device *sh7722_early_devices[] __initdata = { 365 &cmt_device, 366 &tmu0_device, 367 &tmu1_device, 368 &tmu2_device, 369 }; 370 371 void __init plat_early_device_setup(void) 372 { 373 early_platform_add_devices(sh7722_early_devices, 374 ARRAY_SIZE(sh7722_early_devices)); 375 } 376 377 enum { 378 UNUSED=0, 379 380 /* interrupt sources */ 381 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 382 HUDI, 383 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI, 384 RTC_ATI, RTC_PRI, RTC_CUI, 385 DMAC0, DMAC1, DMAC2, DMAC3, 386 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU, 387 VPU, TPU, 388 USB_USBI0, USB_USBI1, 389 DMAC4, DMAC5, DMAC_DADERR, 390 KEYSC, 391 SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO, 392 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 393 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI, 394 SDHI0, SDHI1, SDHI2, SDHI3, 395 CMT, TSIF, SIU, TWODG, 396 TMU0, TMU1, TMU2, 397 IRDA, JPU, LCDC, 398 399 /* interrupt groups */ 400 SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI, 401 }; 402 403 static struct intc_vect vectors[] __initdata = { 404 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 405 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 406 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 407 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 408 INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720), 409 INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760), 410 INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0), 411 INTC_VECT(RTC_CUI, 0x7c0), 412 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820), 413 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860), 414 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0), 415 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0), 416 INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0), 417 INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40), 418 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0), 419 INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0), 420 INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20), 421 INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80), 422 INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00), 423 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0), 424 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), 425 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20), 426 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60), 427 INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0), 428 INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0), 429 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), 430 INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0), 431 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 432 INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480), 433 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580), 434 }; 435 436 static struct intc_group groups[] __initdata = { 437 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI), 438 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 439 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), 440 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU), 441 INTC_GROUP(USB, USB_USBI0, USB_USBI1), 442 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR), 443 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, 444 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 445 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI), 446 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3), 447 }; 448 449 static struct intc_mask_reg mask_registers[] __initdata = { 450 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 451 { } }, 452 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 453 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } }, 454 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 455 { 0, 0, 0, VPU, } }, 456 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 457 { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } }, 458 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 459 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } }, 460 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 461 { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } }, 462 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 463 { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } }, 464 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 465 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 466 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 467 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 468 { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, TWODG, SIU } }, 469 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 470 { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } }, 471 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 472 { } }, 473 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 474 { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } }, 475 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 476 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 477 }; 478 479 static struct intc_prio_reg prio_registers[] __initdata = { 480 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } }, 481 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } }, 482 { 0xa4080008, 0, 16, 4, /* IPRC */ { } }, 483 { 0xa408000c, 0, 16, 4, /* IPRD */ { } }, 484 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } }, 485 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } }, 486 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } }, 487 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } }, 488 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } }, 489 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } }, 490 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } }, 491 { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } }, 492 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 493 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 494 }; 495 496 static struct intc_sense_reg sense_registers[] __initdata = { 497 { 0xa414001c, 16, 2, /* ICR1 */ 498 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 499 }; 500 501 static struct intc_mask_reg ack_registers[] __initdata = { 502 { 0xa4140024, 0, 8, /* INTREQ00 */ 503 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 504 }; 505 506 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7722", vectors, groups, 507 mask_registers, prio_registers, sense_registers, 508 ack_registers); 509 510 void __init plat_irq_setup(void) 511 { 512 register_intc_controller(&intc_desc); 513 } 514 515 void __init plat_mem_setup(void) 516 { 517 /* Register the URAM space as Node 1 */ 518 setup_bootmem_node(1, 0x055f0000, 0x05610000); 519 } 520