1 /* 2 * SH7366 Setup 3 * 4 * Copyright (C) 2008 Renesas Solutions 5 * 6 * Based on linux/arch/sh/kernel/cpu/sh4a/setup-sh7722.c 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 #include <linux/platform_device.h> 13 #include <linux/init.h> 14 #include <linux/serial.h> 15 #include <linux/serial_sci.h> 16 #include <linux/uio_driver.h> 17 #include <linux/sh_timer.h> 18 #include <linux/usb/r8a66597.h> 19 #include <asm/clock.h> 20 21 static struct resource iic_resources[] = { 22 [0] = { 23 .name = "IIC", 24 .start = 0x04470000, 25 .end = 0x04470017, 26 .flags = IORESOURCE_MEM, 27 }, 28 [1] = { 29 .start = 96, 30 .end = 99, 31 .flags = IORESOURCE_IRQ, 32 }, 33 }; 34 35 static struct platform_device iic_device = { 36 .name = "i2c-sh_mobile", 37 .id = 0, /* "i2c0" clock */ 38 .num_resources = ARRAY_SIZE(iic_resources), 39 .resource = iic_resources, 40 }; 41 42 static struct r8a66597_platdata r8a66597_data = { 43 .on_chip = 1, 44 }; 45 46 static struct resource usb_host_resources[] = { 47 [0] = { 48 .start = 0xa4d80000, 49 .end = 0xa4d800ff, 50 .flags = IORESOURCE_MEM, 51 }, 52 [1] = { 53 .start = 65, 54 .end = 65, 55 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, 56 }, 57 }; 58 59 static struct platform_device usb_host_device = { 60 .name = "r8a66597_hcd", 61 .id = -1, 62 .dev = { 63 .dma_mask = NULL, 64 .coherent_dma_mask = 0xffffffff, 65 .platform_data = &r8a66597_data, 66 }, 67 .num_resources = ARRAY_SIZE(usb_host_resources), 68 .resource = usb_host_resources, 69 }; 70 71 static struct uio_info vpu_platform_data = { 72 .name = "VPU5", 73 .version = "0", 74 .irq = 60, 75 }; 76 77 static struct resource vpu_resources[] = { 78 [0] = { 79 .name = "VPU", 80 .start = 0xfe900000, 81 .end = 0xfe902807, 82 .flags = IORESOURCE_MEM, 83 }, 84 [1] = { 85 /* place holder for contiguous memory */ 86 }, 87 }; 88 89 static struct platform_device vpu_device = { 90 .name = "uio_pdrv_genirq", 91 .id = 0, 92 .dev = { 93 .platform_data = &vpu_platform_data, 94 }, 95 .resource = vpu_resources, 96 .num_resources = ARRAY_SIZE(vpu_resources), 97 }; 98 99 static struct uio_info veu0_platform_data = { 100 .name = "VEU", 101 .version = "0", 102 .irq = 54, 103 }; 104 105 static struct resource veu0_resources[] = { 106 [0] = { 107 .name = "VEU(1)", 108 .start = 0xfe920000, 109 .end = 0xfe9200b7, 110 .flags = IORESOURCE_MEM, 111 }, 112 [1] = { 113 /* place holder for contiguous memory */ 114 }, 115 }; 116 117 static struct platform_device veu0_device = { 118 .name = "uio_pdrv_genirq", 119 .id = 1, 120 .dev = { 121 .platform_data = &veu0_platform_data, 122 }, 123 .resource = veu0_resources, 124 .num_resources = ARRAY_SIZE(veu0_resources), 125 }; 126 127 static struct uio_info veu1_platform_data = { 128 .name = "VEU", 129 .version = "0", 130 .irq = 27, 131 }; 132 133 static struct resource veu1_resources[] = { 134 [0] = { 135 .name = "VEU(2)", 136 .start = 0xfe924000, 137 .end = 0xfe9240b7, 138 .flags = IORESOURCE_MEM, 139 }, 140 [1] = { 141 /* place holder for contiguous memory */ 142 }, 143 }; 144 145 static struct platform_device veu1_device = { 146 .name = "uio_pdrv_genirq", 147 .id = 2, 148 .dev = { 149 .platform_data = &veu1_platform_data, 150 }, 151 .resource = veu1_resources, 152 .num_resources = ARRAY_SIZE(veu1_resources), 153 }; 154 155 static struct sh_timer_config cmt_platform_data = { 156 .name = "CMT", 157 .channel_offset = 0x60, 158 .timer_bit = 5, 159 .clk = "cmt0", 160 .clockevent_rating = 125, 161 .clocksource_rating = 200, 162 }; 163 164 static struct resource cmt_resources[] = { 165 [0] = { 166 .name = "CMT", 167 .start = 0x044a0060, 168 .end = 0x044a006b, 169 .flags = IORESOURCE_MEM, 170 }, 171 [1] = { 172 .start = 104, 173 .flags = IORESOURCE_IRQ, 174 }, 175 }; 176 177 static struct platform_device cmt_device = { 178 .name = "sh_cmt", 179 .id = 0, 180 .dev = { 181 .platform_data = &cmt_platform_data, 182 }, 183 .resource = cmt_resources, 184 .num_resources = ARRAY_SIZE(cmt_resources), 185 }; 186 187 static struct sh_timer_config tmu0_platform_data = { 188 .name = "TMU0", 189 .channel_offset = 0x04, 190 .timer_bit = 0, 191 .clk = "tmu0", 192 .clockevent_rating = 200, 193 }; 194 195 static struct resource tmu0_resources[] = { 196 [0] = { 197 .name = "TMU0", 198 .start = 0xffd80008, 199 .end = 0xffd80013, 200 .flags = IORESOURCE_MEM, 201 }, 202 [1] = { 203 .start = 16, 204 .flags = IORESOURCE_IRQ, 205 }, 206 }; 207 208 static struct platform_device tmu0_device = { 209 .name = "sh_tmu", 210 .id = 0, 211 .dev = { 212 .platform_data = &tmu0_platform_data, 213 }, 214 .resource = tmu0_resources, 215 .num_resources = ARRAY_SIZE(tmu0_resources), 216 }; 217 218 static struct sh_timer_config tmu1_platform_data = { 219 .name = "TMU1", 220 .channel_offset = 0x10, 221 .timer_bit = 1, 222 .clk = "tmu0", 223 .clocksource_rating = 200, 224 }; 225 226 static struct resource tmu1_resources[] = { 227 [0] = { 228 .name = "TMU1", 229 .start = 0xffd80014, 230 .end = 0xffd8001f, 231 .flags = IORESOURCE_MEM, 232 }, 233 [1] = { 234 .start = 17, 235 .flags = IORESOURCE_IRQ, 236 }, 237 }; 238 239 static struct platform_device tmu1_device = { 240 .name = "sh_tmu", 241 .id = 1, 242 .dev = { 243 .platform_data = &tmu1_platform_data, 244 }, 245 .resource = tmu1_resources, 246 .num_resources = ARRAY_SIZE(tmu1_resources), 247 }; 248 249 static struct sh_timer_config tmu2_platform_data = { 250 .name = "TMU2", 251 .channel_offset = 0x1c, 252 .timer_bit = 2, 253 .clk = "tmu0", 254 }; 255 256 static struct resource tmu2_resources[] = { 257 [0] = { 258 .name = "TMU2", 259 .start = 0xffd80020, 260 .end = 0xffd8002b, 261 .flags = IORESOURCE_MEM, 262 }, 263 [1] = { 264 .start = 18, 265 .flags = IORESOURCE_IRQ, 266 }, 267 }; 268 269 static struct platform_device tmu2_device = { 270 .name = "sh_tmu", 271 .id = 2, 272 .dev = { 273 .platform_data = &tmu2_platform_data, 274 }, 275 .resource = tmu2_resources, 276 .num_resources = ARRAY_SIZE(tmu2_resources), 277 }; 278 279 static struct plat_sci_port sci_platform_data[] = { 280 { 281 .mapbase = 0xffe00000, 282 .flags = UPF_BOOT_AUTOCONF, 283 .type = PORT_SCIF, 284 .irqs = { 80, 80, 80, 80 }, 285 .clk = "scif0", 286 }, { 287 .flags = 0, 288 } 289 }; 290 291 static struct platform_device sci_device = { 292 .name = "sh-sci", 293 .id = -1, 294 .dev = { 295 .platform_data = sci_platform_data, 296 }, 297 }; 298 299 static struct platform_device *sh7366_devices[] __initdata = { 300 &cmt_device, 301 &tmu0_device, 302 &tmu1_device, 303 &tmu2_device, 304 &iic_device, 305 &sci_device, 306 &usb_host_device, 307 &vpu_device, 308 &veu0_device, 309 &veu1_device, 310 }; 311 312 static int __init sh7366_devices_setup(void) 313 { 314 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 315 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 316 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 317 318 return platform_add_devices(sh7366_devices, 319 ARRAY_SIZE(sh7366_devices)); 320 } 321 arch_initcall(sh7366_devices_setup); 322 323 static struct platform_device *sh7366_early_devices[] __initdata = { 324 &cmt_device, 325 &tmu0_device, 326 &tmu1_device, 327 &tmu2_device, 328 }; 329 330 void __init plat_early_device_setup(void) 331 { 332 early_platform_add_devices(sh7366_early_devices, 333 ARRAY_SIZE(sh7366_early_devices)); 334 } 335 336 enum { 337 UNUSED=0, 338 339 /* interrupt sources */ 340 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 341 ICB, 342 DMAC0, DMAC1, DMAC2, DMAC3, 343 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU, 344 MFI, VPU, USB, 345 MMC_MMC1I, MMC_MMC2I, MMC_MMC3I, 346 DMAC4, DMAC5, DMAC_DADERR, 347 SCIF, SCIFA1, SCIFA2, 348 DENC, MSIOF, 349 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 350 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI, 351 SDHI0, SDHI1, SDHI2, SDHI3, 352 CMT, TSIF, SIU, 353 TMU0, TMU1, TMU2, 354 VEU2, LCDC, 355 356 /* interrupt groups */ 357 358 DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C, SDHI, 359 }; 360 361 static struct intc_vect vectors[] __initdata = { 362 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 363 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 364 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 365 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 366 INTC_VECT(ICB, 0x700), 367 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820), 368 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860), 369 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0), 370 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0), 371 INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), INTC_VECT(USB, 0xa20), 372 INTC_VECT(MMC_MMC1I, 0xb00), INTC_VECT(MMC_MMC2I, 0xb20), 373 INTC_VECT(MMC_MMC3I, 0xb40), 374 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0), 375 INTC_VECT(DMAC_DADERR, 0xbc0), 376 INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIFA1, 0xc20), 377 INTC_VECT(SCIFA2, 0xc40), 378 INTC_VECT(DENC, 0xc60), INTC_VECT(MSIOF, 0xc80), 379 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0), 380 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), 381 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20), 382 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60), 383 INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0), 384 INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0), 385 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), 386 INTC_VECT(SIU, 0xf80), 387 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 388 INTC_VECT(TMU2, 0x440), 389 INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580), 390 }; 391 392 static struct intc_group groups[] __initdata = { 393 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), 394 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU), 395 INTC_GROUP(MMC, MMC_MMC1I, MMC_MMC2I, MMC_MMC3I), 396 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR), 397 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, 398 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 399 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI), 400 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3), 401 }; 402 403 static struct intc_mask_reg mask_registers[] __initdata = { 404 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 405 { } }, 406 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 407 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } }, 408 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 409 { 0, 0, 0, VPU, 0, 0, 0, MFI } }, 410 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 411 { 0, 0, 0, ICB } }, 412 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 413 { 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } }, 414 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 415 { 0, DMAC_DADERR, DMAC5, DMAC4, DENC, SCIFA2, SCIFA1, SCIF } }, 416 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 417 { 0, 0, 0, 0, 0, 0, 0, MSIOF } }, 418 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 419 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 420 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 421 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 422 { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } }, 423 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 424 { 0, 0, 0, CMT, 0, USB, } }, 425 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 426 { 0, MMC_MMC3I, MMC_MMC2I, MMC_MMC1I } }, 427 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 428 { 0, 0, 0, 0, 0, 0, 0, TSIF } }, 429 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 430 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 431 }; 432 433 static struct intc_prio_reg prio_registers[] __initdata = { 434 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } }, 435 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } }, 436 { 0xa4080008, 0, 16, 4, /* IPRC */ { } }, 437 { 0xa408000c, 0, 16, 4, /* IPRD */ { } }, 438 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } }, 439 { 0xa4080014, 0, 16, 4, /* IPRF */ { 0, DMAC45, USB, CMT } }, 440 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIFA1, SCIFA2, DENC } }, 441 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF, 0, FLCTL, I2C } }, 442 { 0xa4080020, 0, 16, 4, /* IPRI */ { 0, 0, TSIF, } }, 443 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } }, 444 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } }, 445 { 0xa408002c, 0, 16, 4, /* IPRL */ { } }, 446 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 447 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 448 }; 449 450 static struct intc_sense_reg sense_registers[] __initdata = { 451 { 0xa414001c, 16, 2, /* ICR1 */ 452 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 453 }; 454 455 static struct intc_mask_reg ack_registers[] __initdata = { 456 { 0xa4140024, 0, 8, /* INTREQ00 */ 457 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 458 }; 459 460 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7366", vectors, groups, 461 mask_registers, prio_registers, sense_registers, 462 ack_registers); 463 464 void __init plat_irq_setup(void) 465 { 466 register_intc_controller(&intc_desc); 467 } 468 469 void __init plat_mem_setup(void) 470 { 471 /* TODO: Register Node 1 */ 472 } 473