1 /*
2  * SH7366 Setup
3  *
4  *  Copyright (C) 2008 Renesas Solutions
5  *
6  * Based on linux/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
7  *
8  * This file is subject to the terms and conditions of the GNU General Public
9  * License.  See the file "COPYING" in the main directory of this archive
10  * for more details.
11  */
12 #include <linux/platform_device.h>
13 #include <linux/init.h>
14 #include <linux/serial.h>
15 #include <linux/serial_sci.h>
16 #include <linux/uio_driver.h>
17 #include <linux/sh_timer.h>
18 #include <linux/usb/r8a66597.h>
19 #include <asm/clock.h>
20 
21 static struct plat_sci_port scif0_platform_data = {
22 	.mapbase	= 0xffe00000,
23 	.flags		= UPF_BOOT_AUTOCONF,
24 	.type		= PORT_SCIF,
25 	.irqs		= { 80, 80, 80, 80 },
26 	.clk		= "scif0",
27 };
28 
29 static struct platform_device scif0_device = {
30 	.name		= "sh-sci",
31 	.id		= 0,
32 	.dev		= {
33 		.platform_data	= &scif0_platform_data,
34 	},
35 };
36 
37 static struct resource iic_resources[] = {
38 	[0] = {
39 		.name	= "IIC",
40 		.start  = 0x04470000,
41 		.end    = 0x04470017,
42 		.flags  = IORESOURCE_MEM,
43 	},
44 	[1] = {
45 		.start  = 96,
46 		.end    = 99,
47 		.flags  = IORESOURCE_IRQ,
48        },
49 };
50 
51 static struct platform_device iic_device = {
52 	.name           = "i2c-sh_mobile",
53 	.id             = 0, /* "i2c0" clock */
54 	.num_resources  = ARRAY_SIZE(iic_resources),
55 	.resource       = iic_resources,
56 };
57 
58 static struct r8a66597_platdata r8a66597_data = {
59 	.on_chip = 1,
60 };
61 
62 static struct resource usb_host_resources[] = {
63 	[0] = {
64 		.start  = 0xa4d80000,
65 		.end    = 0xa4d800ff,
66 		.flags  = IORESOURCE_MEM,
67 	},
68 	[1] = {
69 		.start  = 65,
70 		.end    = 65,
71 		.flags	= IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
72 	},
73 };
74 
75 static struct platform_device usb_host_device = {
76 	.name	= "r8a66597_hcd",
77 	.id	= -1,
78 	.dev = {
79 		.dma_mask		= NULL,
80 		.coherent_dma_mask	= 0xffffffff,
81 		.platform_data		= &r8a66597_data,
82 	},
83 	.num_resources	= ARRAY_SIZE(usb_host_resources),
84 	.resource	= usb_host_resources,
85 };
86 
87 static struct uio_info vpu_platform_data = {
88 	.name = "VPU5",
89 	.version = "0",
90 	.irq = 60,
91 };
92 
93 static struct resource vpu_resources[] = {
94 	[0] = {
95 		.name	= "VPU",
96 		.start	= 0xfe900000,
97 		.end	= 0xfe902807,
98 		.flags	= IORESOURCE_MEM,
99 	},
100 	[1] = {
101 		/* place holder for contiguous memory */
102 	},
103 };
104 
105 static struct platform_device vpu_device = {
106 	.name		= "uio_pdrv_genirq",
107 	.id		= 0,
108 	.dev = {
109 		.platform_data	= &vpu_platform_data,
110 	},
111 	.resource	= vpu_resources,
112 	.num_resources	= ARRAY_SIZE(vpu_resources),
113 };
114 
115 static struct uio_info veu0_platform_data = {
116 	.name = "VEU",
117 	.version = "0",
118 	.irq = 54,
119 };
120 
121 static struct resource veu0_resources[] = {
122 	[0] = {
123 		.name	= "VEU(1)",
124 		.start	= 0xfe920000,
125 		.end	= 0xfe9200b7,
126 		.flags	= IORESOURCE_MEM,
127 	},
128 	[1] = {
129 		/* place holder for contiguous memory */
130 	},
131 };
132 
133 static struct platform_device veu0_device = {
134 	.name		= "uio_pdrv_genirq",
135 	.id		= 1,
136 	.dev = {
137 		.platform_data	= &veu0_platform_data,
138 	},
139 	.resource	= veu0_resources,
140 	.num_resources	= ARRAY_SIZE(veu0_resources),
141 };
142 
143 static struct uio_info veu1_platform_data = {
144 	.name = "VEU",
145 	.version = "0",
146 	.irq = 27,
147 };
148 
149 static struct resource veu1_resources[] = {
150 	[0] = {
151 		.name	= "VEU(2)",
152 		.start	= 0xfe924000,
153 		.end	= 0xfe9240b7,
154 		.flags	= IORESOURCE_MEM,
155 	},
156 	[1] = {
157 		/* place holder for contiguous memory */
158 	},
159 };
160 
161 static struct platform_device veu1_device = {
162 	.name		= "uio_pdrv_genirq",
163 	.id		= 2,
164 	.dev = {
165 		.platform_data	= &veu1_platform_data,
166 	},
167 	.resource	= veu1_resources,
168 	.num_resources	= ARRAY_SIZE(veu1_resources),
169 };
170 
171 static struct sh_timer_config cmt_platform_data = {
172 	.name = "CMT",
173 	.channel_offset = 0x60,
174 	.timer_bit = 5,
175 	.clk = "cmt0",
176 	.clockevent_rating = 125,
177 	.clocksource_rating = 200,
178 };
179 
180 static struct resource cmt_resources[] = {
181 	[0] = {
182 		.name	= "CMT",
183 		.start	= 0x044a0060,
184 		.end	= 0x044a006b,
185 		.flags	= IORESOURCE_MEM,
186 	},
187 	[1] = {
188 		.start	= 104,
189 		.flags	= IORESOURCE_IRQ,
190 	},
191 };
192 
193 static struct platform_device cmt_device = {
194 	.name		= "sh_cmt",
195 	.id		= 0,
196 	.dev = {
197 		.platform_data	= &cmt_platform_data,
198 	},
199 	.resource	= cmt_resources,
200 	.num_resources	= ARRAY_SIZE(cmt_resources),
201 };
202 
203 static struct sh_timer_config tmu0_platform_data = {
204 	.name = "TMU0",
205 	.channel_offset = 0x04,
206 	.timer_bit = 0,
207 	.clk = "tmu0",
208 	.clockevent_rating = 200,
209 };
210 
211 static struct resource tmu0_resources[] = {
212 	[0] = {
213 		.name	= "TMU0",
214 		.start	= 0xffd80008,
215 		.end	= 0xffd80013,
216 		.flags	= IORESOURCE_MEM,
217 	},
218 	[1] = {
219 		.start	= 16,
220 		.flags	= IORESOURCE_IRQ,
221 	},
222 };
223 
224 static struct platform_device tmu0_device = {
225 	.name		= "sh_tmu",
226 	.id		= 0,
227 	.dev = {
228 		.platform_data	= &tmu0_platform_data,
229 	},
230 	.resource	= tmu0_resources,
231 	.num_resources	= ARRAY_SIZE(tmu0_resources),
232 };
233 
234 static struct sh_timer_config tmu1_platform_data = {
235 	.name = "TMU1",
236 	.channel_offset = 0x10,
237 	.timer_bit = 1,
238 	.clk = "tmu0",
239 	.clocksource_rating = 200,
240 };
241 
242 static struct resource tmu1_resources[] = {
243 	[0] = {
244 		.name	= "TMU1",
245 		.start	= 0xffd80014,
246 		.end	= 0xffd8001f,
247 		.flags	= IORESOURCE_MEM,
248 	},
249 	[1] = {
250 		.start	= 17,
251 		.flags	= IORESOURCE_IRQ,
252 	},
253 };
254 
255 static struct platform_device tmu1_device = {
256 	.name		= "sh_tmu",
257 	.id		= 1,
258 	.dev = {
259 		.platform_data	= &tmu1_platform_data,
260 	},
261 	.resource	= tmu1_resources,
262 	.num_resources	= ARRAY_SIZE(tmu1_resources),
263 };
264 
265 static struct sh_timer_config tmu2_platform_data = {
266 	.name = "TMU2",
267 	.channel_offset = 0x1c,
268 	.timer_bit = 2,
269 	.clk = "tmu0",
270 };
271 
272 static struct resource tmu2_resources[] = {
273 	[0] = {
274 		.name	= "TMU2",
275 		.start	= 0xffd80020,
276 		.end	= 0xffd8002b,
277 		.flags	= IORESOURCE_MEM,
278 	},
279 	[1] = {
280 		.start	= 18,
281 		.flags	= IORESOURCE_IRQ,
282 	},
283 };
284 
285 static struct platform_device tmu2_device = {
286 	.name		= "sh_tmu",
287 	.id		= 2,
288 	.dev = {
289 		.platform_data	= &tmu2_platform_data,
290 	},
291 	.resource	= tmu2_resources,
292 	.num_resources	= ARRAY_SIZE(tmu2_resources),
293 };
294 
295 static struct platform_device *sh7366_devices[] __initdata = {
296 	&scif0_device,
297 	&cmt_device,
298 	&tmu0_device,
299 	&tmu1_device,
300 	&tmu2_device,
301 	&iic_device,
302 	&usb_host_device,
303 	&vpu_device,
304 	&veu0_device,
305 	&veu1_device,
306 };
307 
308 static int __init sh7366_devices_setup(void)
309 {
310 	platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
311 	platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
312 	platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
313 
314 	return platform_add_devices(sh7366_devices,
315 				    ARRAY_SIZE(sh7366_devices));
316 }
317 arch_initcall(sh7366_devices_setup);
318 
319 static struct platform_device *sh7366_early_devices[] __initdata = {
320 	&scif0_device,
321 	&cmt_device,
322 	&tmu0_device,
323 	&tmu1_device,
324 	&tmu2_device,
325 };
326 
327 void __init plat_early_device_setup(void)
328 {
329 	early_platform_add_devices(sh7366_early_devices,
330 				   ARRAY_SIZE(sh7366_early_devices));
331 }
332 
333 enum {
334 	UNUSED=0,
335 
336 	/* interrupt sources */
337 	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
338 	ICB,
339 	DMAC0, DMAC1, DMAC2, DMAC3,
340 	VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
341 	MFI, VPU, USB,
342 	MMC_MMC1I, MMC_MMC2I, MMC_MMC3I,
343 	DMAC4, DMAC5, DMAC_DADERR,
344 	SCIF, SCIFA1, SCIFA2,
345 	DENC, MSIOF,
346 	FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
347 	I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
348 	SDHI0, SDHI1, SDHI2, SDHI3,
349 	CMT, TSIF, SIU,
350 	TMU0, TMU1, TMU2,
351 	VEU2, LCDC,
352 
353 	/* interrupt groups */
354 
355 	DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C, SDHI,
356 };
357 
358 static struct intc_vect vectors[] __initdata = {
359 	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
360 	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
361 	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
362 	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
363 	INTC_VECT(ICB, 0x700),
364 	INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
365 	INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
366 	INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
367 	INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
368 	INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), INTC_VECT(USB, 0xa20),
369 	INTC_VECT(MMC_MMC1I, 0xb00), INTC_VECT(MMC_MMC2I, 0xb20),
370 	INTC_VECT(MMC_MMC3I, 0xb40),
371 	INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
372 	INTC_VECT(DMAC_DADERR, 0xbc0),
373 	INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIFA1, 0xc20),
374 	INTC_VECT(SCIFA2, 0xc40),
375 	INTC_VECT(DENC, 0xc60), INTC_VECT(MSIOF, 0xc80),
376 	INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
377 	INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
378 	INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
379 	INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
380 	INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
381 	INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
382 	INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
383 	INTC_VECT(SIU, 0xf80),
384 	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
385 	INTC_VECT(TMU2, 0x440),
386 	INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580),
387 };
388 
389 static struct intc_group groups[] __initdata = {
390 	INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
391 	INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
392 	INTC_GROUP(MMC, MMC_MMC1I, MMC_MMC2I, MMC_MMC3I),
393 	INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
394 	INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
395 		   FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
396 	INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
397 	INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
398 };
399 
400 static struct intc_mask_reg mask_registers[] __initdata = {
401 	{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
402 	  { } },
403 	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
404 	  { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
405 	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
406 	  { 0, 0, 0, VPU, 0, 0, 0, MFI } },
407 	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
408 	  { 0, 0, 0, ICB } },
409 	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
410 	  { 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } },
411 	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
412 	  { 0, DMAC_DADERR, DMAC5, DMAC4, DENC, SCIFA2, SCIFA1, SCIF } },
413 	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
414 	  { 0, 0, 0, 0, 0, 0, 0, MSIOF } },
415 	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
416 	  { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
417 	    FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
418 	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
419 	  { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } },
420 	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
421 	  { 0, 0, 0, CMT, 0, USB, } },
422 	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
423 	  { 0, MMC_MMC3I, MMC_MMC2I, MMC_MMC1I } },
424 	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
425 	  { 0, 0, 0, 0, 0, 0, 0, TSIF } },
426 	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
427 	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
428 };
429 
430 static struct intc_prio_reg prio_registers[] __initdata = {
431 	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
432 	{ 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } },
433 	{ 0xa4080008, 0, 16, 4, /* IPRC */ { } },
434 	{ 0xa408000c, 0, 16, 4, /* IPRD */ { } },
435 	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
436 	{ 0xa4080014, 0, 16, 4, /* IPRF */ { 0, DMAC45, USB, CMT } },
437 	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIFA1, SCIFA2, DENC } },
438 	{ 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF, 0, FLCTL, I2C } },
439 	{ 0xa4080020, 0, 16, 4, /* IPRI */ { 0, 0, TSIF, } },
440 	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
441 	{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
442 	{ 0xa408002c, 0, 16, 4, /* IPRL */ { } },
443 	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
444 	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
445 };
446 
447 static struct intc_sense_reg sense_registers[] __initdata = {
448 	{ 0xa414001c, 16, 2, /* ICR1 */
449 	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
450 };
451 
452 static struct intc_mask_reg ack_registers[] __initdata = {
453 	{ 0xa4140024, 0, 8, /* INTREQ00 */
454 	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
455 };
456 
457 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7366", vectors, groups,
458 			     mask_registers, prio_registers, sense_registers,
459 			     ack_registers);
460 
461 void __init plat_irq_setup(void)
462 {
463 	register_intc_controller(&intc_desc);
464 }
465 
466 void __init plat_mem_setup(void)
467 {
468 	/* TODO: Register Node 1 */
469 }
470